ULTRACHIP The Coolest LCD Driver, Ever! HIGH-VOLTAGE MIXED-SIGNAL IC. 65x132 STN Controller-Driver

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1 Crystalfontz Thiscontrolerdatasheetwasdownloadedfrom htp:/wwwcrystalfontzcom/controlers/ HIGH-VOLTAGE MIXED-SIGNAL IC 65x132 STN Controller-Driver Preliminary Specifications January 3, 27 Revision 6 ULTRACHIP The Coolest LCD Driver, Ever! Specifications and information herein are subject to change without notice

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3 UC161S 65x132 STN Controller-Drivers Table of Content INTRODUCTION 1 MAIN APPLICATIONS1 FEATURE HIGHLIGHTS 1 ORDERING INFORMATION 2 BLOCK DIAGRAM3 PIN DESCRIPTION 4 RECOMMENDED COG LAYOUT7 CONTROL REGISTERS8 COMMAND TABLE 1 COMMAND DESCRIPTION11 LCD VOLTAGE SETTING 18 V LCD QUICK REFERENCE19 LCD DISPLAY CONTROLS21 ITO LAYOUT AND LC SELECTION22 HOST INTERFACE24 DISPLAY DATA RAM (DDRAM)32 RESET & POWER MANAGEMENT 34 ESD CONSIDERATION37 ABSOLUTE MAXIMUM RATINGS 38 SPECIFICATIONS 39 AC CHARACTERISTICS4 PHYSICAL DIMENSIONS5 ALIGNMENT MARK INFORMATION 51 PAD COORDINATES 52 TRAY INFORMATION55 REVISION HISTORY 56 Revision A_1-1 -

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5 UC161S 65x132 STN Controller-Drivers UC161s Single-Chip, Ultra-Low Power 65COM by 132SEG Passive Matrix LCD Controller-Driver INTRODUCTION UC161s is an advanced high-voltage mixedsignal CMOS IC, especially designed for the display needs of ultra-low power hand-held devices This chip employs UltraChip s unique DCC (Direct Capacitor Coupling) driver architecture to achieve near crosstalk free images In addition to low power column and row drivers, the IC contains all necessary circuits for high-v LCD power supply, bias voltage generation, timing generation and graphics data memory Advanced circuit design techniques are employed to minimize external component counts and reduce connector size while achieving extremely low power consumption MAIN APPLICATIONS Cellular Phones, Smart Phones, PDA, and other battery operated palm top devices or portable Instruments FEATURE HIGHLIGHTS Single chip controller-driver support 65x132 graphics STN LCD panels Support both row ordered and column ordered display buffer RAM access A software-readable ID pin to support configurable vender identification Support both row-ordered and columnordered display buffer RAM access Support industry standard 8-bit parallel bus (88 or 68 mode), 4-wire and 3-wire serial buses (S8 and S9), and 2-wire I 2 C serial interface Ultra-low power consumption under all display patterns Fully programmable Mux Rate, partial display, Bias Ratio and Frame Rate allow many flexible power management options Software programmable frame rates at 8 and 1 Hz Four software programmable temperature compensation coefficients 7-x internal charge pump with on-chip pumping capacitor requires only 3 external capacitors to operate On-chip Power-ON Reset and Software RESET commands, make RST pin optional Very low pin count (1-pin) allows exceptional image quality in COG format on conventional ITO glass Flexible data addressing/mapping schemes to support wide ranges of software models and LCD layout placements V DD (digital) range: 18V (Typ) ~ 33V V DD (analog) range: 25V (Typ) ~ 33V LCD V OP range: 47V ~ 115V Available in gold bump dies COM/SEG bump information Bump pitch: 355 µm Bump gap: 13 µm Bump surface: 225 µm 2 Revision A_6 1

6 ULTRACHIP High-Voltage Mixed-Signal IC 1999~27 ORDERING INFORMATION Part Number I 2 C Description UC161sGAA Yes Gold Bumped Die General Notes APPLICATION INFORMATION For improved readability, the specification contains many application data points When application information is given, it is advisory and does not form part of the specification for the device USE OF I 2 C The implementation of I 2 C is already included and tested in all silicon However, unless I 2 C licensing obligation is executed satisfactorily, it is not legal to use UltraChip product for I 2 C applications Unless I 2 C version is ordered from UltraChip, the customer will take the responsibility for all such licensing liabilities BARE DIE DISCLAIMER All die are tested and are guaranteed to comply with all data sheet limits up to the point of There is no post waffle saw/pack testing performed on individual die Although the latest modern processes are utilized for wafer sawing and die pick-&-place into waffle pack carriers, UltraChip has no control of third party procedures in the handling, packing or assembly of the die Accordingly, it is the responsibility of the customer to test and qualify their application in which the die is to be used UltraChip assumes no liability for device functionality or performance of the die or systems after handling, packing or assembly of the die LIFE SUPPORT APPLICATIONS These devices are not designed for use in life support appliances, or systems where malfunction of these products can reasonably be expected to result in personal injuries Customer using or selling these products for use in such applications do so at their own risk CONTENT DISCLAIMER UltraChip believes the information contained in this document to be accurate and reliable However, it is subject to change without notice No responsibility is assumed by UltraChip for its use, nor for infringement of patents or other rights of third parties No part of this publication may be reproduced, or transmitted in any form or by any means without the prior consent of UltraChip Inc UltraChip's terms and conditions of sale apply at all times CONTACT DETAILS UltraChip Inc (Headquarter) 2F, No 7, Chowtze Street, Nei Hu District, Taipei 114, Taiwan, R O C Tel: +886 (2) Fax: +886 (2) Sales sales@ultrachipcom Web site: 2 ES Specifications

7 UC161S 65x132 STN Controller-Drivers BLOCK DIAGRAM COLUMN ADDRESS GENERATOR POWER ON & RESET CONTROL CLOCK & TIMING GENERATOR CONTROL & STATUS REGISTER PAGE ADDRESS GENERATOR DATA RAM I/O BUFFER DISPLAY DATA RAM ROW ADDRESS GENERATOR LEVEL SHIFTER COM DRIVERS DISPLAY DATA LATCHES COMMAND HOST INTERFACE LEVEL SHIFTERS SEG DRIVERS V LCD & BIAS GENERATOR C L C B C B1 Revision A_6 3

8 ULTRACHIP High-Voltage Mixed-Signal IC 1999~27 PIN DESCRIPTION Name Type Pins Description MAIN POWER SUPPLY V DD supplies for Display Data RAM and digital logic, V DD2 supplies for V LCD and V D generator, V DD3 supplies for V BIAS and other analog circuits V DD2 /V DD3 should be connected to the same power source But V DD can be connected to a source voltage no higher than V DD2 /V DD3 Please maintain the following relationship: V DD +13V V DD2/3 V DD ITO trace resistance needs to be minimized for V DD2 /V DD3 V DD V DD2 V DD3 PWR V SS V SS2 GND 4 4 Ground Connect V SS and V SS2 to the shared GND pin In COG applications, minimize the ITO resistance for both V SS and V SS2 LCD POWER SUPPLY & VOLTAGE CONTROL V B1+ V B1 V B+ V B PWR LCD Bias Voltages These are the voltage sources to provide SEG driving currents These voltages are generated internally Connect capacitors of C BX value between V BX+ and V BX In COG application, the resistance of these ITO traces directly affects the SEG driving strength of the resulting LCD module Minimize these trace resistance is critical in achieving high quality image V LCDIN V LCDOUT PWR 1 1 Main LCD Power Supply When internal V LCD is used, connect these pins together When external V LCD source is used, connect external V LCD source to V LCDIN pins and leave V LCDOUT open By-pass capacitor C L is optional It can be connected between V LCD and V SS When C L is used, keep the ITO trace resistance around 7 Ω NOTE Recommended capacitor values: C B : 22µF/5V or 3x(LCD load capacitance), whichever is higher C L : 33nF/25V is appropriate for most applications 4 ES Specifications

9 UC161S 65x132 STN Controller-Drivers Name Type Pins Description HOST INTERFACE Bus mode: The interface bus mode is determined by BM[1:] and {DB7, DB6} by the following relationship: BM[1:] {DB7, DB6} Mode 11 Data 68/8-bit BM BM1 I Data 88/8-bit 1 4-wire SPI w/ 8-bit token (S8: conventional) wire SPI w/ 9-bit token (S9: conventional) wire serial (I 2 C) CS1/A3 CS/A2 I 1 1 RST I 1 CD I 1 ID I 1 WR WR1 I 1 1 D~D7 I/O 8 Chip Select Chip is selected when CS1= H and CS = L When the chip is not selected, D[15:] will be of high impedance In I 2 C mode, these two pins specifies bits 3~2 of UC161s device address (A[3:2]) When RST= L, all control registers are re-initialized by their default states Since UC161s has built-in Power-On Reset and Software Reset command, RST pin is not required for proper chip operation An RC Filter has been included on-chip There is no need for external RC noise filter When RST is not used, connect the pin to V DD Select Control data or Display data for read/write operation In S9, CD pin is not used Connect CD to V SS when not used L : Control data H : Display data ID may be used for production identification Connect ID to V DD for H or V SS for L WR [1:] controls the read/write operation of the host interface See Host Interface section for details In parallel mode, the meaning of WR[1:] depends on which interface it is in, 68 or 88 mode In serial interface modes, these two pins are not used, Connect them to V SS Bi-directional bus for both serial and parallel host interfaces In serial modes, connect D[] to SCK, D[3] to SDA BM=1x (8-bit) BM= (S8) BM=1 (S9) BM=1 (I 2 C) D D SCK SCK SCK D1 D D2 D D3 D3 SDA SDA SDA D4 D D5 D D6 D6 1 D7 D Always connect unused pins to either V SS or V DD Revision A_6 5

10 ULTRACHIP High-Voltage Mixed-Signal IC 1999~27 Name Type Pins Description SEG1 ~ SEG132 HV HIGH VOLTAGE LCD DRIVER OUTPUT 132 SEG (column) driver outputs Support up to 132 pixels Leave unused SEG drivers open-circuit 64 COM (row) driver outputs Support up to 64 rows COM1 ~ HV When designing LCM, always start from COM1 If the LCM has N pixel COM64 rows and N is less than 64, set CEN to be N-1, and leave COM drivers [N+1 ~ 64] open-circuit CIC HV 2 Icon driver outputs Leave it open if not used V DDX 1 TST4 I 1 TST2 TST1 I/O 1 1 MISC PINS Auxiliary V DD This pin is connected to the main V DD bus within the IC It s provided to facilitate chip configurations in COG application There s no need to connect V DDX to main V DD externally and it should NOT be used to provide V DD power to the chip Test control There s an on-chip pull-up resistor for TST4 Connect to GND during normal operation Test I/O pins Leave these pins open during normal use Note: 1 Several control registers will specify based index for COM and SEG electrodes In those situations, COMX or SEGX will correspond to index X-1, and the value range for those index register will be ~63 for COM and ~131 for SEG 6 ES Specifications

11 UC161S 65x132 STN Controller-Drivers RECOMMENDED COG LAYOUT CS RST CD WR WR1 D D1 D2 D3 D4 D5 D6 D7 BM BM1 ID UC161s Bump View VDD VSS TST4 VB1+ VB1- VB- VB+ VLCD NOTES FOR V DD WITH COG: The operation condition, V DD =18V (typical), should be satisfied under all operating conditions UC161s peak current (I DD ) can be up to ~15mA during high speed data-write to UC161s on-chip SRAM Such high pulsing current mandates very careful design of V DD and V SS ITO trances in COG modules When V DD and V SS trace resistance is not low enough, the pulsing I DD current can cause the actual on-chip V DD to drop to below 165V and cause the IC to malfunction Revision A_6 7

12 ULTRACHIP High-Voltage Mixed-Signal IC 1999~27 CONTROL REGISTERS UC161s contains registers, which control the chip operation The following table is a summary of these control registers, a brief description and the default values These registers can be modified by commands, which will be described in the next two sections, Command Table and Command Description Name: Default: The Symbolic reference of the register Note that, some symbol name refers to bits (flags) within another register Numbers shown in Bold font are default values after Power-Up-Reset and System-Reset Name Bits Default Description SL 6 H Scroll Line Scroll the displayed image up by SL rows The valid SL value is between (for no scrolling) and 63 Setting SL outside of this range causes undefined effects on the displayed image This register does not affect icon output CIC CA 8 H Column Address of DDRAM (Display Data RAM) Value range is ~131 (Used in Host to access DDRAM) PA 4 H Page Address of DDRAM Value range ~8 (Used in Host to access DDRAM) BR 2 3H Bias Ratio The ratio between V LCD and V D : 6 1: 7 1: 8 11: 9 TC 2 H Temperature Compensation (per o C) : -5% 1: -1% 1: -15% 11: -% PM 8 CH Electronic Potentiometer to fine tune the value of V LCD PC 3 6H Power Control PC []: : LCD: 15nF 1: LCD: 15~24nF PC [2:1]: : External V LCD 11: Internal V LCD (7x charge pump) AC 3 1H Address Control AC[]: WA: automatic column/page Wrap Around (Default 1: ON) AC[1]: Auto-Increment order : Column (CA) first 1: Page (PA) first AC[2]: PID: PA (page address) auto Increment Direction (:+1 1:-1) DC 3 H Display Control: DC[]: PXV: Pixels Inverse (bit-wise data inversion Default : OFF) DC[1]: APO: All Pixels ON (Default : OFF) DC[2]: Display ON/OFF (Default : OFF) When DC[2] is set to, the IC will enter Sleep Mode 8 ES Specifications

13 UC161S 65x132 STN Controller-Drivers Name Bits Default Description LC 5 H LCD Control: LC[]: Reserved LC[1]: MX, Mirror X SEG/Column sequence inversion (Default: OFF) LC[2]: MY, Mirror Y COM/Row sequence inversion (Default: OFF) LC[3]: Frame Rate b: 8 fps 1b: 1 fps LC[4]: Partial Display control b: Disable Mux-Rate = CEN+1 (DST, DEN not used) 1b: Enabled Mux-Rate = DEN-DST+1 CEN DST DEN FH H 3FH COM-scanning End (last COM with full line cycle, -based index) Display Start (first COM with active scan pulse, -based index) Display End (last COM with active scan pulse, -based index) Please maintain the following relationship: CEN = (the actual number of pixel rows on the LCD) - 1 CEN DEN DST+ 9 APC N/A Advanced Program Control For UltraChip only Please do not use Status Registers OM 2 Operating Modes (Read only) b: Reset 1b: (Not used) 1b: Sleep 11b: Normal ID 2 PIN Access the connected status of ID pins Revision A_6 9

14 ULTRACHIP High-Voltage Mixed-Signal IC 1999~27 COMMAND TABLE The following is a list of host commands supported by UC161s C/D: : Control, 1: Data W/R: : Write Cycle, 1: Read Cycle Useful Data bits Don t Care Command C/D W/R D7 D6 D5 D4 D3 D2 D1 D Action Default 1 Write Data Byte 1 Write 1 byte N/A 2 Read Data Byte 1 1 Read 1 byte N/A 3 Get Status 1 ID MX MY WA DE Product Code Ver Get Status -- 4 Set Column Address LSB Set CA [3:] Set Column Address MSB 1 Set CA [7:4] 5 Set Temp Compensation 1 1 Set TC[1:] b 6 Set Power Control 1 1 Set PC[2:] 11b 7 Set Adv Program Control 1 1 R Set APC[R][7:], (double byte command) R =, or 1 N/A 8 Set Scroll Line 1 Set SL[5:] 9 Set Page Address Set PA[3:] 1 Set V BIAS Potentiometer 1 1 (double-byte command) Set PM[7:] CH 11 Set Partial Display Control 1 1 Set LC[4] b 12 Set RAM Address Control 1 1 Set AC[2:] 1b 13 Set Frame Rate 1 1 Set LC[3] b 14 Set All-Pixel-ON Set DC[1] b 15 Set Inverse Display Set DC[] b 16 Set Display Enable Set DC[2] b 17 Set LCD Mapping Control 1 1 Set LC[2:1] b 18 System Reset System Reset N/A 19 NOP No operation N/A Set Test Control TT For testing only 2 (double-byte command) Do not use N/A 21 Set LCD Bias Ratio Set BR[1:] 11b: 9 22 Set COM End Set CEN[6:] Set Partial Display Start Set DST[6:] 24 Set Partial Display End Set DEN[6:] 63 Serial Read Command (Enabled only in S8/S9 mode ) Read Data Byte Get Status 1 MX MY WA DE Prod_ code Ver * Other than commands listed above, all other bit patterns result in NOP (No Operation) Read until chip disabled Get status till chip disabled N/A N/A 1 ES Specifications

15 UC161S 65x132 STN Controller-Drivers COMMAND DESCRIPTION 1 Write Data Byte to Memory Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D Write data 1 8-bit data write to SRAM 2 Read Data Byte from Memory Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D Read data bit data read from SRAM Write/Read Data Byte (Command 1,2) access Display Data RAM based on Page Address (PA) register and Column Address (CA) register To minimize bus interface cycles, PA and CA will increase or decrease automatically after each bus cycle, depending on the setting of Access Control (AC) registers PA and CA can also be programmed directly by issuing Set Page Address and Set Column Address commands If Wrap-Around (WA) is OFF (AC[] = ), CA will stop increasing after reaching the end of the page, and system programmers need to set the values of PA and CA explicitly If WA is ON (AC[]=1), when CA reaches the end of the page, CA will be reset to and PA will increase or decrease by 1, depending on the setting of Page Increment Direction (PID, AC[2]) When PA reaches the boundary of RAM, PA will be wrapped around to the other end of RAM and continue (See command 3, Window Programming, for more details) 3 Get Status Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D 1 ID MX MY WA DE Get Status 1 Product Code Ver Status1 definitions: ID: Provide access to ID pins connection status MX: Status of register LC[1], mirror X MY: Status of register LC[2], mirror Y WA: Status of register AC[] Automatic column/row wrap around DE: Display Enable flag DE=1 when display is enabled Status2 definitions: Product Code: production identification Default: 11b Ver: IC Version, ~ 1 4 Set Column Address Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D Set Column Address LSB CA[3:] CA3 CA2 CA1 CA Set Column Address MSB CA[7:4] 1 CA7 CA6 CA5 CA4 Set the SRAM column address before Write/Read memory from host interface CA value range: ~131 Revision A_6 11

16 ULTRACHIP High-Voltage Mixed-Signal IC 1999~27 5 Set Temperature Compensation Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D Set Temperature Comp TC[1:] 1 1 TC1 TC Set VBIAS temperature compensation coefficient (%-per-degree-c) Temperature compensation curve definition: b= -5%/ o C 1b= -1%/ o C 1b= -15%/ o C 11b= -%/ o C 6 Set Power Control Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D Set Power Control PC[2:] 1 1 PC2 PC1 PC Set PC[] according to the capacitance loading of LCD panel Panel loading definition: b : 15nF 1b : 15~24nF Set PC[2:1] to program the build-in charge pump stages b = External V LCD 11b = Internal V LCD ( x7 ) 7 Set Advanced Program Control Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D Set Adv Program Control 1 1 R APC[R][7:](Double byte command) APC register parameter For UltraChip only Please Do NOT use 8 Set Scroll Line Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D Set Scroll Line SL[5:] 1 SL5 SL4 SL3 SL2 SL1 SL Set the scroll line number Scroll line setting will scroll the displayed image up by SL rows Icon output CIC will not be affected by Set Scroll Line command Image row : Image row N-1 row : : Image row N : : Image row N : : Image row 63 Image row : Image row 63 row 63 Image row N-1 SL= SL=N row : : row 63 9 Set Page Address Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D Set Page Address PA3 PA2 PA1 PA Set the SRAM page address before write/read memory from host interface Each page of SRAM corresponds to 8 COM lines on LCD panel, except for the last page The last page corresponds to the icon output CIC Possible value = ~8 12 ES Specifications

17 UC161S 65x132 STN Controller-Drivers 1 Set V BIAS Potentiometer Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D Set V BIAS Potentiometer PM [7:] 1 1 (Double byte command) PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM Program V BIAS Potentiometer (PM[7:]) See section LCD Voltage Setting for more detail Effective range: ~ Set Partial Display Control Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D Set Partial Display Enable LC [4] 1 1 LC4 This command is used to enable partial display function LC[4] : b: Disable Partial Display, Mux-Rate = CEN+1 (DST, DEN not used) 1b: Enable Partial Display, Mux-Rate = DEN-DST+1 12 Set RAM Address Control Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D Set AC [2:] 1 1 AC2 AC1 AC Program registers AC[2:] for RAM address control It controls the auto-increment behavior of CA and PA AC[] WA, Automatic column/page wrap around : CA or PA (depends on AC[1]= or 1) will stop increasing after reaching boundary 1: CA or PA (depends on AC[1]= or 1) will restart, and CA or PA will increase by one AC[1] Auto-Increment order : column (CA) increasing (+1) first until CA reach CA boundary, then PA will increase by (+/-1) 1 : page (PA) increasing (+/-1) first until PA reach PA boundary, then CA will increase by (+1) AC[2] PID, page address (PA) auto increment direction ( /1 = +/- 1 ) When WA=1 and CA reaches CA boundary, PID controls whether page address will be adjusted by +1 or Set Frame Rate Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D Set Frame Rate LC [3] 1 1 LC3 Program LC [3] for frame rate setting b: 8 fps 1b: 1 fps (fps: frame-per-second) Revision A_6 13

18 ULTRACHIP High-Voltage Mixed-Signal IC 1999~27 14 Set All Pixel ON Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D Set All Pixel ON DC [1] DC1 Set DC[1] to force all SEG drivers to output ON signals This function has no effect on the existing data stored in display RAM 15 Set Inverse Display Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D Set Inverse Display DC [] DC Set DC[] to force all SEG drivers to output the inverse of the data (bit-wise) stored in display RAM This function has no effect on the existing data stored in display RAM 16 Set Display Enable Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D Set Display Enable DC[2] DC2 This command is for programming register DC[2] When DC[2] is set to 1, UC161s will first exit from sleep mode, restore the power and then turn on COM drivers and SEG drivers 17 Set LCD Mapping Control Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D Set LCD Control LC[2:1] 1 1 MY MX Set LC[2:1] for COM (row) mirror (MY), SEG (column) mirror (MX) MY is implemented by reversing the mapping order between RAM and COM (row) electrodes The data stored in RAM is not affected by MY command MY will have immediate effect on the display image MX is implemented by selecting the CA or 5-CA as write/read (from host interface) display RAM column address so this function will only take effect after rewriting the RAM data 18 System Reset Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D System Reset This command will activate the system reset Control register values will be reset to their default values Data store in RAM will not be affected 19 NOP Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D No Operation This command is used for no operation 2 Set Test Control Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D Set TT TT (Double byte command) Testing parameter This command is used for UltraChip production testing Please do NOT use 14 ES Specifications

19 UC161S 65x132 STN Controller-Drivers 21 Set LCD Bias Ratio Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D Set Bias Ratio BR [1:] BR1 BR Bias ratio definition: b= 6 1b= 7 1b= 8 11b= 9 22 Set COM End Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D Set CEN [6:] (Double-byte command) - CEN register parameter This command programs the ending COM electrode CEN defines the number of used COM electrodes, and it should correspond to the number of pixel-rows in the LCD When the LCD has less than 64 pixel rows, the LCM designer should set CEN to N-1 (where N is the number of pixel rows) and use COM1 through COM-N as COM driver electrodes Revision A_6 15

20 ULTRACHIP High-Voltage Mixed-Signal IC 1999~27 23 Set Partial Display Start Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D Set DST [6:] (Double-byte command) - DST register parameter This command programs the starting COM electrode, which has been assigned a full scanning period and will output an active COM scanning pulse 24 Set Partial Display End Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D Set DEN [6:] (Double-byte command) - DEN register parameter This command programs the ending COM electrode, which has been assigned a full scanning period and will output an active COM scanning pulse CEN, DST, and DEN are -based index of COM electrodes They control only the COM electrode activity, and do not affect the mapping of display RAM to each COM electrodes The image displayed by each pixel row is therefore not affected by the setting of these three registers When LC[4]=1b, the Mux-Rate is narrowed down to DST-DEN+1 When MUX rate is reduced, reduce the frame rate accordingly to reduce power Changing MUX rate also require BR and V LCD to be reduced For minimum power consumption, set LC[4]=1b, set (DST, DEN, CEN) to minimize Mux rate, use slowest frame rate which satisfies the flicker requirement, set PC[]=b, and use lowest BR, lowest V LCD which satisfies the contrast requirement When Mux-Rate is under 16, it is recommended to set BR=6 for optimum power saving In either case, DST/DEN defines a small subsection of the display which will remain active while shutting down all the rest of the display to conserve energy DST DEN CEN 95 Scan Method Not scanned Pulse Enable Not scanned Not Scanned Display Result: Display segment 16 ES Specifications

21 UC161S 65x132 STN Controller-Drivers Serial Read Command (Enable only in S8/S9 mode): 25 Read Data Byte from Memory Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D Read data bit Data read from SRAM 26 Get Status Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D Get Status MX MY WA DE Prod_Code Ver Revision A_6 17

22 ULTRACHIP High-Voltage Mixed-Signal IC 1999~27 LCD VOLTAGE SETTING MULTIPLEX RATES Multiplex Rate is completely software programmable in UC161s via registers CEN, DST, DEN, and partial display control flags LC[4] Combined with low power partial display mode and a low bias ratio of 6, UC161s can support wide variety of display control options For example, when a system goes into stand-by mode, a large portion of LCD screen can be turned off to conserve power BIAS RATIO SELECTION Bias Ratio (BR) is defined as the ratio between V LCD and V BIAS, ie BR = V LCD /V BIAS, where V BIAS = V B1+ V B1 = V B+ V B The theoretical optimum Bias Ratio can be estimated by Mux + 1 BR of value 15~2% lower/higher than the optimum value calculated above will not cause significant visible change in image quality UC161s supports four BR as listed below BR can be selected by software program BR Bias Ratio Table 1: Bias Ratios TEMPERATURE COMPENSATION Four different temperature compensation coefficients can be selected via software The four coefficients are given below: TC % per o C Table 2: Temperature Compensation V LCD GENERATION V LCD may be supplied either by internal charge pump or by external power supply The source of V LCD is controlled by PC[2:1] When V LCD is generated internally, the voltage level of V LCD is determined by three control registers: BR (Bias Ratio), PM (Potentiometer), and TC (Temperature Compensation), with the following relationship: V LCD = ( CV + CPM PM ) (1 + ( T 25) CT %) where C V and C PM are two constants, whose value depends on the setting of BR register, as illustrated in the table on the next page, PM is the numerical value of PM register, T is the ambient temperature in O C, and C T is the temperature compensation coefficient as selected by TC register V LCD FINE TUNING Black-and-white STN LCD is sensitive to even a 1% mismatch between IC driving voltage and the V OP of LCD However, it is difficult for LCD makers to guarantee such high precision matching of parts from different venders It is therefore necessary to adjust V LCD to match the actual V OP of the LCD For the best result, software based approach for V LCD adjustment is the recommended method for V LCD fine-tuning System designers should always consider the contrast fine tuning requirement before finalizing on the LEM design LOAD DRIVING STRENGTH The power supply circuit of UC161s is designed to handle LCD panels with loading up to ~24nF using 2-Ω/Sq ITO glass with V DD2/3 24V For larger LCD panels, use lower resistance ITO glass packaging 18 ES Specifications

23 UC161S 65x132 STN Controller-Drivers V LCD QUICK REFERENCE VLCD PM V LCD Programming Curve BR CV (V) CPM (mv) PM VLCD Range (V) Note: 1 For good product reliability, keep V LCD under 115V over all temperature 2 The integer values of BR above are for reference only and may have slight shift Revision A_6 19

24 ULTRACHIP High-Voltage Mixed-Signal IC 1999~27 HI-V GENERATOR AND BIAS REFERENCE CIRCUIT VDD VDD VDD2/VDD3 VDD2 VDD3 VB+ VB- VB1+ VB1- CB CB1 UC161s VSS VSS2 VLCDOUT VLCDIN CL RL (OPTIONAL) FIGURE 1: Reference circuit using internal Hi-V generator circuit Note Sample component values: (The illustrated circuit and component values are for reference only Please optimize for specific requirements of each application) C Bx : 22 µf/5v or 3x LCD load capacitance, whichever is higher C L : 33nF(25V) is appropriate for most applications R L : 33~1M Ω to act as a draining circuit when V DD is shut down abruptly 2 ES Specifications

25 UC161S 65x132 STN Controller-Drivers LCD DISPLAY CONTROLS CLOCK & TIMING GENERATOR UC161s contains a built-in system clock All required components for the clock oscillator are built-in No external parts are required Two different frame rates are provided for system design flexibility The frame rate is controlled by register LC[3] When Mux-Rate is above 34, Frame rate: 8 fps and 1 fps When Mux-Rate is lowered to 33, and 16, frame rate will be scaled down automatically by 2 and 4 times to reduce power consumption Choose lower frame rate for lower power, and choose higher frame rate to improve LCD contrast and minimize flicker DRIVER MODES COM and SEG drivers can be in either Idle mode or Active mode, controlled by Display Enable flag (DC[2]) When SEG and COM drivers are in idle mode, they will be connected together to ensure zero DC condition on the LCD DRIVER ARRANGEMENTS The naming conventions are: COMx, where x = 1~64, refers to the row driver for the x-th row of pixels on the LCD panel The mapping of COM(x) to LCD pixel rows is fixed and it is not affected by SL, CEN, DST, DEN, MX or MY settings DISPLAY CONTROLS There are three groups of display control flags in the control register DC: Driver Enable (DE), All- Pixel-ON (APO) and Inverse (PXV) DE has the overriding effect over PXV and APO DRIVER ENABLE (DE) Driver Enable is controlled by the value of DC[2] via Set Display Enable command When DC[2] is set to OFF (logic ), both COM and SEG drivers will become idle and UC161s will put itself into Sleep Mode to conserve power When DC[2] is set to ON, the DE flag will become 1,and UC161s will first exit from Sleep Mode, restore the power (V LCD, V D etc) and then turn on COM and SEG drivers ALL PIXELS ON (APO) When set, this flag will force all SEG drivers to output ON signals, disregarding the data stored in the display buffer This flag has no effect when Display Enable is OFF and it has no effect on data stored in RAM INVERSE (PXV) When this flag set to ON, SEG drivers will output the inverse of the value it received from the display buffer RAM (bit-wise inversion) This flag has no impact on data stored in RAM PARTIAL DISPLAY UC161s provides flexible control of Mux Rate and active display area Please refer to commands Set COM End, Set Partial Display Start, and Set Partial Display End for more detail Revision A_6 21

26 ULTRACHIP High-Voltage Mixed-Signal IC 1999~27 ITO LAYOUT AND LC SELECTION Since COM scanning pulses of UC161s can be as short as 153µS, it is critical to control the RC delay of COM and SEG signal to minimize crosstalk and maintain good mass production consistency COM TRACES Excessive COM scanning pulse RC decay can cause fluctuation of contrast and increase COM direction crosstalk Please limit the worst case of COM signals RC delay (RC MAX ) as calculated below (R ROW / 27 + R COM ) x C ROW < 923µS where C ROW : LCD loading capacitance of one row of pixels It can be calculated by C LCD /Mux- Rate, where C LCD is the LCD panel capacitance R ROW : ITO resistance over one row of pixels within the active area R COM : COM routing resistance from IC to the active area + COM driver output impedance In addition, please limit the min-max spread of RC decay to be: RC MAX RC MIN < 276µS so that the COM distortions on the top of the screen to the bottom of the screen are uniform (Use worst case values for all calculations) SEG TRACES Excessive SEG signal RC decay can cause image dependent changes of medium gray shades and sharply increase the crosstalk of SEG direction For good image quality, please minimize SEG ITO trace resistance and limit the worst case of SEG signal RC delay as calculated below (R COL / 27 + R SEG ) x C COL < 63µS where C COL : LCD loading capacitance of one pixel column It can be calculated by C LCD / ( of column), where C LCD is the LCD panel capacitance R COL : ITO resistance over one column of pixels within the active area R SEG : SEG routing resistance from IC to the active area + SEG driver output impedance (Use worst case values for all calculations) SELECTING LIQUID CRYSTAL The selection of LC material is crucial to achieve the optimum image quality of finished LCM When (V 9 -V 1 )/V 1 is too large, image contrast will deteriorate, and images will look murky and dull When (V 9 -V 1 )/V 1 is too small, image contrast will become too strong, and crosstalk will increase For the best result, it is recommended the LC material has the following characteristics: (V 9 -V 1 )/V 1 = (V ON -V OFF )/V OFF x 72~8 where V 9 and V 1 are the LC characteristics, and V ON and V OFF are the ON and OFF V RMS voltage produced by LCD driver IC at the specific Mux-rate Two examples are provided below: Duty Bias V ON /V OFF -1 x8 x72 1/65 1/9 16% 96% 75% 1/65 1/8 15% 95% 74% 22 ES Specifications

27 UC161S 65x132 STN Controller-Drivers RAM W/R POL COM1 COM2 COM3 SEG1 SEG2 FIGURE 2: COM and SEG Electrode Driving Waveform Revision A_6 23

28 ULTRACHIP High-Voltage Mixed-Signal IC 1999~27 HOST INTERFACE As summarized in the table below, UC161s supports two 8-bit parallel bus protocols and two serial bus protocols Designers can choose either the 8-bit parallel bus to achieve high data transfer rate, or use serial bus to create compact LCD modules and minimize connector pins Control & Data Pins Bus Type S8(4wr) S9(3wr) I 2 C(2wr) Width 8-bit 8-bit Serial Access Read / Write Write only R / W BM[1:] {DB[7], DB[6]} Data Data CS[1:] Chip Select A[3:2] CD Control/Data WR WR1 WR R/W RD EN DB[1,2,4,5,6,7] Data - DB[:3] Data DB[]=SCK, DB[3]=SDA * Connect unused control pins and data bus pins to V DD or V SS CS Disable Interface CS Init Bus State CD 1 Init Bus State RESET Init Bus State RESET Init Color Mapping 8-bit S8 or S9 I 2 C CS disable bus interface CS can be used to disable Bus Interface Write / Read Access CD refers to CD transitions within valid CS window CD = means write command or read status CS / CD Sync / RESET can be used to initialize bus state machine (like 8-bit / S8 / S9) RESET can be pin reset / soft reset / power on reset Table 3: Host interfaces Summary 24 ES Specifications

29 UC161S 65x132 STN Controller-Drivers PARALLEL INTERFACE The timing relationship between UC161s internal control signal RD, WR and their associated bus actions are shown in the figure below The Display RAM read interface is implemented as a two-stage pipeline This architecture requires that, every time memory address is modified, either in parallel mode or serial mode, by either Set CA or Set PA command, a dummy read cycle need to be performed before the actual data can propagate through the pipeline and be read from data port D[7:] There is no pipeline in write interface of Display RAM Data is transferred directly from bus buffer to internal RAM on the rising edges of write pulses External CD WR RD D[7:] L LSB D L D L+K C MSB C LSB Dummy D C D C+1 M MSB M LSB Internal Write Read Data Latch Column Address D L D L+K Dummy D C D C+1 D C+2 L L+K L+K+1 C C+1 C+2 C+3 M Figure 3: Parallel Interface & Related Internal Signals Revision A_6 25

30 ULTRACHIP High-Voltage Mixed-Signal IC 1999~27 SERIAL INTERFACE UC161s supports three serial modes, one 4-wire SPI mode (S8), one 3-wire SPI mode (S9) and one 2-wire SPI mode (I 2 C) Bus interface mode is determined by the wiring of the BM[1:] and DB[7:6] See table in last page for more detail S8 (4-WIRE) INTERFACE Only write operations are supported in 4-wire serial mode Pin CS[1:] are used for chip select and bus cycle reset Pin CD is used to determine the content of the data been transferred During each write cycle, 8 bits of data, MSB first, are latched on eight rising SCK edges into an 8-bit data holder If CD=, the data byte will be decoded as command If CD=1, this 8-bit will be treated as data and transferred to proper address in the Display Data RAM on the rising edge of the last SCK pulse Pin CD is examined when SCK is pulled low for the LSB (D) of each token CS SDI D7 D6 D5 D4 D3 D2 D1 D D7 D6 D5 SCK CD Figure 4a: 4-wire Serial Interface (S8) S9 (3-WIER) INTERFACE Only write operations are supported in 3-wire serial mode Pin CS[1:] are used for chip select and bus cycle reset On each write cycle, the first bit is CD, which determines the content of the following 8 bits of data, MSB first These 8 command or data bits are latched on rising SCK edges into an 8-bit data holder If CD=, the data byte will be decoded as command If CD=1, this 8-bit will be treated as data and transferred to proper address in the Display Data RAM at the rising edge of the last SCK pulse By sending CD information explicitly in the bit stream, control pin CD is not used, and should be connected to either V DD or V SS The toggle of CS (or CS1) for each byte of data/command is recommended but optional CS SDI CD D7 D6 D5 D4 D3 D2 D1 D CD D7 D6 SCK Figure 4b: 3-wire Serial Interface (S9) 26 ES Specifications

31 UC161S 65x132 STN Controller-Drivers I 2 C (2-WIRE) INTERFACE When BM[1:] is set to LH and D[7:6] is set to HH, UC161s is configured as an I 2 C bus signaling protocol compliant slave device Please refer to I 2 C standard for details of the bus signaling protocol, and AC Characteristic section for timing parameters of UltraChip implementation In this mode, pins CS[1:] become A[3:2] and is used to configure UC161s device address Proper wiring to V DD or V SS is required for the IC to operate properly for I 2 C mode Write Mode Each UC161s I 2 C interface sequence starts with a S (Start) from the bus master, followed by a sequence header, containing a device address, the mode of transfer (CD, :Control, 1:Data), and the direction of the transfer (RW, :Write, 1:Read) Since both WR and CD are expressed explicitly in the header byte, the control pins WR[1:] and CD are not used in I 2 C mode and should be connected to V SS MPU MPU MPU MPU MPU S A A C 3 2 D A D 7 D A D 7 D A A P Read Mode MPU MPU MPU MPU MPU S A A C 3 2 D 1 A D 7 D A D 7 D A N P The direction (read or write) and content type (command or data) of the data bytes following each header byte are fixed for the sequence To change the direction (RW) or the content type (CD), start a new sequence with a START (S) flag, followed by a new header After receiving the header, the UC161s will send out a A (Acknowledge signal) Then, depends on the setting of the header, the transmitting device (either the bus master or UC161s) will start placing data bits on SDA, MSB to LSB, and the sequence will repeat until a STOP signal (P, in WRITE mode), or an N (Not Acknowledged, in READ mode) is sent by the bus master Revision A_6 27

32 ULTRACHIP High-Voltage Mixed-Signal IC 1999~27 When using I 2 C serial mode, if command System Reset is to be written, the writing sequence must be finished (STOP) before succeeding data or commands start The flow chart on the right shows a writing sequence with a System Reset command Note that, for data read (CD=1), the first byte of data transmitted will be dummy START Header Command = System Reset STOP START Header Command / Data Command / Data Command / Data STOP 28 ES Specifications

33 UC161S 65x132 STN Controller-Drivers HOST INTERFACE REFERENCE CIRCUIT VDD VCC VDD D7~D DB7~DB CD WR RD CD WR(WR) WR1(RD) MPU ADDRESS IORQ DECODER CS CS1 UC161s VDD RST VDD BM1 BM GND VSS FIGURE 5: 88/8bit parallel mode reference circuit VDD VCC VDD D7~D D7~D CD R/W E CD WR(R/W) WR1(E) MPU ADDRESS IORQ DECODER CS CS1 UC161s VDD RST VDD BM1 BM GND VSS FIGURE 6: 68/8bit parallel mode reference circuit Revision A_6 29

34 ULTRACHIP High-Voltage Mixed-Signal IC 1999~27 VDD VCC DB7 DB6 VDD SCK SDA CD SCK(DB) SDA(DB3) CD WR WR1 MPU ADDRESS IORQ DECODER CS CS1 UC161s VDD RST BM1 BM GND VSS FIGURE 7: Serial-8 serial mode reference circuit VDD VCC DB7 DB6 VDD SCK SDA SCK(DB) SDA(DB3) CD WR WR1 MPU ADDRESS IORQ DECODER CS CS1 UC161s VDD RST VDD BM1 BM GND VSS FIGURE 8: Serial-9 serial mode reference circuit 3 ES Specifications

35 UC161S 65x132 STN Controller-Drivers VDD VCC R2 R1 DB7 DB6 VDD SCK SDA SCK(DB) SDA(DB3) CD WR WR1 CS(A2) CS1(A3) MPU UC161s VDD RST VDD BM1 BM GND VSS Note FIGURE 9: I 2 C serial mode reference circuit The ID pins are for production control The connection will affect the content of D[7] of the 1st byte of the Get Status command Connect to V DD for H or V SS for L RST pin is optional When the RST pin is not used, connect it to V DD When using I 2 C serial mode, CS1/ are user configurable and affect A[3:2] of device address R1, R2: 2k ~ 1k Ω, use lower resistor for bus speed up to 36MHz, use higher resistor for lower power Revision A_6 31

36 ULTRACHIP High-Voltage Mixed-Signal IC 1999~27 DISPLAY DATA RAM (DDRAM) DATA ORGANIZATION The input display data is stored to a dual port static DDRAM (DDRAM, for Display Data RAM) organized as 65x132 After setting CA and RA, the subsequent data write cycle will store the data for the specified pixel to the proper memory location Please refer to the map in the following page between the relation of COM, SEG, SRAM, and various memory control registers DISPLAY DATA RAM ACCESS The Display RAM is a special purpose dual port RAM which allows asynchronous access to both its column and row data Thus, RAM can be independently accessed both for Host Interface and for display operations DISPLAY DATA RAM ADDRESSING A Host Interface (HI) memory access operation starts with specifying Row Address (RA) and Column Address (CA) by issuing Set Row Address and Set Column Address commands If wrap-around (WA, AC[]) is OFF (), CA will stop increasing after reaching the end of row (131), and system programmers need to set the values of PA and CA explicitly If WA is ON (1), when CA reaches end of page, CA will be reset to and PA will increase or decrease, depending on the setting of row Increment Direction (PID, AC[2]) When PA reaches the boundary of RAM (ie PA = or 7), PA will be wrapped around to the other end of RAM and continue MX IMPLEMENTATION Column Mirroring (MX) is implemented by selecting either (CA) or (131 CA) as the RAM column address Changing MX affects the data written to the RAM Since MX has no effect of the data already stored in RAM, changing MX does not have immediate effect on the displayed pattern To refresh the display, refresh the data stored in RAM after setting MX ROW MAPPING COM electrode scanning orders are not affected by Start Line (SL), Fixed Line (FLT & FLB) or Mirror Y (MY, LC[3]) Visually, register SL having a non-zero value is equivalent to scrolling the LCD display up or down (depends on MY) by SL rows RAM ADDRESS GENERATION The mapping of the data stored in the display SRAM and the scanning electrodes can be obtained by combining the fixed Rm scanning sequence and the following RAM address generation formula During the display operation, the RAM line address generation can be mathematically represented as following: For the 1st line period of each field Line = SL Otherwise Line = Mod(Line+1, 64) Where Mod is the modular operator, and Line is the bit slice line address of RAM to be outputted to column drivers Line corresponds to the first bit-slice of data in RAM The above Line generation formula produce the loop around effect as it effectively resets Line to when Line+1 reaches 64 MY IMPLEMENTATION Row Mirroring (MY) is implemented by reversing the mapping order between row electrodes and RAM, ie the mathematical address generation formula becomes: For the 1 st line period of each field Line = Mod(SL + MR -1, 64) Otherwise Line = Mod(Line-1, 64) Visually, the effect of MY is equivalent to flipping the display upside down The data stored in display RAM is not affected by MY 32 ES Specifications

37 UC161S 65x132 STN Controller-Drivers Line MY= MY=1 PA[3:] AddeCss SL= SL=16 SL= SL= SL=25 SL=25 D H C1 C49 C64 C48 C25 C9 D1 1H C2 C5 C63 C47 C24 C8 D2 2H C3 C51 C62 C46 C23 C7 D3 3H C4 C52 C61 C45 C22 C6 Page D4 4H C5 C53 C6 C44 C21 C5 D5 5H C6 C54 C59 C43 C2 C4 D6 6H C7 C55 C58 C42 C19 C3 D7 7H C8 C56 C57 C41 C18 C2 D 8H C9 C57 C56 C4 C17 C1 D1 9H C1 C58 C55 C39 C D2 AH C11 C59 C54 C38 C D3 BH C12 C6 C53 C37 C Page 1 D4 CH C13 C61 C52 C36 C D5 DH C14 C62 C51 C35 C D6 EH C15 C63 C5 C34 C D7 FH C16 C64 C49 C33 C1 --- D 1H C17 C1 C48 C32 C9 --- D1 11H C18 C2 C47 C31 C8 --- D2 12H C19 C3 C46 C3 C D3 13H C2 C4 C45 C29 C6 --- Page 2 D4 14H C21 C5 C44 C28 C5 --- D5 15H C22 C6 C43 C27 C4 --- D6 16H C23 C7 C42 C26 C3 --- D7 17H C24 C8 C41 C25 C2 --- D 18H C25 C9 C4 C24 C1 --- D1 19H C26 C1 C39 C23 C64 C48* D2 1AH C27 C11 C38 C22 C63 C47 11 D3 1BH C28 C12 C37 C21 C62 C46 Page 3 D4 1CH C29 C13 C36 C2 C61 C45 D5 1DH C3 C14 C35 C19 C6 C44 D6 1EH C31 C15 C34 C18 C59 C43 D7 1FH C32 C16 C33 C17 C58 C42 D 2H C33 C17 C32 C16 C57 C41 D1 21H C34 C18 C31 C15 C56 C4 D2 22H C35 C19 C3 C14 C55 C39 1 D3 23H C36 C2 C29 C13 C54 C38 Page 4 D4 24H C37 C21 C28 C12 C53 C37 D5 25H C38 C22 C27 C11 C52 C36 D6 26H C39 C23 C26 C1 C51 C35 D7 27H C4 C24 C25 C9 C5 C34 D 28H C41 C25 C24 C8 C49 C33 D1 29H C42 C26 C23 C7 C48 C32 D2 2AH C43 C27 C22 C6 C47 C31 11 D3 2BH C44 C28 C21 C5 C46 C3 Page 5 D4 2CH C45 C29 C2 C4 C45 C29 D5 2DH C46 C3 C19 C3 C44 C28 D6 2EH C47 C31 C18 C2 C43 C27 D7 2FH C48 C32 C17 C1 C42 C26 D 3H C49 C33 C C41 C25 D1 31H C5 C34 C C4 C24 D2 32H C51 C35 C C39 C23 11 D3 33H C52 C36 C C38 C22 Page 6 D4 34H C53 C37 C C37 C21 D5 35H C54 C38 C C36 C2 D6 36H C55 C39 C1 --- C35 C19 D7 37H C56 C4 C9 --- C34 C18 D 38H C57 C41 C8 --- C33 C17 D1 39H C58 C42 C7 --- C32 C16 D2 3AH C59 C43 C6 --- C31 C D3 3BH C6 C44 C5 --- C3 C14 Page 7 D4 3CH C61 C45 C4 --- C29 C13 D5 3DH C62 C46 C3 --- C28 C12 D6 3EH C63 C47 C2 --- C27 C11 D7 3FH C64 C48 C1 --- C26 C1 1 D 4H Page 8 CIC CIC CIC CIC CIC CIC MUX MX 1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG132 SEG131 SEG13 SEG129 SEG128 SEG127 SEG126 SEG125 SEG128 SEG129 SEG13 SEG131 SEG132 SEG5 SEG4 SEG3 SEG2 SEG1 Example for memory mapping: let MX =, MY =, SL =, according to the data shown in the above table: Page SEG 1: 111b Page SEG 2: 1111b Revision A_6 33

38 ULTRACHIP High-Voltage Mixed-Signal IC 1999~27 RESET & POWER MANAGEMENT TYPES OF RESET UC161s has two different types of Reset: Power-ON-Reset and System-Reset Power-ON-Reset is performed right after V DD is connected to power Power-On-Reset will first wait for about ~5mS, depending on the time required for V DD to stabilize, and then trigger the System Reset System Reset can also be activated by software command or by connecting RST pin to ground In the following discussions, Reset means System Reset RESET STATUS When UC161s enters RESET sequence: Operation mode will be Reset All control registers are reset to default values Refer to Control Registers for details of their default values OPERATION MODES UC161s has three operating modes (OM): Reset, Sleep, Normal For each mode, the related statuses are as below: Mode Reset Sleep Normal OM 1 11 Host Interface Active Active Active Clock OFF OFF ON LCD Drivers OFF OFF ON Charge Pump OFF OFF ON Draining Circuit ON ON OFF Table 4: Operating Modes CHANGING OPERATION MODE In addition to Power-ON-Reset, two commands will initiate OM transitions: Set Display Enable, and System Reset When DC[2] is modified by Set Display Enable, OM will be updated automatically There is no other action required to enter power saving mode For maximum energy utilization, Sleep mode is designed to retain charges stored in external capacitors C B, C B1, and C L To drain these capacitors, use Reset command to activate the on-chip draining circuit Action Mode OM Reset command RST_ pin pulled L Reset Power ON reset Set Driver Enable to Sleep 1 Set Driver Enable to 1 Normal 11 Table 5: OM changes Even though UC161s consumes very little energy in Sleep mode (typically under 2µA); however, since all capacitors are still charged, the leakage through COM drivers may damage the LCD over the long term It is therefore recommended to use Sleep mode only for brief Display OFF operations, such as full-frame screen updates, and to use RESET for extended screen OFF operations EXITING SLEEP MODE UC161s contains internal logic to check whether V LCD and V BIAS are ready before releasing COM and SEG drivers from their idle states When exiting Sleep or Reset mode, COM and SEG drivers will not be activated until UC161s internal voltage sources are restored to their proper values 34 ES Specifications

39 UC161S 65x132 STN Controller-Drivers POWER-UP SEQUENCE UC161s power-up sequence is simplified by built-in Power Ready flags and by the automatic invocation of System-Reset command after Power-ON-Reset System programmer is required to wait for only 5 ~ 1 ms before starting to issue commands to UC161s No additional commands or waits are required between enabling of the charge pump, turning on the display drivers, writing to RAM or any other commands There s no delay needed while turning on V DD and V DD2/3, and either one can be turned on first Turn ON the power POWER-DOWN SEQUENCE To prevent the charge stored in capacitors C BX+ and C L from damaging the LCD when V DD is switched off, use Reset mode to enable the builtin charge draining circuit to discharge these external capacitors The draining resistance is 1K for both V LCD and V B It is recommended to wait 3 x RC for V LCD and 15 x RC for V B For example, if C LCD is 1nF, then the draining time required for V LCD is 3mS When internal V LCD is not used, UC161s will NOT drain V LCD during RESET System designers need to make sure external V LCD source is properly drained off before turning off V DD Wait 5~1 ms Reset command Set LCD Bias Ratio (BR) Wait ~1 ms Set Potentiometer (PM) Reset Display Enable Turn OFF the power FIGURE 1: Reference Power-Up Sequence FIGURE 11: Reference Power-Down Sequence Either V DD or V DD2/3 may be turned on first T Wait > 1mS V DD < 1V V DD2/3 25V V DD 18V V DD2/3 V DD T f < 1 ms 1µS < T 1 < 1 ms Figure 12: Power Off-On Sequence Revision A_6 35