RW1072-0A-001 INTRODUCTION FEATURES. Driver Output Circuit. Microprocessor Interface. Internal Memory. On-chip Low Power Analog Circuit FUNCTION

Transcription

1 INTRODUCTION RW1072-0A-001 RW1072 is a Character Type LCD driver& controller LSI which is fabricated by low power CMOS process technology. It can display 1-lines/2-lines/3-lines with 5*8 or 6*8 dots font and 2 independent COMS signals can support 288 icons max (for 6*8 dots font) or 280 icons (for 5*8 dots font). FEATURES Driver Output Circuit Segment outputs / 26 Common outputs (1/26 Duty, 6*8 dots font) Segment outputs / 18 Common outputs (1/18 Duty, 6*8 dots font) Segment outputs / 10 Common outputs (1/10 Duty, 6*8 dots font) Segment outputs / 26 Common outputs (1/26 Duty, 5*8 dots font) Segment outputs / 18 Common outputs (1/18 Duty, 5*8 dots font) Segment outputs / 10 Common outputs (1/10 Duty, 5*8 dots font) Microprocessor Interface - 8-bit and 4-bit 6800 MPU Parallel bi-directional interface - 4-line serial peripheral interface (Only support write operation) - 3-line serial peripheral interface (Only support write operation) - IIC serial interface (only support write operation) Internal Memory - Character Generator ROM (CGROM): 240*6*8bits (240 characters for GM=0;176 characters for GM=1) - Character Generator RAM (CGRAM):80*6*8bits (16 characters for GM=0; 80 characters for GM=1) - ICONRAM (SEGRAM): 288bits (for 6*8 dots font) /280 bits (for 5*8 dots font) - Display Data RAM (DDRAM): 80*8bits (80 characters Max) On-chip Low Power Analog Circuit - Logic Power supply voltage range: 1.7 V to 3.6 V (-) - Boost Power supply voltage range: 2.4 V to 3.6 V (2-) - Boost maximum voltage limited: 18.0V (-) - Liquid crystal drive power supply range: 4.25 V~ 14.5 V (-) - Generation of intermediate LCD bias voltages: 1/4 ~ 1/7 bias - Wide range of operating temperatures: -40 to +85 degree FUNCTION - Internal voltage converter (X2, X3, X4, X5, X6) - Voltage regulator and follower (,V1~V4) - RC built-in Internal oscillator - Automatic power on reset - All characters Reverse Display -Dual Common output for each Common signal -Display shift per line and Cursor shift -Common and Segment bi-direction -Bias and Duty set by software -Electronic contrast control function -Adjustment frame frequency and Double frame frequency can available to 200Hz 1

2 Programmable duty cycles Dots Font Width Display Line Numbers Duty Ratio Display able Characters Possible ICONS 1 1/10 1-lines of 28 characters 2*140 5*8 2 1/18 2-lines of 28 characters 2* /26 3-lines of 26 characters 2* /10 1-lines of 24 characters 2*144 6*8 2 1/18 2-lines of 24 characters 2* /26 3-lines of 24 characters 2*144 2

3 ARRANGEMENT(COG) Chip Size: 6057 um 937 um Gold Bump Pitch: No. Pitch No. Pitch 1~63 40 um 118~ um 63~64 49 um 126~ um 64~ um 30 um 145~ ~ um (com/seg) Gold Bump Size: No. 1 ~ 144: 20 (x) um 78 (y) um No. 145 ~ 340: 15(x) um 124(y) um Gold Bump Height: 15 um (Typ.) Chip Thickness: 500 um 3

4 BLOCK DIAGRAM 4

5 COORDINATE ( 1/26 Duty, SHL=0,3-1) No. X Y No. X Y No. X Y 1 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY V DUMMY V DUMMY V CLL DUMMY V DUMMY V CS1B DUMMY V CS DUMMY V DUMMY V RSTP DUMMY A DUMMY DUMMY RW DUMMY E DUMMY DUMMY D DUMMY D DUMMY D P VRAB D P D N D N D P D P P CLS P N C N VRS P PSB P N IRS N P P T[8] T[7] T[6]

6 COORDINATE ( 1/26 Duty, SHL=0,3-2) No. X Y No. X Y No. X Y 121 T[5] COM[7] SEG[30] T[4] COM[6] SEG[31] T[3] COM[5] SEG[32] T[2] COM[4] SEG[33] T[1] COM[3] SEG[34] T[0] COM[2] SEG[35] DUMMY COM[1] SEG[36] DUMMY COM[0] SEG[37] DUMMY COMS SEG[38] DUMMY COMS SEG[39] DUMMY SEG[0] SEG[40] DUMMY SEG[1] SEG[41] DUMMY SEG[2] SEG[42] DUMMY SEG[3] SEG[43] DUMMY SEG[4] SEG[44] DUMMY SEG[5] SEG[45] DUMMY SEG[6] SEG[46] DUMMY SEG[7] SEG[47] DUMMY SEG[8] SEG[48] DUMMY SEG[9] SEG[49] DUMMY SEG[10] SEG[50] DUMMY SEG[11] SEG[51] DUMMY SEG[12] SEG[52] DUMMY SEG[13] SEG[53] COM[23] SEG[14] SEG[54] COM[22] SEG[15] SEG[55] COM[21] SEG[16] SEG[56] COM[20] SEG[17] SEG[57] COM[19] SEG[18] SEG[58] COM[18] SEG[19] SEG[59] COM[17] SEG[20] SEG[60] COM[16] SEG[21] SEG[61] COM[15] SEG[22] SEG[62] COM[14] SEG[23] SEG[63] COM[13] SEG[24] SEG[64] COM[12] SEG[25] SEG[65] COM[11] SEG[26] SEG[66] COM[10] SEG[27] SEG[67] COM[9] SEG[28] SEG[68] COM[8] SEG[29] SEG[69]

7 COORDINATE ( 1/26 Duty, SHL=0,3-3) No. X Y No. X Y No. X Y 241 SEG[70] SEG[110] COM[6] SEG[71] SEG[111] COM[7] SEG[72] SEG[112] COM[8] SEG[73] SEG[113] COM[9] SEG[74] SEG[114] COM[10] SEG[75] SEG[115] COM[11] SEG[76] SEG[116] COM[12] SEG[77] SEG[117] COM[13] SEG[78] SEG[118] COM[14] SEG[79] SEG[119] COM[15] SEG[80] SEG[120] COM[16] SEG[81] SEG[121] COM[17] SEG[82] SEG[122] COM[18] SEG[83] SEG[123] COM[19] SEG[84] SEG[124] COM[20] SEG[85] SEG[125] COM[21] SEG[86] SEG[126] COM[22] SEG[87] SEG[127] COM[23] SEG[88] SEG[128] COMS SEG[89] SEG[129] COMS SEG[90] SEG[130] SEG[91] SEG[131] SEG[92] SEG[132] SEG[93] SEG[133] SEG[94] SEG[134] SEG[95] SEG[135] SEG[96] SEG[136] SEG[97] SEG[137] SEG[98] SEG[138] SEG[99] SEG[139] SEG[100] SEG[140] SEG[101] SEG[141] SEG[102] SEG[142] SEG[103] SEG[143] SEG[104] COM[0] SEG[105] COM[1] SEG[106] COM[2] SEG[107] COM[3] SEG[108] COM[4] SEG[109] COM[5]

8 COORDINATE ( 1/26 Duty, SHL=1,3-1) No. X Y No. X Y No. X Y 1 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY V DUMMY V DUMMY V CLL DUMMY V DUMMY V CS1B DUMMY V CS DUMMY V DUMMY V RSTP DUMMY A DUMMY DUMMY RW DUMMY E DUMMY DUMMY D DUMMY D DUMMY D P VRAB D P D N D N D P D P P CLS P N C N VRS P PSB P N IRS N P P T[8] T[7] T[6]

9 COORDINATE ( 1/26 Duty, SHL=1,3-2) No. X Y No. X Y No. X Y 121 T[5] COM[16] SEG[30] T[4] COM[17] SEG[31] T[3] COM[18] SEG[32] T[2] COM[19] SEG[33] T[1] COM[20] SEG[34] T[0] COM[21] SEG[35] DUMMY COM[22] SEG[36] DUMMY COM[23] SEG[37] DUMMY COMS SEG[38] DUMMY COMS SEG[39] DUMMY SEG[0] SEG[40] DUMMY SEG[1] SEG[41] DUMMY SEG[2] SEG[42] DUMMY SEG[3] SEG[43] DUMMY SEG[4] SEG[44] DUMMY SEG[5] SEG[45] DUMMY SEG[6] SEG[46] DUMMY SEG[7] SEG[47] DUMMY SEG[8] SEG[48] DUMMY SEG[9] SEG[49] DUMMY SEG[10] SEG[50] DUMMY SEG[11] SEG[51] DUMMY SEG[12] SEG[52] DUMMY SEG[13] SEG[53] COM[0] SEG[14] SEG[54] COM[1] SEG[15] SEG[55] COM[2] SEG[16] SEG[56] COM[3] SEG[17] SEG[57] COM[4] SEG[18] SEG[58] COM[5] SEG[19] SEG[59] COM[6] SEG[20] SEG[60] COM[7] SEG[21] SEG[61] COM[8] SEG[22] SEG[62] COM[9] SEG[23] SEG[63] COM[10] SEG[24] SEG[64] COM[11] SEG[25] SEG[65] COM[12] SEG[26] SEG[66] COM[13] SEG[27] SEG[67] COM[14] SEG[28] SEG[68] COM[15] SEG[29] SEG[69]

10 COORDINATE ( 1/26 Duty, SHL=1,3-3) No. X Y No. X Y No. X Y 241 SEG[70] SEG[110] COM[17] SEG[71] SEG[111] COM[16] SEG[72] SEG[112] COM[15] SEG[73] SEG[113] COM[14] SEG[74] SEG[114] COM[13] SEG[75] SEG[115] COM[12] SEG[76] SEG[116] COM[11] SEG[77] SEG[117] COM[10] SEG[78] SEG[118] COM[9] SEG[79] SEG[119] COM[8] SEG[80] SEG[120] COM[7] SEG[81] SEG[121] COM[6] SEG[82] SEG[122] COM[5] SEG[83] SEG[123] COM[4] SEG[84] SEG[124] COM[3] SEG[85] SEG[125] COM[2] SEG[86] SEG[126] COM[1] SEG[87] SEG[127] COM[0] SEG[88] SEG[128] COMS SEG[89] SEG[129] COMS SEG[90] SEG[130] SEG[91] SEG[131] SEG[92] SEG[132] SEG[93] SEG[133] SEG[94] SEG[134] SEG[95] SEG[135] SEG[96] SEG[136] SEG[97] SEG[137] SEG[98] SEG[138] SEG[99] SEG[139] SEG[100] SEG[140] SEG[101] SEG[141] SEG[102] SEG[142] SEG[103] SEG[143] SEG[104] COM[23] SEG[105] COM[22] SEG[106] COM[21] SEG[107] COM[20] SEG[108] COM[19] SEG[109] COM[18]

11 COORDINATE ( 1/18uty, SHL=0, 3-1) No. X Y No. X Y No. X Y 1 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY V DUMMY V DUMMY V CLL DUMMY V DUMMY V CS1B DUMMY V CS DUMMY V DUMMY V RSTP DUMMY A DUMMY DUMMY RW DUMMY E DUMMY DUMMY D DUMMY D DUMMY D P VRAB D P D N D N D P D P P CLS P N C N VRS P PSB P N IRS N P P T[8] T[7] T[6]

12 COORDINATE ( 1/18uty, SHL=0, 3-2) No. X Y No. X Y No. X Y 121 T[5] COM[7] SEG[30] T[4] COM[6] SEG[31] T[3] COM[5] SEG[32] T[2] COM[4] SEG[33] T[1] COM[3] SEG[34] T[0] COM[2] SEG[35] DUMMY COM[1] SEG[36] DUMMY COM[0] SEG[37] DUMMY COMS SEG[38] DUMMY COMS SEG[39] DUMMY SEG[0] SEG[40] DUMMY SEG[1] SEG[41] DUMMY SEG[2] SEG[42] DUMMY SEG[3] SEG[43] DUMMY SEG[4] SEG[44] DUMMY SEG[5] SEG[45] DUMMY SEG[6] SEG[46] DUMMY SEG[7] SEG[47] DUMMY SEG[8] SEG[48] DUMMY SEG[9] SEG[49] DUMMY SEG[10] SEG[50] DUMMY SEG[11] SEG[51] DUMMY SEG[12] SEG[52] DUMMY SEG[13] SEG[53] NC SEG[14] SEG[54] NC SEG[15] SEG[55] NC SEG[16] SEG[56] NC SEG[17] SEG[57] NC SEG[18] SEG[58] NC SEG[19] SEG[59] NC SEG[20] SEG[60] NC SEG[21] SEG[61] COM[15] SEG[22] SEG[62] COM[14] SEG[23] SEG[63] COM[13] SEG[24] SEG[64] COM[12] SEG[25] SEG[65] COM[11] SEG[26] SEG[66] COM[10] SEG[27] SEG[67] COM[9] SEG[28] SEG[68] COM[8] SEG[29] SEG[69]

13 COORDINATE ( 1/18uty, SHL=0, 3-3) No. X Y No. X Y No. X Y 241 SEG[70] SEG[110] COM[6] SEG[71] SEG[111] COM[7] SEG[72] SEG[112] COM[8] SEG[73] SEG[113] COM[9] SEG[74] SEG[114] COM[10] SEG[75] SEG[115] COM[11] SEG[76] SEG[116] COM[12] SEG[77] SEG[117] COM[13] SEG[78] SEG[118] COM[14] SEG[79] SEG[119] COM[15] SEG[80] SEG[120] NC SEG[81] SEG[121] NC SEG[82] SEG[122] NC SEG[83] SEG[123] NC SEG[84] SEG[124] NC SEG[85] SEG[125] NC SEG[86] SEG[126] NC SEG[87] SEG[127] NC SEG[88] SEG[128] COMS SEG[89] SEG[129] COMS SEG[90] SEG[130] SEG[91] SEG[131] SEG[92] SEG[132] SEG[93] SEG[133] SEG[94] SEG[134] SEG[95] SEG[135] SEG[96] SEG[136] SEG[97] SEG[137] SEG[98] SEG[138] SEG[99] SEG[139] SEG[100] SEG[140] SEG[101] SEG[141] SEG[102] SEG[142] SEG[103] SEG[143] SEG[104] COM[0] SEG[105] COM[1] SEG[106] COM[2] SEG[107] COM[3] SEG[108] COM[4] SEG[109] COM[5]

14 COORDINATE ( 1/18uty, SHL=1, 3-1) No. X Y No. X Y No. X Y 1 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY V DUMMY V DUMMY V CLL DUMMY V DUMMY V CS1B DUMMY V CS DUMMY V DUMMY V RSTP DUMMY A DUMMY DUMMY RW DUMMY E DUMMY DUMMY D DUMMY D DUMMY D P VRAB D P D N D N D P D P P CLS P N C N VRS P PSB P N IRS N P P T[8] T[7] T[6]

15 COORDINATE ( 1/18uty, SHL=1, 3-2) No. X Y No. X Y No. X Y 121 T[5] COM[8] SEG[30] T[4] COM[9] SEG[31] T[3] COM[10] SEG[32] T[2] COM[11] SEG[33] T[1] COM[12] SEG[34] T[0] COM[13] SEG[35] DUMMY COM[14] SEG[36] DUMMY COM[15] SEG[37] DUMMY COMS SEG[38] DUMMY COMS SEG[39] DUMMY SEG[0] SEG[40] DUMMY SEG[1] SEG[41] DUMMY SEG[2] SEG[42] DUMMY SEG[3] SEG[43] DUMMY SEG[4] SEG[44] DUMMY SEG[5] SEG[45] DUMMY SEG[6] SEG[46] DUMMY SEG[7] SEG[47] DUMMY SEG[8] SEG[48] DUMMY SEG[9] SEG[49] DUMMY SEG[10] SEG[50] DUMMY SEG[11] SEG[51] DUMMY SEG[12] SEG[52] DUMMY SEG[13] SEG[53] NC SEG[14] SEG[54] NC SEG[15] SEG[55] NC SEG[16] SEG[56] NC SEG[17] SEG[57] NC SEG[18] SEG[58] NC SEG[19] SEG[59] NC SEG[20] SEG[60] NC SEG[21] SEG[61] COM[0] SEG[22] SEG[62] COM[1] SEG[23] SEG[63] COM[2] SEG[24] SEG[64] COM[3] SEG[25] SEG[65] COM[4] SEG[26] SEG[66] COM[5] SEG[27] SEG[67] COM[6] SEG[28] SEG[68] COM[7] SEG[29] SEG[69]

16 COORDINATE ( 1/18uty, SHL=1, 3-3) No. X Y No. X Y No. X Y 241 SEG[70] SEG[110] COM[9] SEG[71] SEG[111] COM[8] SEG[72] SEG[112] COM[7] SEG[73] SEG[113] COM[6] SEG[74] SEG[114] COM[5] SEG[75] SEG[115] COM[4] SEG[76] SEG[116] COM[3] SEG[77] SEG[117] COM[2] SEG[78] SEG[118] COM[1] SEG[79] SEG[119] COM[0] SEG[80] SEG[120] NC SEG[81] SEG[121] NC SEG[82] SEG[122] NC SEG[83] SEG[123] NC SEG[84] SEG[124] NC SEG[85] SEG[125] NC SEG[86] SEG[126] NC SEG[87] SEG[127] NC SEG[88] SEG[128] COMS SEG[89] SEG[129] COMS SEG[90] SEG[130] SEG[91] SEG[131] SEG[92] SEG[132] SEG[93] SEG[133] SEG[94] SEG[134] SEG[95] SEG[135] SEG[96] SEG[136] SEG[97] SEG[137] SEG[98] SEG[138] SEG[99] SEG[139] SEG[100] SEG[140] SEG[101] SEG[141] SEG[102] SEG[142] SEG[103] SEG[143] SEG[104] COM[15] SEG[105] COM[14] SEG[106] COM[13] SEG[107] COM[12] SEG[108] COM[11] SEG[109] COM[10]

17 COORDINATE ( 1/10 duty, SHL=0, 3-1) No. X Y No. X Y No. X Y 1 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY V DUMMY V DUMMY V CLL DUMMY V DUMMY V CS1B DUMMY V CS DUMMY V DUMMY V RSTP DUMMY A DUMMY DUMMY RW DUMMY E DUMMY DUMMY D DUMMY D DUMMY D P VRAB D P D N D N D P D P P CLS P N C N VRS P PSB P N IRS N P P T[8] T[7] T[6]

18 COORDINATE ( 1/18 duty, SHL=0, 3-2) No. X Y No. X Y No. X Y 121 T[5] COM[7] SEG[30] T[4] COM[6] SEG[31] T[3] COM[5] SEG[32] T[2] COM[4] SEG[33] T[1] COM[3] SEG[34] T[0] COM[2] SEG[35] DUMMY COM[1] SEG[36] DUMMY COM[0] SEG[37] DUMMY COMS SEG[38] DUMMY COMS SEG[39] DUMMY SEG[0] SEG[40] DUMMY SEG[1] SEG[41] DUMMY SEG[2] SEG[42] DUMMY SEG[3] SEG[43] DUMMY SEG[4] SEG[44] DUMMY SEG[5] SEG[45] DUMMY SEG[6] SEG[46] DUMMY SEG[7] SEG[47] DUMMY SEG[8] SEG[48] DUMMY SEG[9] SEG[49] DUMMY SEG[10] SEG[50] DUMMY SEG[11] SEG[51] DUMMY SEG[12] SEG[52] DUMMY SEG[13] SEG[53] NC SEG[14] SEG[54] NC SEG[15] SEG[55] NC SEG[16] SEG[56] NC SEG[17] SEG[57] NC SEG[18] SEG[58] NC SEG[19] SEG[59] NC SEG[20] SEG[60] NC SEG[21] SEG[61] NC SEG[22] SEG[62] NC SEG[23] SEG[63] NC SEG[24] SEG[64] NC SEG[25] SEG[65] NC SEG[26] SEG[66] NC SEG[27] SEG[67] NC SEG[28] SEG[68] NC SEG[29] SEG[69]

19 COORDINATE ( 1/18 duty, SHL=0, 3-3) No. X Y No. X Y No. X Y 241 SEG[70] SEG[110] COM[6] SEG[71] SEG[111] COM[7] SEG[72] SEG[112] NC SEG[73] SEG[113] NC SEG[74] SEG[114] NC SEG[75] SEG[115] NC SEG[76] SEG[116] NC SEG[77] SEG[117] NC SEG[78] SEG[118] NC SEG[79] SEG[119] NC SEG[80] SEG[120] NC SEG[81] SEG[121] NC SEG[82] SEG[122] NC SEG[83] SEG[123] NC SEG[84] SEG[124] NC SEG[85] SEG[125] NC SEG[86] SEG[126] NC SEG[87] SEG[127] NC SEG[88] SEG[128] COMS SEG[89] SEG[129] COMS SEG[90] SEG[130] SEG[91] SEG[131] SEG[92] SEG[132] SEG[93] SEG[133] SEG[94] SEG[134] SEG[95] SEG[135] SEG[96] SEG[136] SEG[97] SEG[137] SEG[98] SEG[138] SEG[99] SEG[139] SEG[100] SEG[140] SEG[101] SEG[141] SEG[102] SEG[142] SEG[103] SEG[143] SEG[104] COM[0] SEG[105] COM[1] SEG[106] COM[2] SEG[107] COM[3] SEG[108] COM[4] SEG[109] COM[5]

20 COORDINATE ( 1/10 duty, SHL=1, 3-1) No. X Y No. X Y No. X Y 1 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY V DUMMY V DUMMY V CLL DUMMY V DUMMY V CS1B DUMMY V CS DUMMY V DUMMY V RSTP DUMMY A DUMMY DUMMY RW DUMMY E DUMMY DUMMY D DUMMY D DUMMY D P VRAB D P D N D N D P D P P CLS P N C N VRS P PSB P N IRS N P P T[8] T[7] T[6]

21 COORDINATE ( 1/18 duty, SHL=1, 3-2) No. X Y No. X Y No. X Y 121 T[5] COM[0] SEG[30] T[4] COM[1] SEG[31] T[3] COM[2] SEG[32] T[2] COM[3] SEG[33] T[1] COM[4] SEG[34] T[0] COM[5] SEG[35] DUMMY COM[6] SEG[36] DUMMY COM[7] SEG[37] DUMMY COMS SEG[38] DUMMY COMS SEG[39] DUMMY SEG[0] SEG[40] DUMMY SEG[1] SEG[41] DUMMY SEG[2] SEG[42] DUMMY SEG[3] SEG[43] DUMMY SEG[4] SEG[44] DUMMY SEG[5] SEG[45] DUMMY SEG[6] SEG[46] DUMMY SEG[7] SEG[47] DUMMY SEG[8] SEG[48] DUMMY SEG[9] SEG[49] DUMMY SEG[10] SEG[50] DUMMY SEG[11] SEG[51] DUMMY SEG[12] SEG[52] DUMMY SEG[13] SEG[53] NC SEG[14] SEG[54] NC SEG[15] SEG[55] NC SEG[16] SEG[56] NC SEG[17] SEG[57] NC SEG[18] SEG[58] NC SEG[19] SEG[59] NC SEG[20] SEG[60] NC SEG[21] SEG[61] NC SEG[22] SEG[62] NC SEG[23] SEG[63] NC SEG[24] SEG[64] NC SEG[25] SEG[65] NC SEG[26] SEG[66] NC SEG[27] SEG[67] NC SEG[28] SEG[68] NC SEG[29] SEG[69]

22 COORDINATE ( 1/18 duty, SHL=1, 3-3) No. X Y No. X Y No. X Y 241 SEG[70] SEG[110] COM[1] SEG[71] SEG[111] COM[0] SEG[72] SEG[112] NC SEG[73] SEG[113] NC SEG[74] SEG[114] NC SEG[75] SEG[115] NC SEG[76] SEG[116] NC SEG[77] SEG[117] NC SEG[78] SEG[118] NC SEG[79] SEG[119] NC SEG[80] SEG[120] NC SEG[81] SEG[121] NC SEG[82] SEG[122] NC SEG[83] SEG[123] NC SEG[84] SEG[124] NC SEG[85] SEG[125] NC SEG[86] SEG[126] NC SEG[87] SEG[127] NC SEG[88] SEG[128] COMS SEG[89] SEG[129] COMS SEG[90] SEG[130] SEG[91] SEG[131] SEG[92] SEG[132] SEG[93] SEG[133] SEG[94] SEG[134] SEG[95] SEG[135] SEG[96] SEG[136] SEG[97] SEG[137] SEG[98] SEG[138] SEG[99] SEG[139] SEG[100] SEG[140] SEG[101] SEG[141] SEG[102] SEG[142] SEG[103] SEG[143] SEG[104] COM[7] SEG[105] COM[6] SEG[106] COM[5] SEG[107] COM[4] SEG[108] COM[3] SEG[109] COM[2]

23 PIN DESCRIPTION Pin I/O Description No. of Pins LCD driver outputs SEG 0 to O SEG 143 LCD segment driver outputs This display data and the FRR signal control the output voltage of segment driver. Display data FRR Segment driver output voltage Normal Reverse display display H H VLCD() V 2 H L V 3 L H V 2 VLCD() L L V 3 V SS Power save mode V SS V SS 144 LCD common driver outputs, each common signal has two identical outputs. This internal scanning data and FRR signal control the output voltage of common driver. COM 0 to COM 23 O Display data FRR Common driver output voltage Normal Reverse display display H H V SS H L VLCD() L H V 1 48 L L V 4 Power save mode V SS COMS1,COMS2 COMS3,COMS4 O Common output for the icons drive The output signals of COMS1 COMS2 pins are same. The output signals of COMS3 COMS4 pins are the same. When not used, this pin should be left open. 4 23

24 Pin I/O Description LCD Driver Setting pins and signal output pins PSB I Microprocessor interface select input pin PSB= H : parallel data input. PSB= L : serial data input. (3-lin/4-line SPI or IIC serial interface) No. of Pins 1 Input mode select C86 I PSB C86 Interface H H 8 bit or 4 bit 6800 parallel MPU interface L H 3-SPI/4-SPI serial interface L L IIC serial interface 1 Input/output. CLL I/O I/O selection 1 CLS = H :Output CLS = L :Input CLS I Oscillator select When the on-chip oscillator is used, this input must be connected to. When the external clock input is used, this input must be connected to. An external clock is connected to CLL pin. 1 This terminal selects the resistors for the voltage level adjustment. IRS I IRS = H : Use the internal resistors. 1 IRS = L : Do not use the internal resistors. The voltage level is regulated by an external resistive voltage divider attached to the VRAB terminal 24

25 Pin I/O Description System Bus Connection Pins CS1B,CS2 I Chip select input pins Data/instruction I/O is enabled only.when CS1B is L and CS2 is H. When chip select is non-active, DB0 to DB7 is high impedance. No. of Pins 2 RSTP A0 RW I I I Reset input pin When RSTP is L, initialization is executed. It determines whether the data bits are data or a command. A0=" H : Indicates that D0 to D7 are display data. A0=" L : Indicates that D0 to D7 are control data. There is no A0 pin in 3-SPI and IIC interface, so this pin can fix to H or L Read/Write execution control pin PIN Description Read/Write control input pin RW RW=" H : read RW=" L : write When in the serial interface must fixed to H ". Read only support parallel interface Read/Write execution control pin E I PIN E Description Read/Write control input pin RW=" H : When E is H ", D0 to D7 are in an output status. 1 RW=" L : The data on D0 to D7 are latched at the falling edge of the E signal. When in the serial interface must fixed to H ". 25

26 When the Parallel interface is selected (PSB=" H "& C86= H ): 8-bit interface 8-bit bi-directional data bus that is connected to the standard 8-bit microprocessor data bus. When chip select is not active, D0 to D7 is high impedance. (PSB=" H "& C86= H ): 4-bit interface In 4-bit mode, D4 to D7 connect to microprocessor data bus, the D0 to D3 connect to high impedance. When the serial interface is selected (PSB= L & C86= H ):3/4-line SPI Interface D7: serial input data (SI) D6: serial input clock (SCLK) D5, D4, D3, D2, D1, D0: must fixed to H.. When chip select is not active, D0 to D7 is high impedance. In 3-SPI interface, A0 pin must fixed to L When the IIC serial interface is selected (PSB= L & C86= L ): IIC Interface D0 is SA0 D1 is SA1 D5 to D0 D6/SDA/SCLK D7 /SI/SCL I/O SA1, SA0: Is slave address bit1 and bit0, must fixed to H or L. D2,D3 are SDA_OUT D4,D5,D6 are SDA_IN D7 is SCL 8 D6(SDA_IN): serial input data SDA_OUT: serial data acknowledge output for the I 2 C interface. D7(SCL): serial clock input By connecting SDA_OUT to SDA_IN externally, the SDA line becomes fully 2-line interface compatible. Having the acknowledge output separated from the serial data line is advantageous in chip on glass (COG) applications. In COG application where the track resistance from the SDA_OUT pad to the system SDA line can be significant, a potential divider is generated by the bus pull-up resistor and the ITO track resistance. It is possible the during the acknowledge cycle the RW1072 will not be able to create a valid logic 0 level. By splitting the SDA_IN input from the SDA_OUT output the device could be used in a mode that ignores the acknowledge bit. In COG applications where the acknowledge cycle is required, it is necessary to minimize the track resistance from the SDA_OUT pad to the system SDA line to guarantee a valid low level. All Pad of SDA_IN, SDA_OUT must be connected together (SDA) 26

27 Power Supply Pins 2 2 1P 1N 2P 2N 3P 4P 5P V1, V2, V3, V4 VRS VRAB Power Supply Power Supply Power Supply Power Supply O O O O O O O O Power Supply Power Supply I Digital Ground. The 2 supply rails and 2 must be connected 2 together at the FPC side Analog Ground The 2 supply rails and 2 must be connected 6 together at the FPC side Digital Supply voltage. The 2 supply rails V DD and V DD2 could be connected together. 8 If Digital Option pin is high, must be this level. Power supply for DC/DC voltage converter The 2 supply rails V DD and V DD2 could be connected together. 8 DC/DC voltage converter. Connect a capacitor between this terminal and. 8 If an external supply is used this pin must be left open. DC/DC voltage converter. Connect a capacitor between this terminal and the 1N terminal. 2 DC/DC voltage converter. Connect a capacitor between this terminal and the 1P terminal. 4 DC/DC voltage converter. Connect a capacitor between this terminal and the 2N terminal. 2 DC/DC voltage converter. Connect a capacitor between this terminal and the 2P terminal. 2 DC/DC voltage converter. Connect a capacitor between this terminal and the 1N terminal. 2 DC/DC voltage converter. Connect a capacitor between this terminal and the 2N terminal. 2 DC/DC voltage converter. Connect a capacitor between this terminal and the 1N terminal. 2 This is a multi-level power supply for the liquid crystal. V1 V2 V3 V4 16 Monitor Voltage Regulator level, must be left open. 1 Output voltage regulator terminal. Provides the voltage between and through a resistive voltage divider. IRS = L : the voltage regulator internal resistors are not used. IRS = H : the voltage regulator internal resistors are used. Dummy N.C 40 Test Pin T[0]~T[8] For test used. T[0]~T[8] must floating

28 RW1072 I/O PIN ITO resistance Limitation PIN ITO Resister C86, PSB, CLS,IRS No Limitation, 2,,2,,, VRAB <100Ω V1, V2, V3, V4, 1P, 1N, 2P, 2N, 3P, 4P, 5P <500Ω CS1B,CS2, E, RW, A0, D0~D7,CLL RSTP T[0]~T[8] Dummy <1KΩ <10KΩ Floating Floating 28

29 FUNCTION DESCRIPTION The MPU Interface RW1072 chip has four kinds interface type with MPU: IIC, 3-SPI,4-SPI and Parallel bus (4-bit/8-bit) are selected by PSB and C86 input, and 4-bit bus and 8-bit parallel bus is selected by IF bit in the instruction register. Through selecting the PSB and C86 terminal polarity to the H or L it is possible to select either parallel data input or serial data input as shown in Table 1. Table 1. Interface PSB C86 CS1B CS2 A0 E RW D7 D6 D5 D4 D3~D0 8-bit bit 6800 H H CS1B CS2 A0 E RW D7 D6 D5~D0 H H CS1B CS2 A0 E RW D7 D6 D5 D4 H 4-SPI L H CS1B H A0 H H SI SCLK H H H 3-SPI L H CS1B H L H H SI SCLK H H H IIC L L H H L H H SCL SDA_IN D2~D3:SDA_OUT D1~ D0:SA1~SA0 Parallel Interface: Parallel bus are selected by PSB and C86 input, and 4-bit and 8-bit parallel bus is selected by IF bit in the instruction register. During read or write operation, two 8-bit registers are used. One is data register (DR), the other is instruction register (IR). The data register (DR) is used as temporary data storage place for being written into or read from DDRAM/CGRAM/ICONRAM, target RAM is selected by RAM address setting instruction. Each internal operation, reading from or writing into RAM, is done automatically. So to speak, after MPU reads DR data, the data in the next DDRAM/CGRAM/ICONRAM address is transferred into DR automatically. Also after MPU writes data to DR, the data in DR is transferred into DDRAM/CGRAM/ICONRAM automatically. The Instruction register (IR) is used only to store instruction code transferred from MPU. MPU cannot use it to read instruction data. A0 RW Operation 0 0 Instruction write operation (MPU writes Instruction code into IR) 0 1 Read busy flag (DB7) and address counter (DB0 - DB6) 1 0 Data write operation (MPU writes data into DR) 1 1 Data read operation (MPU reads data from DR) 29

30 SPI Interface: When the SPI interface has been selected (PSB= L,C86= H ),then it is possible to connect directly to an MPU through 4 pins serial interface configuration (A0,CS1B, SCLK, SI pin) or 3 pins serial interface (CS1B, SCLK, SI pin) configuration. Pins configuration is only difference between 4-SPI and 3-SPI. Interface PSB C86 CS1B CS2 A) E RW D7 D6 D5~D0 4SPI L H CS1B H A0 H H SI SCLK H 3SPI L H CS1B H L H H SI SCLK H The 4-SPI serial interface (PSB= L, C86= H ) When 4 pins serial interface configuration is used, A0 is used to realize incoming data is instruction/display data. A0 must be a certain state ( L or H ) when chip is in active mode (CS1B= L, and CS2= H ). A0 can t be kept tri-state or floating when chip is in active mode. It should be fine if A0 is low while power up. The 4-SPI example of timing sequence is shown below Figure 1. Figure 1 4-SPI timing sequence 30

31 The 3-SPI serial interface (PSB= L, C86= H ) When 3 pins serial interface configuration is used, A0 must be kept L or connected to. Data length instruction is used to realize incoming data is instruction/display data.ic will recognize the incoming data that after Set Data length for 3-SPI instruction as display data. User must set data length of the incoming data that after Data length instruction. Interface PSB C86 CS1B CS2 A0 E RW D7 D6 D5~D0 4-SPI L H CS1B H A0 H H SI SCLK H 3-SPI L H CS1B H L H H SI SCLK H The 3-SPI example of timing sequence is shown below Figure2; data length instruction is followed by Display data set. Figure 2 3-SPI timing sequence * When the chip is not active, the shift registers and the counter are reset to their initial states. * Reading is not possible while in serial interface mode (3-SPI,4-SPI and IIC interface). * Caution is required on the SCLK signal when it comes to line-end reflections and external noise. We recommend that operation be rechecked on the actual equipment. 31

32 IIC Interface(PSB= L, C86= L ) The IIC interface receives and executes the commands sent via the IIC Interface. It also receives RAM data and sends it to the RAM. The IIC Interface is for bi-directional, two-line communication between different ICs or modules. The two lines are a Serial Data line SDA and a Serial Clock line SCL. Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy. BIT Transfer One data bit is transferred during each clock pulse. The data on the SDA(DB6) line must remain stable during the HIGH period of the clock pulse because changes in the data line at this time will be interpreted as a control signal. Bit transfer is illustrated in Figure 3. START AND STOP CONDITIONS Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P). The START and STOP conditions are illustrated in Figure 4 SYSTEM CONFIGURATION The system configuration is illustrated in Figure 5. Transmitter: the device, which sends the data to the bus. Receiver: the device, which receives the data from the bus. Master: the device, which initiates a transfer, generates clock signals and terminates a transfer. Slave: the device addressed by a master. ACKNOWLEDGE Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. A master receiver must also generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock Multi-Master: more than one master can attempt to control the bus at the same time without corrupting the message. Arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted. Synchronization: procedure to synchronize the clock signals of two or more devices. pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end-of-data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledgement on the IIC Interface is illustrated in Figure. 32

33 SDA SCL data line stable; data valid change of data allowed Figure 3. Bit transfer SDA SCL S P START con dition STOP con dition Figure 4 Definition of START and STOP conditions MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER (1) SLAVE RECEIVER (2) SLAVE RECEIVER (3) SLAVE RECEIVER (4) SDA SCL Figure 5 System configuration DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER SCL FROM MASTER S START condition not acknowledge acknowledge clock pulse for acknowledge ment Figure 6 Acknowledgement on the 2-line Interface 33

34 IIC Interface Protocol The RW1072 supports command, data write addressed slaves on the bus. Before any data is transmitted on the IIC Interface, the device, which should respond, is addressed first. Four 7-bit slave addresses ( , , and ) are reserved for the RW1072. The least significant bit of the slave address is set by connecting the input (D0) SA0 and (D1) SA1 to either logic 0 () or logic 1 (). The IIC Interface protocol is illustrated in Figure 7. The sequence is initiated with a START condition (S) from the IIC Interface master, which is followed by the slave address. All slaves with the corresponding address acknowledge in parallel, all the others will ignore the IIC Interface transfer. After acknowledgement, one or more command words follow which define the status of the addressed slaves. A command word consists of a control byte, which defines Co and A0, plus a data byte. The last control byte is tagged with a cleared most significant bit (i.e. the continuation bit Co). After a control byte with a cleared Co bit, only data bytes will follow. The state of the A0 bit defines whether the data byte is interpreted as a command or as RAM data. All addressed slaves on the bus also acknowledge the control and data bytes. After the last control byte, depending on the A0 bit setting; either a series of display data bytes or command data bytes may follow. If the A0 bit is set to logic 1, these display bytes are stored in the display RAM at the address specified by the data pointer. The data pointer is automatically updated and the data is directed to the intended RW1072 device. If the A0 bit of the last control byte is set to logic 0, these command bytes will be decoded and the setting of the device will be changed according to the received commands. Only the addressed slave makes the acknowledgement after each byte. At the end of the transmission the IIC INTERFACE-bus master issues a STOP condition (P). Figure 7 2-line Interface protocol Last control byte to be sent. Only a stream of data bytes is allowed to follow. 0 This stream may only be terminated by s STOP or RE-START condition. Co Another control byte will follow the data byte unless a STOP or RE-START condition is 1 received. * Reading is not possible while in serial interface mode (3-SPI,4-SPI and IIC interface). 34

35 The Chip Select The RW1072 have two chips select terminals: CS1B and CS2. The MPU interface or the serial is enable only when CS1B= L and CS2= H. When the chip select is inactive, DB0 to DB7 enter a high impedance state, and the A0, E and RW inputs are inactive. When the serial interface is selected, the shift register and the counter are reset. Busy Flag (BF) When BF = High, it indicates that the internal operation is being processed. So during this time the next instruction cannot be accepted. BF can be read, when A0 = L and RW = H (Read Instruction Operation), through the DB7 port. Before executing the next instruction, be sure that BF is not high. Address Counter (AC) Address counter(ac)is used for address pointer of DDRAM/ICONRAM. (AC) can be set by instruction and after data read or write to the memories (AC) will increase or decrease by 1 according to the setting in entry mode set. When A0= 0 and RW= 1 and E= 1 the value of(ac)will output to DB6~DB0. Cursor/Blink Control Circuit It controls cursor/blink ON/OFF and black/white inversion at cursor position. LCD Driver Circuit LCD driver have 26 commons and 144 segments to drive the LCD panel. Segment data from CGRAM /CGROM /ICONRAM are shifted into the 144 bits segment latches serially, and then it is stored to 144 bit shift latch. When each COM is selected by 26 bits common register, segment data also output through segment driver from 144 bits segment latch. Please refer below display duty mode: 1-line display mode, COM0-COM7 and COMS1/COMS2/COMS3/COMS4 have 1/10 duty. 2-line display mode, COM0-COM15 and COMS1/COMS2/COMS3/COMS4 have 1/18 duty. 3-line display mode, COM0-COM23 and COMS1/COMS2/COMS3/COMS4 have 1/26 duty. Timing Generation Circuit The timing generation circuit generates clock signals for internal operations. 35

36 Display Data RAM (DDRAM) DDRAM stores display data of maximum 80 8 bits (80 characters). DDRAM address is set in the address counter (AC) as a hexadecimal number (Refer to Figure 8). MSB LSB AC6 AC5 AC4 AC3 AC2 AC1 AC0 Figure 8. DDRAM Address (1) 5-dots font 1-line display In the case of a 1-line display with 5-dots font, the address range of DDRAM is 00H ~ 4FH. (Refer to Figure 9). Figure 9.1-line display (5 *8 dots font width) 1-line X 28Characters Display Example (5 *8 dots font width) 36

37 (2) 5-dots font 2-line display In the case of a 2-line display with 5-dots font, the address range of DDRAM is 00H 27H, and 40H 67H. (Refer to Figure 10). Figure 10.2-line display (5 *8 dots font width) 2-line X 28Characters Display Example (5 *8 dots font width) 37

38 (3) 5-dots font 3-line display In the case of a 3-line display with 5-dots font, the address range of DDRAM is 00H 1AH, 20H 3AH, 40H 5AH. (Refer to Figure 11). Figure 11.3-line display (5 *8 dots font width) 2-line X 26Characters Display Example (5 *8 dots font width) 38

39 (1) 6-dots font 1-line display In the case of a 1-line display with 6-dots font, the address range of DDRAM is 00H 4FH. (Refer to Figure 12) Figure 12.1-line display (6 *8 dots font width) 1-line X 24Characters Display Example (6 *8 dots font width) 39

40 (2) 6-dots font 2-line display In the case of a 2-line display with 6-dost font, the address range of DDRAM is 00H 27H, and 40H 67H. (Refer to Figure 13) Figure 13.2-line display (6 *8 dots font width) 2-line X 24Characters Display Example (6 *8 dots font width) 40

41 (3) 6-dots font 3-line display In the case of a 4-line display with 6-dots font, the address range of DDRAM is 00H 17H, 20H 37H, 40H 57H. (Refer to Figure 14) Figure 14.3-line display (6 *8 dots font width) 3-line X 24Characters Display Example (6 *8 dots font width) 41

42 CGRAM (Characters Generator RAM) RW1072 provides RAM to support 80 sets 6*8 dots font (or 5*8 dots font) user-defined fonts when GM register is set to 1, 16 sets 6*8 dots font ( or 5*8 dots font) user-defined fonts when GM register is sets to 0. These user-defined characters are displayed the same ways as CGROM fonts through writing character font code B0H ~ FFH (when GM =1), or 00H ~ 0FH (when GM =0) to DDRAM. (Refer to Table 2) Table 2 Relationship between CGRAM Address and CGRAM Pattern DDRAM DATA (FONT CODE) CGRAM ADDRESS CGRAM DATA D7~D4 D3 D2 D1 D0 A6 A5 A4 A3 A2 A1 A0 C2 C1 C0 D5 D4 D3 D2 D1 D0 0000(GM=0) 1011(GM=1) 0000(GM=0) 1011(GM=1) 0000(GM=0) 1011(GM=1) *8 dots font CGRAM Pattern 42

43 DDRAM DATA (FONT CODE) CGRAM ADDRESS CGRAM DATA D7~D4 D3 D2 D1 D0 A6 A5 A4 A3 A2 A1 A0 C2 C1 C0 D5 D4 D3 D2 D1 D0 0000(GM=0) 1011(GM=1) 0000(GM=0) 1011(GM=1) 0000(GM=0) 1011(GM=1) (GM=0) 1111(GM=1) User-defined Data (GM=0) (GM=1) 5*8 dots font CGRAM Pattern 43

44 DDRAM DATA (FONT CODE) CGRAM ADDRESS CGRAM DATA D7~D4 D3 D2 D1 D0 A6 A5 A4 A3 A2 A1 A0 C2 C1 C0 D5 D4 D3 D2 D1 D0 0000(GM=0) 1011(GM=1) 0000(GM=0) 1011(GM=1) 0000(GM=0) 1011(GM=1) *8 dots font CGRAM Pattern

45 DDRAM DATA (FONT CODE) CGRAM ADDRESS CGRAM DATA D7~D4 D3 D2 D1 D0 A6 A5 A4 A3 A2 A1 A0 C2 C1 C0 D5 D4 D3 D2 D1 D (GM=0) 1011(GM=1) 0000(GM=0) 1011(GM=1) 0000(GM=0) 1011(GM=1) (GM=0) 1111(GM=1) User-defined Data (GM=0) (GM=1) Note: 6*8 dots font CGRAM Pattern 1. CGRAM address bit3 ~ bit9 can be specified by set CGRAM address command, bit0~bit2 are not accessible by user. 2. CGRAM data for each address is 6 bits for 6*8 dots font. 45

46 ICONRAM (Segment RAM) RW1072 has two SEGRAMs which have segment pattern data. COMS1 and COMS2 act as the COM line to display the ICONRAM1 data. COMS3 and COMS4 act as the COM line to display the ICONRAM2 data. The outputs of COMS1 and COMS2 pins are identical; the outputs of COMS3 and COMS4 are identical. The pattern data of SEGRAMs are refer to Table3 and Figure 15. Table3. Relationship between ICONRAM1 and ICONRAM2 addresses and display pattern Set ICON1 RAM Address ICONRAM1 Data Display Pattern 5-dots font width (FW=0) 6-dots font width (FW=1) A4 A3 A2 A1 A0 D5 D4 D3 D2 D1 D0 D5 D4 D3 D2 D1 D X S0 S1 S2 S3 S4 S0 S1 S2 S3 S4 S X S5 S6 S7 S8 S9 S6 S7 S8 S9 S10 S X S10 S11 S12 S13 S14 S12 S13 S14 S15 S16 S X S15 S16 S17 S18 S19 S18 S19 S20 S21 S22 S X S20 S21 S22 S23 S24 S24 S25 S26 S27 S28 S X S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S X S30 S31 S32 S33 S34 S36 S37 S38 S39 S40 S X S35 S36 S37 S38 S39 S42 S43 S44 S45 S46 S X S40 S41 S42 S43 S44 S48 S49 S50 S51 S52 S X S45 S46 S47 S48 S49 S54 S55 S56 S57 S58 S X S50 S51 S52 S53 S54 S60 S61 S62 S63 S64 S X S55 S56 S57 S58 S59 S66 S67 S68 S69 S70 S X S60 S61 S62 S63 S64 S72 S73 S74 S75 S76 S X S65 S66 S67 S68 S69 S78 S79 S80 S81 S82 S X S70 S71 S72 S73 S74 S84 S85 S86 S87 S88 S X S75 S76 S77 S78 S79 S90 S91 S92 S93 S94 S X S80 S81 S82 S83 S84 S96 S97 S98 S99 S100 S X S85 S86 S87 S88 S89 S102 S103 S104 S105 S106 S X S90 S91 S92 S93 S94 S108 S109 S110 S111 S112 S X S95 S96 S97 S98 S99 S114 S115 S116 S117 S118 S X S100 S101 S102 S103 S104 S120 S121 S122 S123 S124 S X S105 S106 S107 S108 S109 S126 S127 S128 S129 S130 S X S110 S111 S112 S113 S114 S132 S133 S134 S135 S136 S X S115 S116 S117 S118 S119 S138 S139 S140 S141 S142 S X S120 S121 S122 S123 S124 X X X X X X X S125 S126 S127 S128 S129 X X X X X X X S130 S131 S132 S133 S134 X X X X X X X S135 S136 S137 S138 S139 X X X X X X Note: 1. S0~S139: Icon pattern in 5-dots font width,s0~s143: Icon pattern in 6-dots font width 2. X : Don t care 46

47 Set ICON2 RAM Address ICONRAM2 Data Display Pattern 5-dots font width (FW=0) 6-dots font width (FW=1) A4 A3 A2 A1 A0 D5 D4 D3 D2 D1 D0 D5 D4 D3 D2 D1 D X S0 S1 S2 S3 S4 S0 S1 S2 S3 S4 S X S5 S6 S7 S8 S9 S6 S7 S8 S9 S10 S X S10 S11 S12 S13 S14 S12 S13 S14 S15 S16 S X S15 S16 S17 S18 S19 S18 S19 S20 S21 S22 S X S20 S21 S22 S23 S24 S24 S25 S26 S27 S28 S X S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S X S30 S31 S32 S33 S34 S36 S37 S38 S39 S40 S X S35 S36 S37 S38 S39 S42 S43 S44 S45 S46 S X S40 S41 S42 S43 S44 S48 S49 S50 S51 S52 S X S45 S46 S47 S48 S49 S54 S55 S56 S57 S58 S X S50 S51 S52 S53 S54 S60 S61 S62 S63 S64 S X S55 S56 S57 S58 S59 S66 S67 S68 S69 S70 S X S60 S61 S62 S63 S64 S72 S73 S74 S75 S76 S X S65 S66 S67 S68 S69 S78 S79 S80 S81 S82 S X S70 S71 S72 S73 S74 S84 S85 S86 S87 S88 S X S75 S76 S77 S78 S79 S90 S91 S92 S93 S94 S X S80 S81 S82 S83 S84 S96 S97 S98 S99 S100 S X S85 S86 S87 S88 S89 S102 S103 S104 S105 S106 S X S90 S91 S92 S93 S94 S108 S109 S110 S111 S112 S X S95 S96 S97 S98 S99 S114 S115 S116 S117 S118 S X S100 S101 S102 S103 S104 S120 S121 S122 S123 S124 S X S105 S106 S107 S108 S109 S126 S127 S128 S129 S130 S X S110 S111 S112 S113 S114 S132 S133 S134 S135 S136 S X S115 S116 S117 S118 S119 S138 S139 S140 S141 S142 S X S120 S121 S122 S123 S124 X X X X X X X S125 S126 S127 S128 S129 X X X X X X X S130 S131 S132 S133 S134 X X X X X X X S135 S136 S137 S138 S139 X X X X X X Note: 3. S0~S139: Icon pattern in 5-dots font width,s0~s143: Icon pattern in 6-dots font width 4. X : Don t care 47

48 5-dots font width (FW=0) 6-dots font width (FW=1) Figure 15.Relationship between ICONRAM Display 48

49 Power Supply Circuit The Power Supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low power consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. They are controlled by power control instruction. Table 4 shows the referenced combinations in using Power Supply circuits. Table 4 shows the referenced combinations in using Power Supply circuits. Power User setup Power Control set (VB VR VF) Control set HEX VB circuit VR circuit VF circuit V1 to V4 code External power supply used x18H OFF OFF OFF External input External input External input Only booster circuit used x1CH ON OFF OFF Internal External input External input booster circuit and regulator circuit used x1EH ON ON OFF Internal Internal External input Internal power supply circuit used x1FH ON ON ON Internal Internal Internal 49

50 Voltage Converter Circuits (Capacitor type booster circuit) Using the step-up voltage circuits equipped within the RW1072 chips it is possible to product a 2X,3X,4X,5X or 6X step-up of the 2 voltage levels. 2X set-up: Connect capacitor C1 between C1N and C1P, between and, leave C2N open and short between C2P, C3P, C4P C5P to. 3X set-up: Connect capacitor C1 between C1N and C1P, between C2N and C2P, and between and, and short between C3P, C4P C5P to. 4X set-up: Connect capacitor C1 between C1N and C1P, between C2N and C2P, between C1N and C3P, between and, short between C4P,C5P to. 5X set-up: Connect capacitor C1 between C1N and C1P, between C2N and C2P, between C1N and C3P, between C2N and C4P, and between and, short between C5P to. 6X set-up: Connect capacitor C1 between C1N and C1P, between C2N and C2P, between C1N and C3P, between C2N and C4P, between C1N and C5P, and between and * The 2 voltage range must be set so that the terminal voltage does not exceed the absolute maximum rated value. 50

51 Voltage Regulator Circuits The function of the internal Voltage Regulator circuits is to determine liquid crystal operating voltage,, by adjusting resistors, Ra and Rb, within the range of <. Because is the operating voltage of operational-amplifier circuits shown in Figure 16.,it is necessary to be applied internally or externally. For the Eq. 1, we determine by Ra, Rb and VEV. The Ra and Rb are connected internally or externally by IRS pin. And VEV called the voltage of electronic volume is determined by Eq. 2, where the parameter is the value selected by instruction, "Set Reference Voltage Register", within the range 0 to 63. VREF voltage at Ta= 25 o C is shown in Table

52 In Case of Using Internal Resistors, Ra and Rb (IRS = H ) When IRS pin is "H", resistor Ra is connected internally between VR pin and, and Rb is connected between and VR. We determine by two instructions, Select Regulator Resistor " and "Select electronic Volume Register". Table 6. Internal Rb / Ra Ratio depending on 3-bit Data (R2 R1 R0) 3-bit data settings (R2 R1 R0) (Rb /Ra) Figure 17.shows voltage measured by adjusting internal regulator register ratio (Rb / Ra) and 6-bit electronic volume registers for each temperature coefficient at Ta = 25 o C. Figure17. Electronic Volume register (α=0 to 63) Table 8.Shows the Range of depending on the above Requirements. Ratio=000~111 0x00H (α=63) Table 8.The Range of voltage Electronic Volume level (EV Value) x3FH (α=0) voltage 4.25V V 52

53 In Case of Using External Resistors, Ra and Rb (IRS = L ) When IRS pin is "L", it is necessary to connect external regulator resistor Ra between VR and, and Rb between and VR. Example: For the following requirements 1. LCD driver voltage, = 10.0V bit reference voltage register = (1, 0, 0, 0, 0, 0) 3. Maximum current flowing Ra, Rb = 1.5 ua From Eq. 1 53

54 Voltage Follower Circuits voltage (VLCD) is resistively divided into four voltage levels (V1, V2, V3 and V4), and those output impedance are converted by the Voltage Follower for increasing drive capability. Table 9 shows the relationship between V1 to V4 level and each duty ratio. Table 9.The Relationship between V1 to V4 Level and Each Duty Ratio LCD bias V1 V2 V3 V4 Remarks 1/N (N-1)/N x (N-2)/N x 2/N x 1/N x N = 4 o 7 1/N (N-1)/N x (N-2)/N x (N-2)/N x (N-3)/N x N= 4 Follower voltage reference circuit: Internal Booster: 54

55 Internal Booster: 55

56 RESET CIRCUIT A. Initializing by Internal Reset Circuit When the power is turned on, RW1072 is initialized automatically by power on reset circuit. During the initialization, the following instructions are executed, and BF (Busy Flag) is kept "High"(busy state) to the end of initialization. After power-on, RAM data are undefined (3) Clear Display: Write "20H" to all DDRAM (5) Entry Mode Set: I/D=1, S=0 (6) Cursor or Display Shift: S/C=0, R/L=0 (7) Display ON/OFF: D=0, C=0, B=0 (6) Function Set and Display Set: IF=1,N=1,NH=0,FW=1,RE=0 (13) Power Down Mode: PD=0 (14) COM/SEG Scan Direction Set: SHL=0, BID=0 (15) Display Shift Control Set: DS3, DS2, DS1=0, 0, 0 (16) Cursor Blink and Display Reverse Set: REV=0, B/W=0 (17) Select LCD Bias: BS1, BS0=0, 1 (1/5 Bias) (18) Power Control Set: VB=0, VR=0, VF=0 (20) Select Regulator Resistor: R2, R1, R0=0, 1, 1 (21) Select Electronic Volume Register: EV5, EV4, EV3, EV2, EV1, E=1, 0, 0, 0, 0, 0 (22) Set Data Length: SD7, SD6, SD5, SD4, SD3, SD2, SD1, SD0=0, 0, 0, 0, 0, 0, 0, 0 (23) Frame Frequency Adjustment: DF3, DF2, DF1, DF0=0, 0, 0, 0 (24) Double Frame Frequency: FRR*2=0 B. Initializing by Hardware Pin RSTP Input When RSTP pin = "Low", RW1072 can be initialized as in the case of power on reset. During the power on reset operation, this pin is ignored. While RSTP is L or reset instruction is executed, no instruction except read status can be accepted, any instruction can be accepted. RSTP must be connected to the reset pin of the MPU, and initialize the MPU and this LSI at the same time. The initialization by RSTP is essential before used. 56

57 INSTRUCTION TABLE RW1072 Instruction Table (Function Set RE=0) Instruction A0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description (1) Read display data 1 1 Read data Read data into DDRAM/CGRAM/ICONRAM Execution (2) Write display data 1 0 Write data Write data into DDRAM/CGRAM/ICONRAM 36uS Time 36uS (3) Clear Display (4) Return Home X (5) Entry Mode Set I/D S (6) Cursor or Display Shift Set S/C R/L X X (7) Display ON/OFF D C B (8) Function Set and RE IF N NH FW Display Set (0) Write "20H" to DDRAM, and set DDRAM address to "00H" from AC Set DDRAM address to "00H" from AC and return cursor to its original position if shifted. The contents of DDRAM are not changed. Assign cursor moving direction. I/D="1": increment (Default) I/D="0": decrement And entire display shift enable bit. S= 0 :Shift of entire display is performed S= 1 :Shift of entire display is not performed Cursor or Display Shift S/C="1": display shift S/C="0": cursor shift R/L="1": shift to right R/L="0": shift to left Set Display /Cursor/Blink ON/OFF D="1": display on D="0": display off C="1": cursor on C="0": cursor off B="1": blink on B="0": blink off Set Interface Data Length: IF="1": 8-bit interface IF="0": 4-bit interface NH="0", N="1": 2line display NH="0", N="0": 1line display NH="1", N="0" :3 line display FW="1", 6*8 font select FW="0", 5*8 font select RE="1" : extended instruction table select RE="0" : basic instruction table set 1.54mS 1.54mS 36uS 36uS 36uS 36uS (9) Set DDRAM Address AC6 AC5 AC4 AC3 AC2 AC1 AC0 Set DDRAM address in address counter 36uS (10) Set ICON1 RAM Address A4 A3 A2 A1 A0 Set ICON RAM1 address in address counter 36uS (11) Set ICON2 RAM Address (12) Read Busy Flag and Address A4 A3 A2 A1 A0 0 1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0 Set ICON RAM2 address in address counter Can know internal operation is ready or not by reading BF. The contents of address counter can also be read. BF="1": busy state BF="0": ready state 36uS 0uS 57

58 RW1072 Instruction Table (Extended Function Set RE=1) Instruction A0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description (1) Read Display Data (2) Write Display Data 1 1 Read data 1 0 Write data 58 Read data into DDRAM/CGRAM/ICONRAM Write data into DDRAM/CGRAM/ICONRAM (3) Clear Display Write "20H" to DDRAM, and set DDRAM address to "00H" from AC (13) Power Down Set power down mode PD PD="1": power down mode enable Mode PD="0": power down mode disable(default) Segment bi-direction function (14) COM/SEG Scan BID="1": Seg > Seg 0(Default) Direction Set SHL BID BID="0": Seg 0--> Seg 143 SHL= 0 :COM scan is normal(default) SHL= 1 :COM scan direction is reverse (15) Display Shift Control Set (16) Cursor Blink and Display Reverse Set (17) Select LCD Bias (18) Power Control Set (19) Extended Function Set and Display Set (20) Select Regulator Resistor (21) Select Electronic Volume Register (22) Set Data Length for 3-SPI (23) Frame Frequency Adjustment (24) Double Frame Frequency (25) Set CGRAM Address DS3 DS2 DS REV B/W BS1 BS VB VR VF IF N NH GM RE (1) Determine the line for display shift DS1= 1/0 :1 st line display shift enable/disable DS2= 1/0 :2 nd line display shift enable/disable DS3= 1/0 :3 rd line display shift enable/disable Assign black/white inverting of cursor REV= 1 :display reverse REV= 0 :display normal B/W= 1 :black/white inverting of cursor enable B/W= 0 : black/white inverting of cursor disable Select LCD bias 1/4 bias ~ 1/7 bias 00:1/4 bias 01:1/5 bias (Default) 10: 1/6 bias 11:1/7 bias Control power circuit ON/OFF VB= 0 :booster circuit off (Default) VB= 1 :booster circuit on VR= 0 :regulator circuit off(default) VR= 1 :regulator circuit on VF= 0 :follower circuit off(default) VF= 1 :follower circuit on Set Interface Data Length: IF="1": 8-bit interface IF="0": 4-bit interface NH="0", N="1": 2line display NH="0", N="0": 1line display NH="1", N="0" :3 line display GM="1",Graphic+characters mode select GM="0", character mode select RE="1" : extended instruction table select RE="0" : basic instruction table set Select Internal resistance ratio of the R2 R1 R0 regulator resistor (Default: 011) EV5 EV4 EV3 EV2 EV1 E Set the output voltage electronic volume register(default:100000) Set Data Length for 3-SPI interface SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD Adjustment Frame Frequency 0001(Slow) ->1111 (Fast) DF3 DF2 DF1 DF0 Default: Double Frame Frequency FRR *2 FRR*2=1: frame frequency *2 FRR*2=0: frame frequency normal (Default) Execution Time 36uS 36uS 1.54mS A6 A5 A4 A3 A2 A1 A0 Set CGRAM Address in address counter 36uS 36uS 36uS 36uS 36uS 36uS 36uS 36uS 36uS 36uS 36uS 36uS 36uS

59 Description of Instruction (1) Read Display Data Instruction A0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Read Display Data 1 1 Read data Read data from internal RAM and alter the (Address Counter) by1. After address set to read (CGRAM/DDRAM/ICONRAM) a DUMMY READ is required. There is no need to DUMMY READ for the following bytes unless a new address set Instruction is issued. (2) Write Display Data Instruction A0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Write Display Data 1 0 Write data Write binary 8-bit data to DDRAM/CGRAM/ICONRAM. The selection of RAM from DDRAM, CGRAM, or ICONRAM is set by the previous address set instruction: DDRAM address set, CGRAM address set, ICONRAM address set. RAM set instruction can also determine the AC direction to RAM. After write operation, the address is automatically Increased / Decreased by 1, according to the entry mode. (3) Clear Display Instruction A0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Clear Display Clear all the display data by writing 20H (space code) to all DDRAM address, and set DDRAM address to 00H into AC (address counter).return cursor to the original status, b ringing the cursor to the left edge on first line of the display. Make entry mode increment (I/D = 1 ). 59

60 (4) Return Home (Function Set RE=0) Instruction A0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Return home X Return Home is a cursor return home instruction. Set DDRAM address to 00H into the address counter. Return cursor to its original site and return display to its original status, if shifted. A content of DDRAM does not change. (5) Entry Mode Set (Function Set RE=0) Instruction A0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Entry Mode Set I/D S Set the moving direction of cursor and display. I/D: Increment / Decrement of DDRAM address (cursor or blink) When I/D=1, cursor/blink moves to right and DDRAM address is increased by 1. When I/D=0, cursor/blink moves to left and DDRAM address is decreased by 1. CGRAM/ICONRAM operates the same as DDRAM, when reading from or writing to CGRAM/ICONRAM S: Shift of entire display When S=0, shift of entire display is not performed When S=1, after DDRAM write, the display of enabled line by DS1 DS3 bits in the Display Shift Set(enable) instruction is shifted to the right (I/D = 0 ) or to the left (I/D = 1 ). But it will seem as if the cursor does not move. (6) Cursor or Display Shift Set (Function Set RE=0) Instruction A0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Cursor or Display Shift Set S/C R/L X X Instruction to move the cursor shift entire display, the content of DDRAM is not changed. S/C R/L Description AC value 0 0 Cursor moves left by 1 AC=AC Cursor moves right by 1 AC=AC Display shift left by 1,cursor also follows to shift AC=AC 1 1 Display shift right by 1,cursor also follows to shift AC=AC 60

61 (7) Display ON/OFF (Function Set RE=0) Instruction A0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display ON/OFF D C B D: Display ON/OFF control bit When D= 1 : Display turn on When D= 0 : Display turn off, but the display data is remained in DDRAM. C: Cursor ON/OFF control bit When C= 1 : Cursor turn on When C= 0 : Cursor turn off B: Cursor Blink ON/OFF control bit When B= 1 : Cursor position blink on. Then display data in cursor position will blink. When B= 0 : Cursor position blink off. (8) Function Set and Display Set (Function Set RE=0) Instruction A0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function Set and Display Set IF N NH FW IF: Interface Data Length Set When IF= 0, it means 4-bit bus mode with MPU When IF= 1, it means 8-bit bus mode with MPU Hence, IF is a signal to select 8-bit or 4-bit bus mode. In 4-bit bus mode, it is required to transfer 4-bit data twice. N, NH: Display Line Mode S e t N NH Display Line Mode line Display line Display line Display FW: Dots Font Width Set When FW= 0 :5*8 dots font width is set When FW= 1 :6*8 dots font width is set The user font, specified in CGRAM, is displayed into 6-dot font width, bit-5 to bit-0, including the left space bit of CGRAM RE: Extended Instruction Table Registers Enable Bit When RE= 0, basic function set registers can be accessed. (see Table 6.1) (default) When RE = 1, extended function set registers can be accessed. (see Table 6.2) At this instruction, RE must be Low. 61 RE (0)

62 (9) Set DDRAM Address (Function Set RE=0) Instruction A0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Set DDRAM Address AC6 AC5 AC4 AC3 AC2 AC1 AC0 Set DDRAM address to AC. This instruction makes DDRAM data available from MPU. In 1-line display mode (N=0, NH=0), DDRAM address is from 00H to 4FH. In 2-line display mode (N=1, NH=0), DDRAM address in the 1st line is from 00H to 27H, and DDRAM address in the 2nd line is from 40H to 67H. In 3-line display mode (NH=1,FW=0), DDRAM address is from 00H to 1BH in the 1st line, from 20H to 3BH in the 2nd line, from 40H to 5BH in the 3rd line. In 3-line display mode (NH=1,FW=1), DDRAM address is from 00H to 17H in the 1st line, from 20H to 37H in the 2nd line, from 40H to 57H in the 3rd line. (10) Set ICON1 RAM Address (Function Set RE=0) Instruction A0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Set ICON1 RAM Address A4 A3 A2 A1 A0 Set ICON1 RAM address to AC. This instruction makes ICON2 RAM data available on COMS1/COMS2 from MPU. (11) Set ICON2 RAM Address (Function Set RE=0) Instruction A0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Set ICON2 RAM Address A4 A3 A2 A1 A0 Set ICON2 RAM address to AC. This instruction makes ICON2 RAM data available on COMS3/COMS4 from MPU. 62

63 (12) Read Busy Flag and Address (Function Set RE=0) RW1072-0A-001 Instruction A0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Read Busy Flag and Address 0 1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0 This instruction shows whether RW1072 is in internal operation or not. If the resultant BF is High, The internal operation is in progress and should wait until BF to be Low, which by then the next instruction can be performed. In this instruction the value of address counter can also be read. (13) Power Down Mode (Extended Function Set RE=1) Instruction A0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Power Down Mode PD Power down mode enable bit When PD= 0 : power down mode become disable When PD= 1 : power down mode enable When power down is enable, it makes RW1072 suppress current consumption except the current of internal OSC. 1. All COM/SEG output is 2. Turn off analog circuit (14) COM/SEG Direction Set (Extended Function Set RE=1) Instruction A0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 COM/SEG Direction Set SHL BID BID: Segment bi-direction function BID= 0, segment data shift direction is set to normal order, from SEG 0 to SEG N BID= 1, segment data shift direction is set reversely, from SEG N to SEG 0. N=143 (FW=1, 6*8 dots font) N=139 (FW=0, 5*8 dots font) By using this instruction, the efficiency of the application board area can be raised. SHL: Common scan direction select SHL= 0 : COM scan direction is normal, from COM 0 ->COM N SHL= 1 : COM scan direction is reverse direction, COM N ->COM 0 N=7 (NH=0, N=0:1line) N=15 (NH=0, N=1:2line) N=23 (NH=1, N=0:3line) 63

64 (15) Display Shift Control Set (Extended Function Set RE=1) RW1072-0A-001 Instruction A0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display Shift Control Set DS3 DS2 DS1 DS3~DS1: Display Shift per Line Enable This instruction select shifted to be according to each line mode in display shift right/left instruction. DS3~DS1 indicate each line to be shifted and each shift is performed individually in each line. Enable bit Enable common signals during shift Description DS1 COM 0~COM 7 The part of display line that corresponds DS2 COM 8~COM 15 to enable common signal can be shifted. DS3 COM 16~COM 23 (16) Cursor Blink and Display Reverse Set (Extended Function Set RE=1) Instruction A0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Cursor Blink and Display Reverse Set REV B/W REV: Display reverse When REV= 1 : Display reverse enable, all the display white dots become black and black dots become white. When REV= 0 : Display reverse disable. B/W: Underscore cursor blinking enable bit When B/W= 1 : underscore cursor blinking at the cursor position is set. When B/W= 0 : underscore cursor blinking disable. 64

65 (17) Select LCD Bias (Extended Function Set RE=1) Instruction A0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Select LCD Bias BS1 BS0 Select LCD bias ratio of the voltage required for driving the LCD. BS1 BS0 LCD bias 0 0 1/ / / /7 (18) Power Control Set (Extended Function Set RE=1) Instruction A0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Power Control Set VB VR VF Analog circuit booster, regulator, follower on/off control VB=1: capacitor type booster on (turn on voltage) VB=0: capacitor type booster off VR=1: internal regulator on (turn on voltage) VR=0: internal regulator off VF=1: internal follower on (turn on V1~V4 voltage) VF=0: internal follower off 65

66 (19) Extended Function Set and Display Set Instruction A0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Extended Function Set and Display Set IF N NH GM RE (1) IF: Interface Data Length Set When IF= 0, it means 4-bit bus mode with MPU When IF= 1, it means 8-bit bus mode with MPU Hence, IF is a signal to select 8-bit or 4-bit bus mode. In 4-bit bus mode, it is required to transfer 4-bit data twice. N, NH: Display Line Mode S e t N NH Display Line Mode line Display line Display line Display GM: Graphic Mode Set: Full graphic mode is available in RW1072 by setting GM register. When GM=0, 16 user-defined characters of CGRAM can be displayed by writing 00H ~ 0FH to DDRAM. When GM=1, 80 user-defined characters of CGRAM can be displayed by writing B0H ~ FFH to DDRAM RE: Extended Instruction Table Registers Enable Bit When RE= 0, basic function set registers can be accessed. When RE = 1, extended function set registers can be accessed. At this instruction, RE must be High. 66

67 (20) Select Regulator Resistor (Extended Function Set RE=1) Instruction A0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Select Regulator Resistor R2 R1 R0 Select resistance ratio of the internal resistor used in the internal voltage regulator. Note: - :don t care R2 R1 R0 1+(Rb/Ra) (Default) (21) Select Electronic Volume Register (Extended Function Set RE=1) Instruction A0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Select Electronic Volume Register EV5 EV4 EV3 EV2 EV1 E This instruction contents of reference voltage register. Note: - :don t care EV5 EV4 EV3 EV2 EV1 E Reference voltage parameter (α) : : : : : : : (Default) : : : : : : :

68 (22) Set Data Length for 3-SPI (Extended Function Set RE=1) Instruction A0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Set Data Length for 3-SPI SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 In 3-line SPI mode, set data length command indicates the length of data which, are going to be received by RW1072. User should set data length before display data sent. The table below shows how SD bits set the data length. Table 10. Set data length according to SD bits SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 Function Followed by 1 data write Followed by 2 data write Followed by 3 data write Followed by 4 data write : : : : : : : : Followed by 256 data write 68

69 (23) Frame Frequency Adjustment (Extended Function Set RE=1) Instruction A0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Frame Frequency Adjustment DF3 DF2 DF1 DF0 DFR3~DFR0: Frame Frequency adjustment from 0000 (slow) ~ 1111 (fast) Note: - :don t care Frame Frequency adjustment table: (+/- 15%) 5*8 Dots Font 6*8 Dots Font DFR3 DFR2 DFR1 DFR0 1/10 Duty (1-line) 1/18 Duty (2-line) 1/26 Duty (3-line) 1/10 Duty (1-line) 1/18 Duty (2-line) 1/26 Duty (3-line) (default) 104(default) 111(default) 78(default) 87(default) 93(default)

70 (24) Double Frame Frequency (Extended Function Set RE=1) RW1072-0A-001 Instruction A0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Frame Frequency Adjustment FRR*2 FRR*2=1: frame frequency *2 FRR*2=0: frame frequency normal Note: - :don t care Frame Frequency *2 adjustment table: (+/- 15%) 5*8 Dots Font 6*8 Dots Font DFR3 DFR2 DFR1 DFR0 1/10 Duty (1-line) 1/18 Duty (2-line) 1/26 Duty (3-line) 1/10 Duty (1-line) 1/18 Duty (2-line) 1/26 Duty (3-line) default) 208default) 222(default) 156(default) 174(default) 186(default) (25) Set CGRAM Address (Extended Function Set RE=1) Instruction A0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Set CGRAM Address A6 A5 A4 A3 A2 A1 A0 Set initial address for each user defined character in CGRAM to AC6 ~ AC0, however, C3~C0 are controlled by internal counter automatically. After write or read operation, the 8-bit CGRAM address ( A 6 ~ A 0 ) is automatically increased/decreased by 1, according to the entry mode. This instruction makes CGRAM data available from MPU. 70

71 LCD Initialization Setup Note: After RW1072 is reset, the voltage level of the LCD driving output pins SEG and COM is 8-bit Interface mode: 71

72 4-bit Interface mode: RW1072-0A

73 SPI and IIC Interface mode: RW1072-0A

74 ABSOLUTE MAXIMUM RATINGS In accordance with the Absolute Maximum Rating System; see notes 1 and 2. Parameter Symbol Conditions Unit Power Supply Voltage -0.3 ~ 5.0 V Power supply voltage ( standard) ~ 4.0 V Power supply voltage ( standard), -0.3 ~ 18.0 V Power supply voltage ( standard) V1, V2, V3, V4 to -0.3 V Operating temperature TOPR 40 to +85 C Storage temperature Bare chip TSTR 55 to +125 C Notes 1. Stresses above those listed under Limiting Values may cause permanent damage to the device. 2. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V SS unless otherwise noted. 3. Insure that the voltage levels of V1, V2, V3, and V4 are always such that V1 V2 V3 V4 74

75 DC CHARACTERISTICS Unless otherwise specified, = 0 V, = 3.0 V ± 10%, Ta = 40 to 85 C Rating Item Symbol Condition Min. Typ. Max. Units Applicable Pin Operating Voltage (1) For Digital Circuit Power V *1 Operating Voltage (2) 2 For Analog Circuit Power V High-level Input Voltage VIHC 0.7 x V *2 Low-level Input Voltage VILC 0.3 x V *2 High-level Output Voltage VOHC 0.7 x V *3 Low-level Output Voltage VOLC 0.3 x V *3 Input leakage current ILI VIN = or μa *3 Output leakage current ILO VIN = or μa *4 Liquid Crystal Driver ON Resistance RON Ta = 25 C (Relative To ) = 13.0 V = 8.0 V KΩ SEGn COMn *5 Oscillator Frequency Internal Oscillator External Input Frame frequency fosc 760 khz *6 fcl Ta = 25 C 760 khz OSC fframe 130 Hz *6 Rating Item Symbol Condition Units Applicable Pin Min. Typ. Max. Input voltage (Relative To ) V Internal Power Input voltage 2 (Relative To 2) V 2 Supply Step-up output voltage Circuit (Relative To ) V Supply Regulator output voltage Circuit (Relative To ) V Base voltage VRS References for items market with* Ta = 25 C V VRS -0.05%/ C *1 While a broad range of operating voltages is guaranteed, performance cannot be guaranteed if there are sudden fluctuations to the voltage while the MPU is being accessed. *2 The A0, D0 to D7,E, RW, CS1B, C86, PSB, RSTP terminals. *3 The D0 to D7 terminals. *4 Applies when the D0 to D5, D6, D7 terminals are in a high impedance state. *5 These are the resistance values for when a 0.1 V voltage is applied between the output terminal SEGn or COMn and the various power supply terminals (V1, V2, V3, and V4). These are specified for the operating voltage range. RON = 0.1 V /ΔI (Where ΔI is the current that flows when 0.1 V is applied while the power supply is ON.) *6 The relationship between the oscillator frequency and the frame rate frequency. 75

76 Dynamic Consumption Current During Display, with the Internal Power Supply OFF Current consumed by internal digital circuit current (Ta = 25 C) Test pattern Symbol Condition Rating Min. Typ. Max. Units Notes I =1.9V, μa *1 Power Down mode I =3.0V, μa *1 I =3.6V μa *1 During Display, with the Internal Power Supply ON Current consumed by internal digital/analog circuit current =2=3.0V (Ta = 25 C) Test pattern Symbol Condition Rating Min. Typ. Max. Units Notes DC Set-up 2X I μa DC Set-up 3X I μa DC Set-up 4X I Power Control Set: VB=1.VR=0,VF=0, LCD Bias Set: 1/ μa DC Set-up 5X I μa DC Set-up 6X I μa Note to the DC characteristics 1. Power down mode. During power down all static currents are switched off. 76

77 Timing CHARACTERISTICS 8 bit and 4 bit 6800 interface ( = 3.3 V, Ta = 25 C) Item Signal Symbol Condition Rating Min. Max. Units Address hold time tah6 0 Address setup time A0 taw6 0 System cycle time tcyc6 240 Enable L pulse width (WRITE) tewlw 80 E Enable H pulse width (WRITE) tewhw 80 Enable L pulse width (READ) tewlr 80 ns E Enable H pulse width (READ) tewhr 140 WRITE Data setup time tds6 40 WRITE Address hold time tdh6 0 D0 to D7 READ access time tacc6 CL = 100 pf 70 READ Output disable time toh6 CL = 100 pf

78 Address hold time Item Signal Symbol Condition RW1072-0A-001 ( = 2.7V, Ta =25 C) Rating Units Min. Max. tah6 0 Address setup time A0 taw6 0 System cycle time tcyc6 400 Enable L pulse width (WRITE) tewlw 220 E Enable H pulse width (WRITE) tewhw 180 Enable L pulse width (READ) tewlr 220 E Enable H pulse width (READ) tewhr 180 WRITE Data setup time tds6 40 WRITE Address hold time tdh6 0 D0 to D7 READ access time tacc6 CL = 100 pf 140 READ Output disable time toh6 CL = 100 pf Address hold time Item Signal Symbol Condition ns ( =1.8V, Ta =25 C) Rating Units Min. Max. tah6 0 Address setup time A0 taw6 0 System cycle time tcyc6 640 Enable L pulse width (WRITE) tewlw 360 E Enable H pulse width (WRITE) tewhw 280 Enable L pulse width (READ) tewlr 360 E Enable H pulse width (READ) tewhr 280 WRITE Data setup time tds6 80 WRITE Address hold time tdh6 0 D0 to D7 READ access time tacc6 CL = 100 pf 240 READ Output disable time toh6 CL = 100 pf *1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr +tf) (tcyc6 tewlw tewhw) for (tr + tf) (tcyc6 tewlr tewhr) are specified. *2 All timing is specified using 20% and 80% of as the reference. *3 tewlw and tewlr are specified as the overlap between CS1B being L and E. ns 78

79 The Serial Interface (3-SPI and 4-SPI) ( = 3.3V, Ta =25 C) Rating Item Signal Symbol Condition Min. Max. Serial Clock Period Tscyc 50 SCL H pulse width SCL Tshw 25 SCL L pulse width TSLW 25 Address setup time TSAS 20 A0 Address hold time Tsah 10 Data setup time Tsds 20 SI Data hold time TSDH 10 CS-SCL time Tcss 20 CS CS-SCL time Tcsh 40 Units ns 79

80 ( =2.7V, Ta =25 C) Item Signal Symbol Condition Rating Min. Max. Units Serial Clock Period Tscyc 100 SCL H pulse width SCL TSHW 50 SCL L pulse width TSLW 50 Address setup time TSAS 30 A0 Address hold time TSAH 20 Ns Data setup time TSDS 30 SI Data hold time TSDH 20 CS-SCL time TCSS 30 CS CS-SCL time TCSH 60 ( = 1.8V, Ta = 25 C) Rating Item Signal Symbol Condition Units Min. Max. Serial Clock Period TSCYC 200 SCL H pulse width SCL TSHW 80 SCL L pulse width TSLW 80 Address setup time TSAS 60 A0 Address hold time TSAH 30 Data setup time TSDS 60 SI Data hold time TSDH 30 CS-SCL time TCSS 40 CS CS-SCL time TCSH 100 *1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less. *2 All timing is specified using 20% and 80% of as the standard. ns 80

81 IIC Interface (Ta =25 C) Item Signal Symbol Condition =1.8 V to =2.7 V =2.7 V to =3.6 V Units Min Max Min Max SCL Frequency fsclk DC 400 DC 400 KHz SCL Clock Low Period SCL tlow us SCL Clock High Period thigh us Data Setup Time tsu;dat ns SDA Data Hold Time thu;dat us SCL,SDA Rise Time SCL,SD tr Cb Cb 300 SCL,SDA Fall Time A tf Cb Cb 300 Capacitive Load represent by each bus line Setup time for a repeated START Condition Start Condition Hold Time SDA Cb pf tsu;sta us thu;sta us Setup Time for STOP tsu;sto us Bus Free Time between a STOP and START Condition SCL tbu us ns 81

82 RESET TIMING ( = 3.3V, Ta =25 C) Rating Item Signal Symbol Condition Min. Typ. Max. Units Reset time tr 1 us Reset L pulse width RESB trw 1 us ( = 2.7V, Ta = 25 C) Rating Item Signal Symbol Condition Min. Typ. Max. Units Reset time tr 1.5 us Reset L pulse width RESB trw 1.5 us ( = 1.8V, Ta = 25 C) Rating Item Signal Symbol Condition Min. Typ. Max. Units Reset time tr 2.0 us Reset L pulse width RESB trw 2.0 us 82

83 THE MPU INTERFACE (REFERENCE EXAMPLES) The RW1072 can be connected to 6800 Series MPUs. Moreover, using the serial interface it is possible to operate the RW1072 chip with fewer signal lines. The display area can be enlarged by using multiple RW1072 chips. When this is done, the chip select signal can be used to select the individual Ics to access. (1) 6800 series MPUs (PSB= H,C86= H ) 8-bit data bus (2) 6800 series MPUs (PSB= H,C86= H ) 4-bit data bus 83

84 (3) 4-SPI Interface (PSB= L, C86= H ) (4) 3-SPI Interface (PSB= L, C86= H ) (5) IIC Interface (PSB= L, C86= L ) 84

85 RW1072 Revision History Version Date Description /6/16 First Edition /5/25 Add stander circuit for all duty Add adjustment frame frequency value for all duty Update Instruction Table Update Initialization setup for all interface Update dynamic consumption current Update Reset circuit Add write command and write data execution time Modify ARRANGEMENT 85

86 86