32 CH COMMON DRIVER FOR DOT MATRIX LCD

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Victor Hampton
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1 _ INTRODUCTION 64 QFP is a LCD driver LSI which is fabricated by low power COS high voltage process technology. This device consists of timing generator circuit, 32 bit shift register and 32 bit driver. FUNCTION Dot matrix LCD common driver with 32 channel output Input /Output signal - Input: bias voltage (,,,, ) - Output; 32 channel waveform for LCD driving and segment driver control pulse. FEATURE Power supply voltage: +V±10% Supply voltage for display: 0~-.V() Applicable LCD duty; selectable 7 kinds (1/8, 1/12, 1/16, 1/24, 1/32, 1/48, 1/64) Interface COON Other SEGENT KS0106 Oscillator frequency can be set by adjusting external capacitor and resistor 64 QFP or bare chip available. BLOCK DIAGRA C 1 C 2 C 32 C bit LCD driver DL 32 bit shift register DR OSC circuit f OSC Timing generator circuit FR K1 K2 /S TEST F 0 F 1 DD 0 DD 1 DD 2 Fig 1. Functional block diagram

2 PIN CONFIGURATION C 19 C 20 C 21 C 22 C 23 C 24 C 2 C 26 C 27 C 28 C 29 C 30 C 31 C 32 C NC C DR C C NC C 4 26 C 13 2 NC C 12 C 11 C 10 C 9 C PIN DESCRIPTION PIN(No.) INPUT/OUTPUT NAE DESCRIPTION INTERFACE (24) Operating Voltage For Internal logic circuit (+V ¾10%) (9) Power GND (0V) Power (31) Negative Supply For LCD driver circuit Supply Voltage Fig QFP Top View,, Oscillator Generate Oscillation Frequency (refer to note 1) (1-17) C 1-C 32 (36-60, 1-7) Output Common Output Common signal output for LCD driving (refer to note 4) LCD DL, DR(8, 29) Input/Output Data Input or Output Data input/output pin of internal shift register Other (26) Input/Output Alternated Signal For LCD Driver Alternating signal input pin for LCD driving KS0106 aster mode Output Slave mode Input C 7 C 6 C C 4 C 3 C 2 C 1 DL 10 F 0 11 F 1 12 DD 0 13 DD 1 DD TEST FR K1 K2 /S

3 PIN DESCRIPTION(continued) PIN(NO.) INPUT/OUTPUT NAE DESCRIPTION INTERFACE, (32, 33) Input Bias Voltage Bias supply voltage terminals to drive the LCD Power, (34, 3) (28) Input/Output Shift Clock Data Shift Clock KS0106 FR (23) Ouput Frame Signal Synchronous frame signal KS0106 (19) Input Data Interface Selection of the shift direction (slave mode) (master mode) K1, K2 Output Operating Clock Clock for KS0106 KS0106 (22, 21) TEST (18) Input - Test pin (This pin must be connected ) DD 0-DD 2 (12-) Input Select Display Duty Can select the duty ratio according to combination of DD 0-DD 2 (refer to note 2) or F 0-F 1 (10, 11) Input Select Frequency Can select the relationship between oscillator frequency and frame frequency. (refer to note 3) /S(20) Input Select aster or Slave Select level Non-select level - - aster mode Slave mode DL DR out in in out Output Input Shift Direction DL çdr DL ædr aster mode: connect - Operated the oscillator and timing generation circuit. Slave mode: connected - not operated the oscrillator and timing generation circuit. - Unnecessary pins (F 0, F 1, DD 0-DD 2, TEST) Connect for prevent floating current. or or or AXIU ABSOLUTE LIIT (Ta=2 É) Characteristics Symbol Value Unit Test pin Operating Voltage -0.3~+7.0 V,, Driver Supply Voltage V LCD *1-13.~+0.3 Input Voltage V IN1-0.3~+0.3 DL, DR,, F O, F I, /S, DD 0-DD 2 V IN2*2-0.3~+0.3,,, Operating Temperature T OPR -20~+7 µa - Storage Temperature T STG -~+12 - * Voltage greater than above may damage to the circuit. *1 : connect a protection resistor (20Ω±%) *2 connect a protection resistor (47Ω±10%)

4 ELECTRICAL CHARACTERISTICS DC Characteristics (=+V±10%, =0V, Ta=2 C) Characteristic Symbol condition in Typ ax Unit Applicable Pin Operating voltage V, Oscillator frequency f f=68kω±2% Cf=10pF±% khz,, Input Voltage High V IH , F 0,F 1,, DD 0-DD 2,, /S Low V IL V, DR, DL, TEST Output voltage High V OH I OH=-400 µs DL, DR,, FR Low V OL I OL=400 µs , K1, K2 On Resistance (V-C) R ON =-V+10% kω - Load Current10 µs Input Leakage Current I LKG1 V IN=~ -1-1 µs, F 0,F 1,, DD 0-DD 2,, /S, DR, DL, TEST I LKG2 V IN=~ - -,,, Power aster P D1 RC Oscillation, 430kHz, 1/32 duty mw, Dissipation Rf=68kΩ±2%, Cf=10pF±% Slave P D2 Frame 70Hz, 1/32 duty Note 1: Oscillation frequency (fosc) Note 4: R f C f D Output level H H L L H L Note 2: Selects frequency Duty Duty ratio 1/8 1/12 1/16 1/24 1/32 1/48 1/64 DD0 L L L H H H H DD1 L H H L L H H DD2 L H L H L H L ode aster mode aster/slave mode Note 3: Selects frequency Condition Oscillator Frame signal K1, K2 F 0 F 1 frequency (KHz) frequency (Hz) frequency (Hz) frequency (KHz) L L H L L H H H `

5 APPLICATION CIRCUIT 1/64 Duty DD 0 DD 1 DD 2 F 0 F 1 R f C f /S TEST DL DR FR (aster) C 1 C 32 to LCD Panel K 1 K 2 VSS TO LCD DD 0 DD 1 DD 2 F 0 F 1 /S TEST DL DR FR K 1 K 2 (aster) C 33 C 64 to KS0106

6 APPLICATION CIRCUIT (continued) V 3 V 4 CS 3 CS 2 R/W D/I E RST DB 0-DB 7 GND CS 1 V 3 V 4 K2 K 1 FR S 1 -S 0 D/I R/W E RST DB 0 -DB 7 GND CS 1 VSS CS 2 CS 3 V 3 V 4 K2 K 1 FR S 1 -S 0 R/W D/I E CS 1 CS 2 CS 3 S 1 -S 0 KS0106 GND DB 0-DB 7 RST K2 K 1 FR R/W D/I E RST DB 0 -DB 7 PU CS 1 CS 2 CS 3 LCD PANEL KS0106 F0 F1 TEST /S VSS VSS DD 0 DD 1 DD 2 C 1 -C 32 FR K1 K2 R f C f V 4 V 3 (20 Ø) KS 010 6

7 PAD DIAGRA CHIP SIZE : PAD SIZE : UNIT : ìm Y (0,0) X

8 PAD LOCATION PAD PAD COORDINATE PAD PAD COORDINATE NUBER NAE X Y NUBER NAE X Y 1 C V C V C V C C C C C C C C DL C VSS C F C F C DD C DD C DD C C C C TEST C C /S C K C K C FR C C NC * * 7 C C NC * * 9 C C DR NC * * 31 VEE V UNIT (µm)

64CH COMMON DRIVER FOR DOT MATRIX LCD INTRODUCTION FEATURES 100 QFP-1420C

64CH COMMON DRIVER FOR DOT MATRIX LCD INTRODUCTION FEATURES 100 QFP-1420C INTRODUCTION The is an LCD driver LSI with 64 channel outputs for dot matrix liquid crystal graphic display systems. This device provides 64 shift registers and 64 output drivers. It generates the timing