16COM x 100SEG 1/16 Duty BITMAP LCD Driver. NJU6573! FEATURES LCD driving circuit : 16-common and 100-segment

Transcription

1 16COM x 100SEG 1/16 Duty BITMAP LCD Driver! GENERAL DESCRIPTION PACKAGE OUTLINE The is a 16-common x 100-segment bitmap LCD driver to display graphics or characters. It incorporates 16 common driver circuits and 100 segment driver circuits. The can display a 16 x 100 dots graphic or 2-line by 20-character (5 x 7 dots per character). In addition, the s useful functions meet a wide range of applications.! FEATURES LCD driving circuit : 16-common and 100-segment Bias Ratio : 1/5 bias Serial Data Transfer : Shift clock max. 2MHz Oscillator : CR oscillation with external resistor and capacitor, or external oscillation signal input. Programmable Contrast Control:16-steps Electrical Variable Resister (EVR) Voltage Tripler and bleeder resistance on-chip. Operating Voltage : V DD =2.4~3.6V C-MOS Technology : Substrate : P Package : LQFP mm x 20.0mm t=1.7mm(max) 0.5mm pitch -1-

2 - 2 -! BLOCK DIAGRAM COM0 COM0 COM0 COM0~COM15 COM15 COM15 COM15 SEG0 SEG0 SEG0 SEG0~SEG SEG SEG SEG SHIFT REGISTER(105) OSCILLATOR CIRCUIT SC SC SC LOGIC CIRCUIT COM DRIVER CIRCUIT(16) VDC DC DC DCOUT OUT OUT OUT VCI VCI VCI VCI OSC OSC OSC OSC LATCH BLOCK(100x16) LINE SELECT SEG DRIVER(100) COM CONTRORER IF VOLTAGE CONVERTER REGULATORE CVON CVON CVON CVON CVOFF CVOFF CVOFF CVOFF SVON SVON SVON SVON SVOFF SVOFF SVOFF SVOFF DISPLAY DATA LCD DRIVER VOLTAGE CIRCUIT SVON SVON SVON SVON SVOFF SVOFF SVOFF SVOFF CVON CVON CVON CVON CVOFF CVOFF CVOFF CVOFF SERIAL DATA CLOCK Chip Chip Chip Chip C2P C2P C2P C2P C2N C2N C2N C2N DD DD DD SS SS SS INH INH INH INHb C1P C1P C1P C1P C1N C1N C1N C1N VREG REG REG REG VDCIN DCIN DCIN DCIN TESTIN2 TESTIN2 TESTIN2 TESTIN2 VREF VREF VREF VREF VREG VREG VREG VREG RST RST RST RSTb BOOST BOOST BOOST BOOST CS CS CS SI

3 -3-! PAD LOCATION COM0 V 0 V 2 V 3 TESTOUT SI OSC INHb BOOST SEG55 SEG V 1 SEG19 SEG20 SEG92 COM15 SEG0 V 4 VDCOUT VCI TESTIN2 RSTb V DD C1P C1N C2N C2P VREF VDCIN N.C VREG TESTIN V SS COM91 COM56

4 ! TERMINAL DISCRIPTION No. Pad Name Function 136 Power Supply: (2.4V-3.6V) VCI VREG VREF Booster voltage input terminal(max:3.3v) Voltage Regulator Output Regulator base voltage input terminal for VREG output (MAX:3.3V) 139 INHb Display ON or OFF High =Display ON, Low =Display OFF, 125 VDCIN Voltage Regulator Input 126 VDCOUT Booster voltage output terminal (Internal Booster Circuit Output Terminal) Bias V SS 133 V SS GND Terminal V SS =0V C1P C1N C2P C2N Capacitor Connect Terminal for Voltage Booster 143 RSTb Reset When RSTb is Low, Latch Circuit is Reset. 142 Chip Select When is Low, Data can be read in. 140 SI Serial Data Input Terminal 141 Serial Clock Input Terminal (Max: 2MHz) OSC OSC: External Resistor and Capacitor Connect Terminal for CR Oscillation, or External Clock Input Terminal. : High =External Clock Input, Low =CR Connect, 1-16 COM0-COM15 Common Driver Outputs SEG0-SEG99 Segment Driver Outputs 135 BOOST Voltage Booster ON or OFF High =Voltage Booster ON, Low =Voltage Booster OFF, BOOST Internal Booster Internal Regulator Circuit L OFF OFF H ON ON 132 TESTIN Test Terminal (Keep TESTIN-Vss short) 134 TESTIN2 Test2 Terminal (Keep TESTIN2-Vss short) 144 TESTOUT Test Out Terminal(There is open Terminal electrically) 124 N.C. There is open Terminal electrically - 4 -

5 ! FUNCTION DESCRIPTION (1) Shift Resister 105 bits resister (2) Latch Circuit Data stored in display data register is assigned to the corresponding SEG/port. (3) Segment Driver Basing on display data, segment drivers output LCD SEG driving signal. (4) Common Driver Common drivers output LCD COM driving signal. (5) Voltage Booster with a built-in Voltage Booster. The internal voltage booster generates up to 3xVCI voltage(input:vci Terminal, Output: VDCOUT Terminal). The boost voltage VDCOUT must not exceed 10.0V(VCIx3 10V), otherwise the voltage stress may case a permanent damage to the LSI. When using the internal LCD power supply, connect the VDCOUT and the VDCIN. The VREF voltage is tripled to obtain the VREG voltage.(vrefx3=vreg) -5-

6 (5) Bleeder Resistance Each LCD driving voltage (,,, ) is LCD driving high voltage input to the V 0 Terminal, generated by the E.V.R and high impedance bleeder resistance. LCD driving voltage generation circuit generates LCD driving bias voltages,,, and. V REG,,,, and terminals requires external capacitors for bias voltage stabilization for display quality. These values of capacitors should be fixed in accordance with evaluation in the application. LCD Driving Voltage vs Duty Ratio Duty Ratio 1/16 Power supply Bias 1/5 V LCD V 0 - V SS V LCD is the maximum amplitude for LCD driving voltage. V DCOUT From Voltage booster Internal V DCIN V REF Regulator V REG 0~11.25K E.V.R(16Steps) 4K 4K 4K V LCD 4K 4K Vss Vss Fig Bleeder Resistance - 6 -

7 (6) Oscillator circuit The oscillator consists of an external capacitor and an resistor. It generates clock signal for LCD driving. When use external clock, input the clock signal to OSC.( Terminal is High when use external clock) 200K OSC (f OSC =30.8kHz TYP) 100pF Fig OSC Circuit (6-1) Relation between Oscillation frequency and Frame frequency Frame frequency = fosc / 384 Set the oscillation frequency to obtain the frame frequency. -7-

8 (7) Input Data Format and Timing Data format is shown below. When the terminal goes to L at terminal H, I/F is data input. Data fetched at rising edge. In case of entering less then 105-bit data(display Data:100bit, COM select data:4bit,e.v.r set data:1bit), Malfunction. In case of entering over then 105-bit data, valid data is last 105-bit data. (7-1) 1/16Duty SI D1 D2 D3 D99 D EVR Display Data(1-100) SI D301 D302 D303 D399 D EVR Display Data( ) SI D1501 D1502 D1503 D1599 D EVR Display Data( ) COM0 select data SI D101 D102 D103 D199 D EVR Display Data( ) Display Data( ) EVR:The Bit set E.V.R or COM L : COM select data H : E.V.R. select data COM1 select data SI D201 D202 D203 D299 D EVR COM2 select data COM3 select data COM15 select data EVR set EVR set EVR set EVR set EVR set - 8 -

9 SI Before are Before are raised, data on 105 bits.(valid) raised, data on 106 bits and more. (Invalid) In case of entering over then 105-bit data (7-2) Display OFF (INHb) When INHb is "H", display is ON, and when INHb is "L", display is off. When INHb= L All segment and common terminal output Vss (7-3) Voltage Booster Circuit Select (BOOST terminal) Voltage Booster ON or OFF BOOST H L Voltage Booster Circuit ON OFF Regulator Circuit ON OFF VLCD operation supply Internal Booster Circuit using External VLCD power supply Input (7-4) Reset(RSTb) When RSTb is Low", latch circuit is reset. But, Display ON/OFF can not be reset (control). (7-5) Supply Voltage Sequence Supply voltage ON Display OFF(INHb= L ) Reset (Over 1.3msec RSTb= L ) Display Data write Display ON (INHb= H ) Fig Supply Voltage Sequence Wait time: 100msec -9-

10 (8) Instructions The incorporates E.V.R register(high). Instruction code as show below. Table. Table of Instructions Instruction Electrical Voltage Resistor Explanation When the terminal rising edge eve one bit is High, Data fetched at rising edge. In case of entering less then 2-5bit data valid. EVR set SI * * * * * C3 C2 C1 C0 1 *: Even only 5 clock can set E.V.R if the last bit is "1". *:Don t care Contrast Control instruction which adjusts the contrast of the LCD is executed when the code "1" is written into EVR and the codes of C3 to C0 are written into 2 to 5bit as shown below. The contrast of LCD can be adjusted one of 16 voltage-stages by setting this 4-bit register. See below "how to adjust the Contrast of LCD". Set the binary code "1,1,1,1" when contrast adjustment is unused. C3 C2 C1 C0 VLCD voltage (Spec) Ex.) VLCD voltage by VOUT=8.4V VOUT x VOUT x VOUT x VOUT x VOUT x VOUT x VOUT x VOUT x VOUT x VOUT x VOUT x VOUT x VOUT x VOUT x VOUT x VOUT x VLCD=VREG x 20 / ( x M) M: Contrast control resistor =

11 Input Data v.s output COM -11-

12 ! ABSOLUTE MAXIMAM RATINGS (V SS =0V, Ta=25 C) PARAMETER SYMBOL RATINGS UNIT CONDITIONS Supply Voltage 1 V DD,V REF -0.3 ~ +7.0 V Supply Voltage 2 V CI -0.3 ~ V V CI Terminal Note-4) Note-1) Note-2) Note-3) Note-4) Supply Voltage 3 V DCIN, V 0 V 1 ~V 4,V REG -0.3 ~ V Input Voltage V t -0.3 ~ V DD +0.3 V Operating Temp. Topr -40 ~ +105 C Storage Temp. Tstg -55 ~ +125 C Dissipation Power P D 1000 mw V DCIN, V 0, V 1 ~V 4,V REG Terminal INHb,,, SI, RSTb, OSC, BOOST,TESTIN,TEST2, applicable. The power dissipation is value mounted on 4 layer glass epoxy board in size 76.2mm x 114.3mm x 1.6tmm Do not exceed the absolute maximum ratings, otherwise the stress may cause a permanent damage to the IC. It is also recommended that the IC be used within the range specified in the DC electrical characteristics, or the electrical stress may cause mulfunctions and impact on the reliability. To stabilize the LSI operation, place decoupling capacitors between V DD -V SS, V CI -V SS and between V DCIN -V SS. All voltages are relative to V SS = 0V reference.the following relationship shall be maintained. V DCIN V 0 V DD >V SS, and V SS =0V When voltage booster circuit, need condition of 10V VCIx

13 ELECTRICAL CHARACTERISTICS DC characteristics (V DD =2.4 to 3.6V, V SS =0V, Ta=-40 to +105 C) PARAMETER SYMBOL Terminal CONDITIONS MIN TYP MAX UNIT Note Power Supply 1 V DD V DD V Power Supply 2 V CI V CI V 5 Power Supply 3 V DCIN V DCIN V IH1,, SI, RSTb, 0.8 V DD - V DD V Input voltage 1 OSC,BOOST V IL1 INHb, V SS V DD V Driver-on(COM) COM0- ±Id=1µA(COM Terminal) R Resistance COM COM15 V O=V 0,V SS, V 1,V kohm 7 Driver-on(SEG) SEG0- ±Id=1µA(SEG Terminal) R Resistance SEG SEG99 V O=V 0,V SS, V 2,V kohm 7,, V IN=0~V DD Input leakage RSTb, INHb, I current LI BOOST, µa I DD1 V DD V DD=V CI=3V, V REF=2.7V, f osc=30.8khz, Checker Display ON, Booster ON, Ta=25 C µa 8 Operating Current E.V.R: 1111 I CI V CI SEG/COM open V DCOUT/V DCIN connect ma I DD1 V DD f OSC=184.8kHz µa 8 I CI V CI Other condition same as I DD ma V 0 V LCD operating voltage Bleeder resistance RB=V 0/I B RB: Bleeder resistance 5 IB: Bleeder resistance Current Booster output voltage V 1 V V V 2 V REG =8.0V E.V.R: 1111 V 3 V V 4 V R B V REG V REG =8.0V E.V.R: 1111, Ta=25 C V OUT V DCOUT OSC Frequency f OSC OSC External clock Operating Frequency Operate Frame Frequency range kohm V CI=3.3V, Ta=25 C f OSC=30.8k-184.8kHz, BoosterON(COM/SEGopen) V V DCOUT between V DCIN connect V DD =3V, Ta=25 C, R OSC= 200kOhm C OSC= 100pF khz R OSC= 30kOhm Other condition same as f OSC f CP OSC External input khz Fr COM Hz 9 V REF input voltage V REF V REF V DD V Regulator output V V voltage REG V DCIN =10V, V REF=3V, V REF x V REF x V REF x REG (COM/SEG open) 3 x x 1.02 V Dropout Voltage Delta VIO V DCIN-V REG V DCIN=9V, V REF=3.6V, I O=-200µA V V DCIN Current I OUT V DCIN V DCIN=9.0V, V REF=2.7V E.V.R: 1111, INHb=0 Ta=25 C (COM/SEG open) ma V -13-

14 Note-5) When voltage booster circuit using, need condition of V DCOUT 10V Note-6) Condition of V DCIN Voltage: 10V V DCIN V REF x Note-7) Driver-On resistance (R SEG /R COM ) is measured from V 0, V SS, V 1, V 2, V 3 or V 4 terminal to each SEG/COM terminal when Id current flows through COM/SEG terminals. 3V A V DD V ss Note-8) If input voltage is outside of the spec, when operating current increase. Input level must be condition H or L. This mesurement condition is SI terminal between short. Note-9) Frame frequency vs OSC is as the show relation between oscillation frequency and Frame frequency page7. Example characteristic) Condition C=100[pF] R=from 27k[ohm] to 200k[ohm] Temperature=25[ C] The following graph is the data of example sample, so without guarantee. fosc vs Resistance (C=100pF) =3V, Ta=25 fosc [khz] Resistance [kohm]

15 AC characteristics (V DD =V 0 =2.4 to 3.6V, V SS =0V, Ta=-40 to +105 C) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Note "L" Level Clock Pulse Width t WCLL ns "H" Level Clock Pulse Width t WCLH ns Data Setup Time t DS ns Data Hold Time t DH ns Setup Time t CS ns Hold Time t CH ns "H" Level Pulse Width t WCH ns Rising Time t r ns Falling Time t f ns Input Timing t WCH t CS t WCLH t WCLL t f t r t CH t DS t DH SI Input condition when hardware reset circuit is used (Ta=-40 to +105 C) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Reset Input L Level Width t RSL f OSC =30.8kHz±18% ms f OSC =184.8kHz±18% ms Reset Rising Time t rrs ns Reset Falling Time t frs ns t frs t RSL t rrs RSTb V IH V IL -15-

16 LCD Operating Wave Form COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM15 SEG COM0 COM COM2 COM3 SEG0 SEG1-16 -

17 Input and Output Circuit IN IN RSTb,, SI, OSC,, INHb, TESTIN, BOOST, TESTIN2 Vss OUT Vss SEG0~SEG99, COM0~COM15-17-

18 APPLICATION CIRCUIT C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 VCI VCI VREF C1P C1N C2P C2N VDCOUT VDCIN VREG (VCI 3 10V) (VREF 3 (VDCIN-0.1V) ) BOOST TESTIN, TESTIN2 R1 C13 OSC CPU RSTb INHb SI Reference value R1 200k C13 100pF C4,5,6, F C1-C3,C8-C F

19 -19- Reference value C F C1,C3-C F VCI VREF C1P C1N C2P C2N VDCOUT VDCIN VREG BOOST TESTIN, TESTIN2 OSC RSTb INHb SI CPU CPU CPU CPU C3 C4 C5 C6 C7 VREG 10V C1 C2

20 C1 VCI C2 VREF C1P C1N C2P C2N VDCOUT C3 VDCIN 10V C4 C5 C6 C7 C8 C9 VDCIN VREG BOOST TESTIN, TESTIN2 OSC CPU RSTb INHb SI Reference value C3, F C1,C2-C F [CAUTION] The specifications on this databook are only given for information, without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights