KS0107B 64CH COMMON DRIVER FOR DOT MATRIX LCD INTRODUCTION

Transcription

1 INTRODUCTION The is a LCD driver LSI with 64 channel output for dot matrix liquid crystal graphic display system. This device provides 64 shift register and 64 output driver. It generates the timing signal to control the KS0108B segment driver. The is fabricated by low power COS high voltage process technology and compose of the liquid crystal display system in combination with the KS0108B segment driver. 100 QFP-1420 FEATURES Dot matrix LCD common driver with 64 channel output. 64 bits shift register ot internal LCD driver circuit. Internal timing generator circuit for dynamic display. Selectable master/slave mode. Applicable LCD duty: 1/48, 1/64,1/96,1/128 Power supply voltage: + 5V ±10% LCD driving voltage: 8V~17V(-) Interface COON Driver SEGENT controller Other KS0108B PU High voltage COS process. 100QFP and bare chip available.

2 BLOCK DIAGRA C1C2C3 C62 C63 C64 L L L L 64 bits LCD driver R R R R 64 bits bidirection shift register DIO1 P SHL Data shift direction ƒ Phase selection control circuit DIO2 C R CR OSC Timing generator cirecuit FR V SS DS 1 DS 2 S FS Fig. 1. Functional block diagram

3 PIN CONFIGURATION C42 C41 C40 C39 C38 C37 C36 C35 C34 C33 C32 C31 C30 C29 C28 C27 C26 C25 C24 C C 22 C 21 C 20 C 19 C 18 C 17 C 16 C 15 C 14 C 13 C 12 C 11 C 10 C 9 C 8 C 7 C 6 C 5 C 4 C 3 C 2 C 1 L L L L DIO1 FS C 43 C 44 C 45 C 46 C 47 C 48 C 49 C 50 C 51 C 52 C 53 C 54 C 55 C 56 C 57 C 58 C 59 C 60 C 61 C 62 C 63 C 64 R R R V OR DIO2 P FR S V SS SHL CR R C DS2 DS1 Fig QFP Top View

4 PIN DESCRIPTION PIN(NO) SYBOL INPUT/OUTPUT DESCRIPTION ,58 V SS Power For internal logic circuit (+5V±10%) GND (0V) For LCD driver circuit 27, 54 24, 57 25, 56 26, 55 L, R L, R L, R L, R Power Bias supply voltage terminals to drive LCD. Select Level L(R), L(R) Non-Select Level L(R), L(R) L and R is connected by the same voltage. 42 S Input Selection of master/slave mode i) aster mode (S=1) DIO1, DIO2, and is output state. ii) Slave mode (S=0) SHL=1 DIO1 is input state(dio2 is output state) SHL=0 DIO2 is input state(dio1 is output state) and is input state. 39 SHL Input Selction of data shift direction. SHL H L Data shift direction DIO1 C1... C64 DIO2 DIO2 C64... C1 DIO1 49 P Input Selection of shift clock () phase. P H L shift clock() phase data shift at the rising edge of data shift at the falling edge of 30 FS Input Selection of oscillation frequency. i) aster mode When the freme frequency is 70Hz, the oscillation frequency should be fosc=430khz at FS=1 () fosc=215khz at FS=0 (V SS) ii) Slave mode Connect to DS1, DS2 Input Selectiom of display duty. i) aster mode DS1 DS2 Duty L L 1/48 L H 1/64 H L 1/96 H H 1/128 ii) Slave mode : Connect to.

5 PIN DESCRIPTION (continued) PIN(NO) SYBOL INPUT/OUTPUT DESCRIPTION C R RC Oscillator i) aster mode 37 CR KS0107 KS0107 R CR C R CR C R f C f ii) Slave mode open external clock open R CR C open Oopen PEN 44, 43, Output Operating clock output for the KS0108B i) aster mod Connection to and of the KS0108B ii) Slave mode Open 46 FR Output Synchronous frame signal. i) aster mode Connection to FR of the KS0108B ii) Slave mode Open 47 Input/Output Alternating signal input for LCD driving. i) aster mode: output state Connection to of the KS0108B ii) Slave mode: input state Connection to the controller 52 Input/Output Data shift clock i) aster mode: output state Connection to CL of the KS0108B ii) Slave mode: input state Connection to shift clock terminal of the controller. 29 DIO1 Input/Output Data input/output pin of internal shift register. 50 DIO2 S SHL DIO1 DIO2 H H Output Output L Output Output L H Input Output L Output Input 22~1 100~59 C1~C64 Output Common signal output for LCD driving. DATA OUT L L V 1 L H V 4 H L V 5 H H V 0 34,36,38,41 45,48,51,53 No Connection

6 AXIU ABSOLUTE LIIT Characteristic Symbol Value Unit Note Operating Voltage -0.3~+7.0 V *1 Supply Voltage -19.0~+0.3 V *4 Driver Supply Voltage V B -0.3~+0.3 V *1,2 V LCD -0.3~+0.3 V *3,4 Operating Temperature T OPR -30~+85 C - Storage Temperature T STG -55~+125 C - *1. Based on V SS=0V *2. Applies to input terminals and I/O terminals at high impedance. (Except L(R), L(R), L(R) and L(R)) *3. Applies to L(R), L(R), L(R) and L(R). *4. Voltgae level: L=R L=R L=R L=R. ELECTRICAL CHARACTERISTICS DC Characteristics (=+5V ± 10%, V SS=0V,l - l =8~17V, T a=-30 ~ +85 C) Characteristic Symbol condition in Typ ax Unit Note Input High V IH V *1 Voltage Low V IL V SS Output Hogh V OH I OH=-0.4mA V *2 Voltage Low V OL I OL=0.4mA Input Leakage Current I LKG V IN=~V SS µa *1 OSC Frequency f OSC Rf=47KΩ±2% KHz Cf=20pf±5% On Resistance R ON -=17V KΩ (Vdiv-Ci) Load current ±150µA Operating Current I DD1 aster mode ma *3 1/128 Duty I DD2 Slave mode µa *4 1/128 Duty Supply Current I EE aster mode *5 1/128 Duty Operating f op1 aster mode KHz External clock Frequency f op2 Slave mode *1. Applies to input terminals FS, DS1, DS2, CR, SHL, S and P and I/O terminals DIO1, DIO2, and in the input state. *2. Applies to output terminals, and FR and I/O terminals DIO1, DIO2, and in the output state. *3. This value is specified about current flowing through V SS. Internal oscillation circuit: Rf=47kΩ, Cf=20pF Each terminals of DS1, DS2, FS, SHL and S is connected to and out is no load. *4. This value is specified about current flowing through V SS. Each terminals is DS1, DS2, FS, SHL, P and CR is connected to, S is connected to V SS and,, DIO1 is external clock. *5. This value is specified about current flowing through. Don t connect to V LCD (~).

7 AC Charcteristics (VDD=5V±10%, Ta=-30 C~+85 C) (1)aster mode (S=, P=, Cf=20pF, Rf=47KΩ) t WLC tsu t WHC DIO1 ( SHL = ) t DH t su t WHC DIO2 ( SHL = V SS ) t D DIO2 ( SHL = ) t D DIO1 ( SHL = V SS ) t DF FR t D t D t F t R t WH1 t WL1 t DI2 t D21 t WH2 t F t R Characteristic Symbol in Typ ax Unit Data Setup Time t SU Data Hold Time t DH Data Delay Time t D FR Delay Time t DF -2-2 µs Delay Time t D -2-2 Low Level Width t WLC High Level Width t WHC Low Level Width t WL Low Level Width t WL High Level Width t WH High Level Width t WH ns - Phase Difference t D Phase Difference t D , Rise/Fall Time t R/t F

8 (2) Slave mode (S=V SS) t F t R twlc1 ( PLK2 = V SS ) t WHC t SU t WHC2 t WLC ( PLK2 = ) t R t F t D t DH hcl DIO1 ( SHL = ) DIO2 ( SHL = V SS ) Input Data t H DIO1 ( SHL = ) DIO2 ( SHL = V SS ) Output Data Characteristics Symbol in Typ ax Unit Note Low Level Width t WLC ns P=V SS High Level Width t WHC ns P=V SS Low Level Width t WLC ns P= High Level Width t WHL ns P= Data Setup Time t SU ns Data Hold Time t DH ns Data Delay Time t D ns *1 Output Data Hold Time t H ns Rise/Fall Time t R/t F ns *1; Connect load CL=30pF OUTPUT 30pF

9 FUTIONAL DESCRIPTION 1.RC Oscillator The RC Oscillator generates,,fr, of the and, of the KS0108B by the oscillation resister R and capacitor C. When selecting the master/slave, oscillation circuit is as following: 1) aster ode R CR C R CR C R f C f open open external clock 2) Slave ode R CR C open open Open 2. Timing Genertion Circuit It generates,, FR,, and by the frequency from oscillation circuit. 1) Selection of aster/slave (/S) When /S, is H, it generates,, FR,, and internally. When /S is L, it operates by receiving, from master device. 2) Frequency Selection (FS) To adjust FR by 70Hz, the oscillation frequency should be as following: FS H L Oscillation Frequency f OSC=430KHz f OSC=215Khz In the slave mode, it is connected to. 3) Duty Selection (DS1, DS2) It provides various duty selection according to DS1, DS2. DS1 DS2 DUTY L L 1/48 H 1/64 H L 1/96 H 1/128

10 3. Data Shift & Phase Select Control 1) Phase Selection It is a circuit to shift data on synchronization or rising edge or falling edge of the according to P. P H L Phase Selection Data shift on rising edge of Data shift on falling edge of 2) Data Shift Direction Selection When /S is connected to, DIO1 and DIO2 terminal is only output. When /S is connected to V SS, it depends on the SHL. S SHL DIO1 DIO2 Direction of Data H H Output Output C1 C64 L Output Output C64 C1 L H Input Output DIO1 C1 C64 DIO2 L Output Input DIO2 C64 C1 DIO1

11 TIING DIAGRA (1) 1/48 duty timing (aster mode) Condition: DS1=L, DS=L, SHL=H(L), P=H C FR DIO1 ( DIO2 ) V 0 V 0 C1 ( C48 ) V 1 V 5 V 1 C2 ( C47 ) C47 ( C2 ) C48 ( C1 ) DIO2 ( DIO1 ) - relation of ƒ DIO1 ( DIO2 ) DIO1 ( DIO2 )

12 (2) 1/128 duty timing (aster mode) - Condition: DS1=H, DS2=H, SHL=H(L), P=H C FR DIO1 ( DIO2 ) C1 ( C48 ) V 0 V 5 V 1 V 0 C2 ( C47 ) C47 ( C2 ) C48 ( C1 ) DIO2 ( DIO1 ) - relation of ƒ DIO1 ( DIO2 ) DIO1 ( DIO2 )

13 (3) 1/48 duty timing (Slave mode) - Condition: P=L, SHL=H(L) DIO1 ( DIO2 ) C1 ( C48 ) C2 ( C47 ) C47 ( C2 ) C48 ( C1 ) DIO2 ( DIO1 )

14 (4) Power driver circuit L/R R1 L/R R1 V2 R2 V3 KS0108B R1 L/R R1 L/R VR relation of duty & bias DUTY BIAS Rdiv 1/48 1/8 R2=4R1 1/64 1/9 R2=5R1 1/96 1/11 R2=7R1 1/128 1/12 R2=8R1 *When duty factor is 1/48, the value of R1 & R2 should satisfy. R1/(4R1+R2)=1/8 R1=3KΩ, R2=12KΩ

15 APPLICATION CIRCUIT -1/128 duty Segment drive(ks0108b) Interface circuit RS R/L R/W E RSTB V2R/L V3R/L DB0 ~ DB7 CS1B CS2B CS3 R/L V2R/L V3R/L R/L FR CL V SS KS0108B R/L R/L V2R/L V3R/L R/L RS R/W E RSTB DB0 ~ DB7 CS1B CS2B CS3 RS R/W E RSTB DB0 ~ DB7 CS1B CS2B CS3 FR CL V SS KS0108B CO1 LCD PANEL CO128 R/L V2R/L V3R/L R/L FR CL V SS KS0108B RS R/W E RSTB DB0 ~ DB7 CS1B CS2B CS3 FR CL V SS KS0108B VDD SHL FS S P DS2 DS1 R CR C R f Cf C1 V SS V OR/L V IR/L V 4R/L (aster) C64 V 5R/L FR DIO2 DIO1 5 2 VOR/L VIR/L R/L R/L V SS S (Slave) DIO1 R CR C FR DIO2 C1 C64 P FS DS1 DS2 SHL open open open open open open open V 0 V 1 V 2 V 3 V 4 V PU S1~S64 S 1~S64 S1~S 64 S1~S RS R/W E RSTB DB0 - DB7 15 CS1B CS2B CS3

16 PAD DIAGRA Y ( 0, 0 ) X CHIP SIZE : PAD SIZE : UNIT : m * There is mark of on the center in chip

17 PAD LOCATION PAD NAE PAD NAE PAD NAE PAD NUBER PAD NUBER PAD NUBER COORDINATE COORDINATE COORDINATE Y Y X X Y X C46 C45 C44 C43 C42 C41 C40 C39 C38 C37 C36 C35 C34 C33 C32 C31 C30 C29 C28 C27 C26 C25 C24 C CR SHL VSS S FR P DIO2 R R R R VEE C64 C63 C62 C61 C60 C59 C58 C57 C56 C55 C54 C53 C52 C51 C50 C49 C48 C C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 VEE L L L L VDD DIO1 FS DS1 DS2 C R UNIT ( m)