80CH COMMON / SEGMENT DRIVER FOR DOT MATRIX LCD

Transcription

1 K006 0H OMMON / EGMENT RIVER FOR OT MATRIX L INTROUTION The K006 is an L driver LI which is fabricated by low power MO high voltage process technology. In segment driver mode, it can be interfaced in -bit serial or -bit parallel method by the controller. In common driver mode, dual type mode is applicable. And in segment mode application, the power down function reduces power consumption. 00 QFP-0 FEATURE Power supply voltage : +5 V ± 0 %, + V ± 0 % upply voltage for display : 6 to V (V-VEE) -bit parallel/-bit serial data processing (in segment mode). ingle mode operation / dual mode operation (in common mode). Power down function (in segment mode). Applicable L duty : /6 ~ /56 Interface 00 TQFP- RIVER OM (cascade) K006 EG (cascade) K006 High voltage MO process Available PKG type : bare chip, 00-QFP, 00-TQFP and 00-TAB.

2 K006 0H OMMON / EGMENT RIVER FOR OT MATRIX L PAKAGE INFORMATION K006 PKG TYPE 00QFP PAKAGE K006 L AM L _I _L _M _R V HL V IP0FFB M V0 V V V5 VEE

3 K006 0H OMMON / EGMENT RIVER FOR OT MATRIX L K006TB PKG TYPE 00TP PAKAGE N N N N N N K006 E R B V E E V 5 V V V 0 M I V H L V L I L A M L E L B P O F F B R M #0 # * PKG TYPE = 00 - TAB - 5 mm * INPUT LEA PITH = 0.0 mm * OUTPUT LEA PITH = 0. mm

4 K006 0H OMMON / EGMENT RIVER FOR OT MATRIX L PA IAGRAM (K006/K006TB)) VEE V5 V V V0 M IPOFFB V HL V _R _M _L _I L AM L K006 Y (0,0) X HIP IZE : 50 X 90 PA IZE : 9 X 9 UNIT : µm

5 K006 0H OMMON / EGMENT RIVER FOR OT MATRIX L PA LOATION (K006/K006TB) PA NO. PA NAME OORINATE PA PA OORINATE PA PA OORINATE NO. NAME NO. NAME X Y X Y X Y V V M IPOFFB V HL V _R _M _L _I L L VEE V V

6 K006 0H OMMON / EGMENT RIVER FOR OT MATRIX L K006TQ PKG TYPE 00TQFP PAKAGE L AM L _I _L _M _R V HL V IPOFFB M V0 V V V5 VEE K * PKG TYPE = 00 - TQFP - * PKG THIKNE =.00 ( ± 0.05) mm * PKG IZE =.00 ( ± 0.0) X.00 ( ± 0.0) mm * PA PITH = 0.5 mm * PA WITH = 0.0 ( + 0, 0, -0.0) mm * PA LENGTH =.00 ( ± 0.) mm

7 K006 0H OMMON / EGMENT RIVER FOR OT MATRIX L PA IAGRAM (K006TQ) VEE V5 V V V0 M IPOFFB V HL V _R _M _L _I L BN06X (0,0) Y X HIP IZE : 0 X 600 PA IZE : 9 X 9 UNIT : µm AM L

8 K006 0H OMMON / EGMENT RIVER FOR OT MATRIX L PA LOATION (K006TQ) PA NO. PA NAME OORINATE PA PA OORINATE PA PA OORINATE NO. NAME NO. NAME X Y X Y X Y _I L AM L VEE V V V V M IPOFFB V HL V _R _M _L 969 9

9 K006 0H OMMON / EGMENT RIVER FOR OT MATRIX L BLOK IAGRAM 9 0 V0 V V V5 0-bit -level driver VEE M IPOFFB Output level selector LK 0-bit level driver 0-bit data latch / common data bi-directional shift register _I _L _M _R K 0 x -bit segment data bi-directional shift register L L lock control ata latch control AM Power down function V V

10 K006 0H OMMON / EGMENT RIVER FOR OT MATRIX L BLOK ERIPTION Name lock control ata latch control Power down function Output level selector 0x-bit segment data I-directional shift register 0-bit data latch/common data I-directional shift register 0-bit level shifter 0-bit -level driver Function Generates latch clock (LK), shift clock (K) and control clock timing according to the input of L, L and control inputs (, AM). In common driver application mode, this block generates the shift clock (LK) for the common data I-directional shift register. etermines the direction of segment data shift, and input data of each I- directional shift register. In -bit segment data parallel transfer mode, data is shifted by a -bit unit. In common driver application mode, data is transferred to the common data shift register directly, which disables this block. ontrols the clock enable state of the current driver according to the input value of enable pin ( or ). If enable input value is Low, every clock of the current driver is enabled and the clock control block works. But if enable input is High, current driver is disabled and the input data value has no effect on the output level. o power consumption can be lowered. ontrols the output voltage level according to the input control pin (M and IPOFFB) (refer to PIN ERIPTION). tores output data value by shifting the input values. In -bit serial interface mode application, all 0 shift clocks (K) are needed to store all the display data. But in -bit parallel transfer mode application, only 0 clocks are needed. In common driver application mode, this block does not work. In segment driver application mode, the data from the 0x-bit segment data shift register are latched for segment driver output. In single-type common driver application,-bit input data (from L or R pin) is shifted and latched by the direction according to the HL signal input. In dual-type common application mode, 0-bit registers are divided by two blocks and controlled independently (refer to NOTE ). Voltage level shifter block for high voltage part. The inputs of this block are of logical voltage level and the outputs of this block are at high voltage level value. These values are input in to the driver. elects the output voltage level according to M and latched data value. If the data value is "High" the driver output is at selected voltage level (V0 or V5), and in the reverse case the driver output value is at the nonselected level (V or V). In segment driver application mode, nonselected output value is V or V. and when in common driver application, this value becomes V or V. OM/ EG OM/ EG EG EG OM/ EG EG OM/ EG EG EG

11 K006 0H OMMON / EGMENT RIVER FOR OT MATRIX L PIN ERIPTION Pin Input Output Name Function Interface V V VEE Power supply Logical "High" input port (+5 V ± 0%, + V ± 0%) 0 V (GN) Logical "Low" for high voltage part Power V0, V, V, V5 Input L driver output voltage level Bias supply voltage input to drive the L. Bias voltage divided by the resistance is usually used as a supply voltage source (refer to NOTE ). Power ~ 0 Output L driver output isplay data output pin which corresponds to the respective latch contents. One of V0, V, V and V5 is selected as a display driving voltage source according to the combination of the latched data level and M signal (refer to NOTE ). L L Input ata shift clock lock pulse input for the bi-directional shift register. - In segment driver application mode, the data is shifted to 0 x - bit segment data shift register at the falling edge of this clock pulse. The clock pulse, which was input when the enable bit (/) is in not active condition, is invalid. - In common driver application mode, the data is shifted to 0-bit common data bi-directional shift register by the L clock. Hence, this clock pin is not used (Open or connect this pin to V). ontroller M Input A signal for L driver output Alternate signal input pin for L driving. Normal frame inversion signal is input in to this pin. ontroller L Input ata latch clock - In segment driver application mode, this signal is used for latching the shift register contents at the falling edge of this clock pulse. L pulse "High" level initializes power-down function block. - In common driver application mode, L is used as a shifting clock of common output data. ontroller IPOFFB Input isplay off control ontrol input pin to fix the driver output (~0) to V0 level, during "Low" value input. L becomes non-selected by V0 level output from every output of segment drivers and every output of common drivers. ontroller Input OM/EG mode control When = "Low", K006 is used as an 0-bit segment driver. When = "High", K006 is set to an 0-bit common driver V/V According to the input value of the AM and the pin, application mode of K006 is differs as shown below. AM Application mode OM/EG AM Input Application mode select 0 0 -bit parallel interface mode EG 0 -bit serial interface mode V/V 0 single-type application mode OM dual-type application mode

12 K006 0H OMMON / EGMENT RIVER FOR OT MATRIX L PIN ERIPTION (continued) Pin _I, _L, _M, _R HL, Input Output Input/ Output Input Input/ Output Name Function Interface isplay data input / serial input data / left, right data input output hift direction control Enable data input/output - In segment driver application mode, these pins are used as -bit data input pin (when -bit parallel interface mode : AM = "Low"), or _I is used as serial data input pin and other pins are not used (connect these to V) (when -bit serial interface mode : AM = "High"). - In common driver application mode, the data is shifted from _L(_R) to _R(_L), when in single type interface mode (AM = "Low"). In dual-type application case, the data are shifted from _L and _M (_R and _M) to _R(_L). In each case the direction of the data shift and the connection of data pins are determined by HL input (refer to NOTE, NOTE ). When HL = "Low", data is shifted from left to right. When HL = "High", the direction is reversed. (refer to NOTE) - In segment driver application mode, the internal operation is enabled only when enable input ( or ) is Low (power down function). When several drivers are serially connected, the enable state of each driver is shifted according to the HL input. onnect these pins as below. - In common driver application mode, power down function is not used. Open these pins. HL L H EGMENT RIVER Output (open) Input (V) Input (V) Output (open) ontroller V/V - NOTE. Output level control X : don t care Output level ( ~ 0) M Latched data IPOFFB EG Mode OM Mode L L H V(V) V(V) L H H V0 V5 H L H V(V) V(V) H H H V5 V0 X X L V0 V0

13 K006 0H OMMON / EGMENT RIVER FOR OT MATRIX L NOTE. L driving voltage application circuit () egment driver application ( = Low ) V V R R (n-)r R R V0 V V V V V5 to OM driver to OM driver V0 V V V5 V K006 V EG ~ EG0 V0,V5 V,V to L Panel election level Non-selection level VEE * n = 9 (when /6 duty) to (when /56 duty) () ommon driver application ( = High ) V V R R (n-)r V0 V V V to EG driver V0 V V K006 EG ~ EG0 to L Panel R R V V5 V V5 V V0,V5 V,V election level Non-selection level VEE * n = 9 (when /6 duty) to (when /56 duty)

14 K006 0H OMMON / EGMENT RIVER FOR OT MATRIX L NOTE. ata shift direction according to control signals () When = Low (segment driver application) AM HL Application mode ata direction Input pin L L -bit parallel data transfer mode (EG) _I, _L, _M, _R H H L -bit serial data transfer mode (EG) _I H first data hift direction last data first data hift direction last data first data hift direction last data (_I) last data hift direction first data

15 K006 0H OMMON / EGMENT RIVER FOR OT MATRIX L () When = High (common driver application) AM HL Application mode ata direction Input pin hift direction L _L L single-type application mode (OM) Input data (_L) hift direction Output data (_R) H _R Output data (_L) Input data (_R) hift direction L _L, _M L dual-type application mode (OM) Input data (_L) Input data (_M) hift direction Output data (_R) H _R, _M Output data (_L) Input data (_M) Input data (_R)

16 K006 0H OMMON / EGMENT RIVER FOR OT MATRIX L NOTE. Usage of data pins OM/EG ( pin) EG ( = Low ) OM ( = High ) Application mode (AM pin) -bit parallel interface mode (AM = Low ) -bit serial interface mode (AM = High ) single-type application mode (AM = Low ) dual-type application mode (AM = High ) HL X X L H L H ata interface pin _I _L _M _R (input) I (input) open open (input) L (input) L (output) L (input) L (output) (input) onnect to V open M (input) M (input) * X = don t care (input) R (output) R (input) R (output) R (input)

17 K006 0H OMMON / EGMENT RIVER FOR OT MATRIX L MAXIMUM ABOLUTE LIMIT haracteristic ymbol Value Unit Power supply voltage V -0. ~ +.0 river supply voltage V L 0 ~ +0 Input voltage V IN -0. ~ V + 0. Operating temperature Topr -0 ~ +5 torage temperature Tstg -55 ~ +50 V o * NOTE: Voltage greater than above may do damage to the circuit.

18 K006 0H OMMON / EGMENT RIVER FOR OT MATRIX L ELETRIAL HARATERITI HARATERITI () EGMENT RIVER APPLIATION haracteristic ymbol Test ondition MIN TYP MAX Unit Operating voltage Input voltage (*) V V L V IN = V - VEE 6 - (Vss = 0V, Ta = -0 ~ +5 o ) V IH - 0.V - V V IL V V Output voltage (*) V OH I OH = -0. ma V V OL I OL = 0. ma V Input leakage current (*) Input leakage current (*) On resistance (*) upply current (*5) I IL V IN = V to V -0-0 I IL V IN = Vto VEE -5-5 R ON I ON = 00 µa - KΩ I TBY f L = khz M=V µa V pin µa V=5 V I fl = khz ma V= V - - f M =0 Hz I EE V=5 V µa NOTE (*) Applied to L, L,,, _I ~ _R, HL, IPOFFB, M,, AM pin (*), pin (*) V0, V, V, V5 pin (*) VL=V-VEE, V0=V=5 V, V5=VEE=- V V=V-/n(VL), V=VEE+/n(VL), n = (/56 duty, / bias) (*5) V0=V, V=. V(V=5V) or V(V= V), V=-9. V(V=5 V) or -9.9 V(V= V), V5=VEE=- V, no-load condition (/56 duty, / bias) -bit parallel interface mode I TBY : V=5 V, fl=5. MHz, HL=V, IPOFFB=V, M=V, display data pattern = 0000 I : V= V, f L = MHz, display data pattern = 00 V=5 V, f L =5. MHz, display data pattern = 00 I EE : V=5 V, f L =5. MHz, display data pattern = 00, VEE pin

19 K006 0H OMMON / EGMENT RIVER FOR OT MATRIX L HARATERITI (continued) () OMMON RIVER APPLIATION haracteristic ymbol Test ondition MIN TYP MAX Unit Operating voltage Input voltage (*) (Vss = 0 V, Ta = -0 ~ +5 o ) V V L V IN = V - VEE 6 - V IH - 0.V - V V IL V V Output voltage (*) V OH I OH = -0. ma V V OL I OL = 0. ma V Input leakage current (*) Input leakage current (*) Input leakage current (*) On resistance (*5) I IL V IN = V to V -0-0 I IL V IN = 0 V, V = 5 V (PULL UP) I IL V IN = V to VEE -5-5 R ON I ON = 00 µa - KΩ I TBY f L = khz V pin µa upply current (*6) V=5 V I fl = khz V= V f M =0 Hz I EE V=5 V µa NOTE (*) Applied to L, _L (HL=LOW), _R (HL=HIGH), HL, IPOFFB, M,, AM pin (*) Pull-up input pins : L, _I, _M (AM=HIGH), (HL=LOW), (HL=HIGH) (*) _L (HL=HIGH),_R (HL=LOW) pin (*) V0, V, V, V5 pin (*5) VL=V-VEE, V0=V=5 V, V5=VEE=- V V=V-/n(VL), V=VEE+/n(VL), n = (/56 duty, / bias) (*6) V0=V, V=.5 V(V=5 V) or. V(V= V), V=-.5 V(V=5 V) or -. V(V= V), V5=VEE=- V, no-load condition (/56 duty, / bias) single-type mode operation : AM=V, HL=V, IPOFFB=V _I=_M=V, _R=OPEN, ==OPEN, I TBY : V=5 V, M=V, _L=V I : fm=0 Hz, _L=V V= V, display data pattern = , , , ,.. V=5 V, display data pattern = , , , ,.. I EE : fm=0hz, _L=V V=5 V, current through V EE Pin, display data pattern = , , ,

20 K006 0H OMMON / EGMENT RIVER FOR OT MATRIX L A HARATERITI () EGMENT RIVER APPLIATION (Vss = 0 V, Ta = -0 ~ +5 o ) haracteristic ymbol Test ondition () V=5 V ± 0% () V= V ± 0% MIN TYP MAX MIN TYP MAX lock cycle time t Y uty=50% Unit lock pulse width t WK lock rise/fall time t R/tF ata set-up time t ata hold time t H lock set-up time t ns lock hold time t H Output 60 5 Propagation delay time t PHL Output 60 5 Input 0 65, set-up time t PU - - Input IPOFFB low pulse width t WL µs IPOFFB clear time t ns M - OUT propagation delay time L - OUT propagation delay time IPOFFB - OUT propagation delay time t P t P L=5 pf t P µs

21 K006 0H OMMON / EGMENT RIVER FOR OT MATRIX L A HARATERITI (continued) () OMMON RIVER APPLIATION (Vss = 0 V, Ta = -0 ~ +5 o ) haracteristic ymbol Test ondition () V=5 V ± 0% () V=V±0% MIN TYP MAX MIN TYP MAX lock cycle time t Y uty=50% Unit lock pulse width t WK lock rise/fall time t R/tF ns ata set-up time t ata hold time t H IPOFFB low pulse width t WL µs IPOFFB clear time t Output delay time M - OUT propagation delay time L - OUT propagation delay time IPOFFB - OUT propagation delay time t L t P L=5 pf t P t P ns µs

22 K006 0H OMMON / EGMENT RIVER FOR OT MATRIX L A HARATERITI (continued) () EGMENT RIVER APPLIATION TIMING L 0.V 0.V twk 0.V 0.V t th L 0.V 0.V tr 0.V twk ty twk 0.V tf t 0.V 0.V th _I~_R 0.V 0.V 0.V 0.V twl t IPOFFB L L V tphl 0.V, (Output), (Input) 0.V 0.V tpu M 0.V 0.V L 0.V tp tp IPOFFB 0.V 0.V tp ~0 (Latched data)

23 K006 0H OMMON / EGMENT RIVER FOR OT MATRIX L A HARATERITI (continued) () OMMON RIVER APPLIATION TIMING ty L 0.V 0.V twkh 0.V 0.V tr t tf th tf (*) I 0.V 0.V tl 0.V 0.V (*) O 0.V 0.V twl t IPOFFB (*) When in single-type interface mode I _L(HL="L"), _R(HL="H") O _R(HL="L"), _L(HL="H") When in dual-type interface mode I _L and _M(HL="L"), _R and _M(HL="H") O _R(HL="L"), _L(HL="H") M 0.V 0.V L 0.V tp tp IPOFFB 0.V 0.V tp ~0 (Latched data)

24 K006 0H OMMON / EGMENT RIVER FOR OT MATRIX L POWER OWN FUNTION In the case of cascade connection of segment mode drivers, K006 has a "power down function" In order to reduce the power consumption. HL Enable input Enable output L H urrent driver status While ="Low", current driver is enabled. While ="Low", current driver is enabled. The other drivers status isabled isabled * In the case of common driver application, power down function does not work. L L n- n n- n n- n n- n n- (Input) / (Output/Input) / (Output/Input) / (Output/Input) (Output) NOTE ) HL = "High" ( = Input, = Output) urrent K006's must be connected to the next K006's. ) When in -bit parallel interface mode : n = 0 When in -bit serial interface mode : n = 0

25 K006 0H OMMON / EGMENT RIVER FOR OT MATRIX L OPERATION TIMING IAGRAM () -BIT PARALLEL MOE INTERFAE EGMENT RIVER When HL = "Low" L _I _L _M _R (Input) (Output) L ~0 When HL = "High" L _I _L _M _R (Input) (Output) L ~0

26 K006 0H OMMON / EGMENT RIVER FOR OT MATRIX L () -BIT ERIAL MOE INTERFAE EGMENT RIVER When HL = "Low" L _I (Input) (Output) L ~0 When HL = "High" L _I (Input) (Output) L ~0

27 K006 0H OMMON / EGMENT RIVER FOR OT MATRIX L () INGLE-TYPE INTERFAE MOE OMMON RIVER When HL = "Low" L _L _R OM_ATA OM_ATA OM_ATA OM_ATA9 OM_ATA0 urrent driver's OMMON area When HL = "High" L _R _L OM_ATA OM_ATA OM_ATA OM_ATA9 OM_ATA0 urrent driver's OMMON area

28 K006 0H OMMON / EGMENT RIVER FOR OT MATRIX L () UAL-TYPE INTERFAE MOE OMMON RIVER When HL = "Low" L _L _M _R OM_ATA OM_ATA OM_ATA OM_ATA9 OM_ATA0 OM_ATA OM_ATA OM_ATA OM_ATA9 OM_ATA0 When HL = "High" L _L _M _R OM_ATA OM_ATA OM_ATA OM_ATA9 OM_ATA0 OM_ATA OM_ATA OM_ATA OM_ATA9 OM_ATA0

29 K006 0H OMMON / EGMENT RIVER FOR OT MATRIX L (5) OMMON / EGMENT RIVER TIMING (/00 UTY) L LATHE ATA(EG) M OM_ATA OM_ATA99 OM_ATA00 OM V0 V V V5 OM99 OM00 V0 V V V5 V0 V V V5 EG_ATA EG V0 V V V V V5 L 9 0 L ~ LATHE _ATA M ENABLE OUT

30 K006 0H OMMON / EGMENT RIVER FOR OT MATRIX L APPLIATION INFORMATION () -BIT ERIAL INTERFAE MOE (0-H EGMENT RIVER) a) Lower View (HL = L, AM = H) L PANEL n n+0 -bit serial data input 0 AM HL _I _L~ _R 0 AM HL _I _L~ _R 0 AM HL _I _L~ _R b) Upper View (HL = H, AM = H) -bit serial data input _R _L~ _I HL AM 0 _R _L~ _I HL AM 0 _R _L~ _I HL AM L PANEL n n+0

31 K006 0H OMMON / EGMENT RIVER FOR OT MATRIX L () -BIT PARALLEL INTERFAE MOE (0-H EGMENT RIVER) a) Lower View (HL = L, AM = L) L PANEL n n+0 0 AM HL _I~ _R 0 AM HL _I~ _R 0 AM HL _I~ _R -bit parallel data input b) Upper View (HL = H, AM = L) -bit parallel data input _I~_R HL AM 0 _I~_R HL AM 0 _I~_R HL AM n n+0 L PANEL

32 K006 0H OMMON / EGMENT RIVER FOR OT MATRIX L () UAL-TYPE INTERFAE MOE (0H + 0H OMMON RIVER) input data _R 0 AM HL _L 0 _R 0 L PANEL (/) AM HL _L 60 input data _R _M 0 6 AM HL _L _R AM HL _L 0 0 L PANEL (/) _R 0 AM HL _L 00 * NOTE: Using this application mode (dual-type common mode), the duty ratio can be reduced to half. In the case abale, /00 duty can be used to drive the 00 common L panel.

33 K006 0H OMMON / EGMENT RIVER FOR OT MATRIX L () INGLE-TYPE INTERFAE MOE (0-H OMMON RIVER) input data AM HL AM HL _R _L _R _L L PANEL _R 0 6 AM HL _L 0

34 K006 0H OMMON / EGMENT RIVER FOR OT MATRIX L APPLIATION IRUIT EXAMPLE V V0 R V R V OM/ EG OM EG V0~V5 _I~_R IPOFFB M L L AM HL K006 0 V0~V5 _I~_R IPOFFB L M L K006 AM HL 0 V0~V5 _I~_R IPOFFB L M L K006 AM HL 0 (n-)r V EG EG ~ EG0 EG ~ EG0 EG ~ EG0 V R R V V5 OM OM/ EG M _R IPOFFB 0 OM ~ K006 AM OM0 HL V0~V5L _L VEE ontroller IPOFFB FRAME(M) M _R IPOFFB 0 OM ~ K006 OM0 AM HL V0~V5L _L 60 0 X 0 L MOULE OM_ATA ~ L L M _R IPOFFB 0 K006 AM HL V0~V5L _L OM ~ OM0 6 0