LC79430KNE. Overview. Features. CMOS LSI Dot-Matrix LCD Drivers

Transcription

1 Ordering number : ENA2123 COS LSI Dot-atrix LCD Drivers Overview The is a large-scale dot matrix LCD common driver LSI. The contains an 80-bit bidirectional shift register and is equipped with a 4-level LCD driver. The input/output pins for cascade connection can be used to further increase the IC s number of bits. The can be used in conjunction with segment driver LC79401KNE (QIP100E) to drive a wide-screen LCD panel. Features On-chip LCD drive circuit (80 bits) Display duty selection ranging from 1/64 to 1/256 On-chip input/output pins support a further increases in bit number Supports externally supplied bias voltage On-chip 80-bit bidirectional shift register (supports 40-bit 2 division) Supports single mode (80-bit shift register) and dual mode (40-bit 2 shift register) applications (1) O1 O80 Single mode (2) O80 O1 (3) O1 O40 and O41 O80 Dual mode (4) O80 O41 and O40 O1 All four of the shift direction selection listed above all supported Operating power supply voltage/operating temperature include VDD (Logic section) : 2.7 to 5.5V/-20 to +85 C VDD- (LCD section) : 12 to 32V/-20 to +85 C COS process 100-pin flat plastic package (QIP100E) Semiconductor Components Industries, LLC, 2013 July, HKPC S00002 No. A2123-1/7

2 Specifications Absolute aximum atings at Ta = 25±2 C, = 0V Parameter Symbol Conditions atings unit aximum supply voltage (Logic) V DD max -0.3 to +7.0 V aximum supply voltage (LCD) V DD -V EE max *1 0 to 35 V aximum input voltage V I max -0.3 to V DD +0.3 V Storage temperature Tstg -40 to +125 C Note *1 The following relations between elements should be maintained: VDD >>>, VDD- 7V, - 7V Stresses exceeding aximum atings may damage the device. aximum atings are stress ratings only. Functional operation above the ecommended Operating Conditions is not implied. Extended exposure to stresses above the ecommended Operating Conditions may affect device reliability. Allowable Operating anges at Ta = -20 to +85 C, = 0V Parameter Symbol Conditions min typ max unit Supply voltage (Logic) V DD V Supply voltage (LCD) V DD -V EE *2, V Input high level voltage V IH,,,, DIN, ODE,, Input low level voltage V IL,,,, DIN, ODE,, 0.8V DD V 0.2V DD V Shift clock f 1 Hz pulse width t WC 63 ns Setup time t SETUP,, DIN Hold time t HOLD,, DIN 100 ns 100 ns rise time t 50 ns fall time t F 50 ns Note *2 The following relations between elements should be maintained: VDD >>>, VDD- 7V, - 7V *3 When the power supply is turned on, power to the LCD driver is turned on after or simultaneously with the turning on of the logic section s power supply. When the power supply is turned off, the logic power supply is turned off after or at the same time the LCD driver power supply is turned off. Electrical Characteristics at Ta = 25±2 C, VDD = 2.7 to 5.5V Parameter Symbol Conditions min typ max unit Input high level current I IH V IN =V DD, V DD =5.5V,,,,, DIN, ODE,, 1 μa Input low level current I IL V IN =V SS, V DD =5.5V,,,,, DIN, ODE,, -1 μa Output high level voltage V OH I OH =-0.4mA,, V DD -0.4 V Output low level voltage V OL I OL =0.4mA,, 0.4 V Driver on resistance ON (1) V DD -V EE =30V, V DE -V O =0.5V V DD =4.5V, *4 1.0 kω ON (2) V DD -V EE =20V, V DE -V O =0.5V V DD =4.5V, *4 1.0 kω Consumable current drain (1) I SS V DD -V EE =30V, =14kHz no-load, V DD =5.5V ; V SS 100 μa Consumable current drain (2) I EE V DD -V EE =30V, =14kHz no-load, V DD =5.5V ; V EE 100 μa Input capacitance CI f=1hz ; 8 pf Note *4 VDE = or or or, = VDD, = 16/17 (VDD-), = 1/17 (VDD-) Switching Characteristics at Ta = 25±2 C, = 0V, VDD = 2.7 to 5.5V Parameter Symbol Conditions min typ max unit Output delay time t PLH CL=15pF ;, 250 ns t PHL CL=15pF ;, 250 ns No. A2123-2/7

3 Package Dimensions unit:mm (typ) 3151A (0.58) max (2.7) SANYO : QIP100E(14X20) Pin Assignment O50 O49 O48 O47 O46 O45 O44 O43 O42 O41 O40 O39 O38 O37 O36 O35 O34 O33 O32 O31 O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 O16 O17 O18 O19 O20 O21 O22 O23 O24 O25 O26 O27 O28 O29 O30 O80 O79 O78 O77 O76 O75 O74 O73 O72 O71 O70 O69 O68 O67 O66 O65 O64 O63 O62 O61 O60 O59 O58 O57 O56 O55 O54 O53 O52 O51 VDD ODE DIN Top view No. A2123-3/7

4 Equivalent Circuit Block Diagram O1 O2 O3 O79 O80 4 Level LCD Drive Circuit (80 bits) VDD Level Shifter (80bits) Bidirectional Shift egister (80 bits) ODE DIN No. A2123-4/7

5 Pin Function Pin No Symbol Function 90 V DD 92 V SS Supply V DD -V SS : Logic power supply V DD -V EE : LCD drive circuit power supply 84 V EE 87 LCD drive level power supply 86 Supply, V EE : Selected level 85, : Unselected level 96 I Bidirectional shift register shift clock (falling edge trigger) ODE Data Transfer Direction DIN L L (Shift right) O1 O80 IN OUT * (Single) H (Shift left) O80 O1 OUT IN * 91 I L (Shift right) O1 O40 95 ODE I H O41 O80 97 DIN I (Dual) H (Shift left) O80 O41 O40 O1 * Don t care (ay be set to either H or L ) 94 I LCD drive output alternation signal IN OUT IN OUT IN IN 89 I output controlling input pins. 1 O1 LCD drive outputs The output levels are determined by the combination of the output the data, The signal, and the pin as shown in the table. Data Output L L H O L H H V EE H L H H H H * * L * Don t care (ay be set to either H or L ) 80 O ust be left open No. A2123-5/7

6 Application Example (LC79401KNE/) Com1 Com2 Com3 LCD PANEL /240 duty Com238 Com239 Com240 Seg320 Seg319 Seg318 Seg3 Seg2 Seg1 /L V4 V DD V SS Power supply circuit Case of 1/n bias CDI LC79401KNE CDO CDI LC79401KNE CDO CDI LC79401KNE CDO V DD #1 V DD #2 V DD #4 /L V4 /L V4 #1 ODE DIN #3 V DD V SS Controller FL GND V DD (n-4) ODE DIN V4 + - No. A2123-6/7

7 Switching Characteristics Diagram t twc tf 0.8VDD 0.2VDD tsetup thold () (DIN) tplh, tphl () ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitabilityof its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PS No. A2123-7/7