8-Bit Bidirectional Universal Shift Register with Parallel I/O High-Speed Silicon-Gate CMOS

Transcription

1 TECHNICAL ATA IN74ACT299 8-Bit Bidirectional Universal Shift Register with Parallel I/O High-Speed Silicon-Gate CMOS The IN74ACT299 is identical in pinout to the LS/ALS299, HC/HCT299. The IN74ACT299 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. The IN74ACT299 features a multiplexed parallel input/output data port to achieve full 8-bit handling in a 20 pin package. ue to the large output drive capability and the 3-state feature, this device is ideally suited for interface with bus lines in a bus-oriented system. Two Mode-Select inputs and two Output Enable inputs are used to choose the mode of operation as listed in the Function Table. Synchronous parallel loading is accomplished by taking both Mode- Select lines, S1 and S2, high. This places the outputs in the highimpedance state, which permits data applied to the data port to be clocked into the register. Reading out of the register can be accomplished when the outputs are enabled. The active-low asynchronous Reset overrides all other inputs. TTL/NMOS Compatible Input Levels Outputs irectly Interface to CMOS, NMOS, and TTL Operating oltage Range: 4.5 to Low Input Current: 1.0 μa; 25 C Outputs Source/Sink 24 ma ORERING INFORMATION IN74ACT299N Plastic IN74ACT299W SOIC TA = -40 to 85 C for all packages PIN ASSIGNMENT LOGIC IAGRAM PIN 20=CC PIN 10 = GN 1

2 MAXIMUM RATINGS * Symbol Parameter alue Unit CC C Supply oltage (Referenced to GN) -0.5 to +7.0 IN C Input oltage (Referenced to GN) -0.5 to CC +0.5 OUT C Output oltage (Referenced to GN) -0.5 to CC +0.5 IIN C Input Current, per Pin ±20 ma IOUT C Output Sink/Source Current, per Pin ±50 ma ICC C Supply Current, CC and GN Pins ±50 ma P Power issipation in Still Air, Plastic IP+ SOIC Package+ Tstg Storage Temperature -65 to +150 C TL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic IP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +erating - Plastic IP: - 10 mw/ C from 65 to 125 C SOIC Package: : - 7 mw/ C from 65 to 125 C mw 260 C RECOMMENE OPERATING CONITIONS Symbol Parameter Min Max Unit CC C Supply oltage (Referenced to GN) 4.5 IN, OUT C Input oltage, Output oltage (Referenced to GN) 0 CC TJ Junction Temperature (PIP) 140 C TA Operating Temperature, All Package Types C IOH Output Current - High -24 ma IOL Output Current - Low 24 ma tr, tf Input Rise and Fall Time * (except Schmitt Inputs) CC =4.5 CC = ns/ * IN from to This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, IN and OUT should be constrained to the range GN (IN or OUT) CC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GN or CC). Unused outputs must be left open. 2

3 C ELECTRICAL CHARACTERISTICS(oltages Referenced to GN) CC Guaranteed Limits Symbol Parameter Test Conditions 25 C -40 C to 85 C IH Minimum High- Level Input oltage IL Maximum Low - Level Input oltage OH Minimum High- Level Output oltage OUT= or CC- 4.5 OUT= or CC- 4.5 IOUT -50 μa Unit * IN=IH or IL IOH=-24 ma IOH=-24 ma OL Maximum Low- Level Output oltage IOUT 50 μa 4.5 IIN ΔICCT IOZ IOL IOH ICC Maximum Input Leakage Current Additional Max. ICC/Input Maximum Three- State Leakage Current +Minimum ynamic Output Current +Minimum ynamic Output Current Maximum Quiescent Supply Current (per Package) * IN= IH or IL IOL=24 ma IOL=24 ma IN=CC or GN ± ±1.0 μa IN=CC ma IN (OE)= IH or IL IN =CC or GN OUT =CC or GN ±0.6 ±6.0 μa OL=1.65 Max 75 ma OH=3.85 Min -75 ma IN=CC or GN μa * All outputs loaded; thresholds on input associated with output under test. +Maximum test duration ms, one output loaded at a time. 3

4 AC ELECTRICAL CHARACTERISTICS(CC=5.0 ± 10%, CL=50pF,Input tr=tf=3.0 ns) Guaranteed Limits Symbol Parameter 25 C -40 C to 85 C Unit Min Max Min Max fmax Maximum Clock Frequency (Figure 1) MHz tplh Propagation elay, Clock to QA or QH (Figure 1) ns tphl Propagation elay, Clock to QA or QH (Figure 1) ns tplh tphl Propagation elay, Clock to QA thru QH (Figure 1) Propagation elay, Clock to QA thru QH (Figure 1) ns ns tphl Propagation elay, Reset to QA or QH (Figure 2) ns tphl Propagation elay, Reset to QA thru QH (Figure 2) ns tpzh tpzl tphz tplz Propagation elay, OE1, OE2 to QA thru QH Propagation elay, OE1, OE2 to QA thru QH Propagation elay, OE1, OE2 to QA thru QH Propagation elay, OE1, OE2 to QA thru QH ns ns ns ns CIN Maximum Input Capacitance pf C,CC=5.0 CP Power issipation Capacitance 170 pf TIMING REQUIREMENTS(CC=5.0 ± 10%, CL=50pF, Input tr=tf=3.0 ns) Guaranteed Limits Symbol Parameter 25 C -40 C to 85 C tsu Minimum Setup Time, Mode Select S1 or S2 to Clock (Figure 4) 5.0 ns tsu Minimum Setup Time, ata Inputs PA thru PH to Clock (Figure 4) ns tsu Minimum Setup Time, ata Inputs SA, SH to Clock (Figure 4) ns th Minimum Hold Time, Clock to Mode Select S1 or S2 (Figure 4) ns th Minimum Hold Time, Clock to ata Inputs PA thru PH (Figure 4) ns th Minimum Hold Time, Clock to ata Inputs SA, SH (Figure 4) ns trec Minimum Recovery Time, Reset Inactive to Clock (Figure 2) ns tw Minimum Pulse Width, Clock (Figure 1) ns tw Minimum Pulse Width, Reset (Figure 2) ns Unit 4

5 FUNCTION TABLE Inputs Response Mode Reset Mode Select Output Enables Clock Serial Inputs PA/ QA PB/ PC/ QC P/ Q PE/ QE PF/ QF PG/ PH/ QH QA QH S2 S1 OE1 OE2 A H Reset L X L L L X X X L L L L L L L L L L Shift Right Shift Left Parallel Load L L X L L X X X L L L L L L L L L L L H H X X X X X QA through QH=Z L L H L H H X X Shift Right: QA through QH=Z; A FA; FA FB; etc H L H X H X Shift Right: QA through QH=Z; A FA; FA FB; etc H L H L L X Shift Right: A FA =QA; FA FB =; etc H H L H X X Shift Left: QA through QH=Z; H FH; FH FG; etc H H L X H X Shift Left: QA through QH=Z; H FH; FH FG; etc H H L L L X Shift Left: H FH =QH; FH FG =; etc H H H X X X X Parallel Load:PN FN PA PH Hold H L L H X X X X Hold: QA through QH=Z; FN=FN PA PH H L L X H X X X Hold: QA through QH=Z; FN=FN PA PH H L L L L X X X Hold: QN =QH PA PH Z = high impedance = data on serial input F = flip-flop (see Logic iagram) When one or both output controls are high the eight input/output terminals are disabled to the highimpedance state; however, sequential operation or clearing of the register is not affected. 5

6 Figure 1. Switching Waveform Figure 2. Switching Waveform Figure 3. Switching Waveform Figure 4. Switching Waveform 6

7 EXPANE LOGIC IAGRAM 7