LOW POWER SCHOTTKY. GUARANTEED OPERATING RANGES ORDERING INFORMATION

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The SN74LS64 is a high speed 8-Bit Serial-In Parallel-Out Shift Register. Serial data is entered through a 2-Input AN gate synchronous with the LOW to HIGH transition of the clock.

1 The SN74LS64 is a high speed 8-Bit Serial-In Parallel-Out Shift Register. Serial data is entered through a 2-Input AN gate synchronous with the LOW to HIGH transition of the clock. The device features an asynchronous Master Reset which clears the register setting all outputs LOW independent of the clock. It utilizes the Schottky diode clamped process to achieve high speeds and is fully compatible with all ON Semiconductor TTL products. Typical Shift Frequency of 35 MHz Asynchronous Master Reset Gated Serial ata Input Fully Synchronous ata Transfers Input Clamp iodes Limit High Speed Termination Effects ES > 3500 Volts LOW POWER SCHOTTKY GUARANTEE OPERATING RANGES Symbol Parameter Min Typ Max Unit V CC Supply Voltage V T A Operating Ambient Temperature Range C I OH Output Current High 0.4 ma I OL Output Current Low 8.0 ma 4 PLASTIC N SUFFIX CASE SOIC SUFFIX CASE 75A ORERING INFORMATION evice Package Shipping SN74LS64N 4 Pin IP 2000 Units/Box SN74LS64 4 Pin 2500/Tape & Reel Semiconductor Components Industries, LLC, 999 ecember, 999 Rev. 6 Publication Order Number: SN74LS64/

2 CONNECTION IAGRAM IP (TOP VIEW) V CC MR NOTE: The Flatpak version has the same pinouts (Connection iagram) as the ual In-Line Package A B GN LOAING (Note a) PIN NAMES HIGH LOW A, B MR 0 7 ata Inputs Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input Outputs 0.5 U.L. 0.5 U.L. 0.5 U.L. 0 U.L U.L U.L U.L. 5 U.L. NOTES: a) TTL Unit Load (U.L.) = 40 A HIGH/.6 ma LOW. LOGIC SYMBOL 2 8 A B LS64 8-BIT SHIFT REGISTER MR V CC = PIN 4 GN = PIN 7 2

3 LOGIC IAGRAM 2 A B C C C C C C C C 8 9 MR V CC = PIN 4 GN = PIN 7 = PIN NUMBERS FUNCTIONAL ESCRIPTION The LS64 is an edge-triggered 8-bit shift register with serial data entry and an output from each of the eight stages. ata is entered serially through one of two inputs (A or B); either of these inputs can be used as an active HIGH Enable for data entry through the other input. An unused input must be tied HIGH, or both inputs connected together. Each LOW-to-HIGH transition on the Clock () input shifts data one place to the right and enters into 0 the logical AN of the two data inputs (A B) that existed before the rising clock edge. A LOW level on the Master Reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all outputs LOW. MOE SELECT TRUTH TABLE OPERATING INPUTS OUTPUTS MOE MR A B 0 7 Reset (Clear) L X X L L L H I I L q 0 q 6 Shift H I h L q 0 q 6 H h I L q 0 q 6 H h h H q 0 q 6 L (l) = LOW Voltage Levels H (h) = HIGH Voltage Levels X = on t Care q n = Lower case letters indicate the state of the referenced input or output one q n = set-up time prior to the LOW to HIGH clock transition. 3

4 C CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min Typ Max Unit Test Conditions V IH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs V IL Input LOW Voltage 0.8 V Guaranteed Input LOW Voltage for All Inputs V IK Input Clamp iode Voltage V V CC = MIN, I IN = 8 ma V OH Output HIGH Voltage V V CC = MIN, I OH = MAX, V IN = V IH or V IL per Truth Table V OL Output LOW Voltage V I OL = 4.0 ma V CC = V CC MIN, V IN =V IH or V IL V I OL = 8.0 ma per Truth Table I IH Input HIGH Current 20 µa V CC = MAX, V IN = 2.7 V 0. ma V CC = MAX, V IN = 7.0 V I IL Input LOW Current 0.4 ma V CC = MAX, V IN = 0.4 V I OS Short Circuit Current (Note ) ma V CC = MAX I CC Power Supply Current 27 ma V CC = MAX Note : Not more than one output should be shorted at a time, nor for more than second. AC CHARACTERISTICS (T A = 25 C) Limits Symbol Parameter Min Typ Max Unit Test Conditions f MAX Maximum Clock Frequency MHz t PHL t PLH t PHL Propagation elay MR to Output Propagation elay Clock to Output ns V CC = 5.0 V C L = 5 pf ns AC SETUP REUIREMENTS (T A = 25 C) Limits Symbol Parameter Min Typ Max Unit Test Conditions t W, MR Pulse Width 20 ns t s ata Setup Time 5 ns t h ata Hold Time 5.0 ns V CC =50V 5.0 t rec MR to Clock Recovery Time 20 ns 4

5 AC WAVEFORMS *The shaded areas indicate when the input is permitted to change for predictable output performance. I /f max t W.3 V.3 V.3 V MR.3 V.3 V t W t rec t PHL.3 V t PLH.3 V.3 V CONITIONS: MR = H t PHL.3 V Figure. Clock to Output elays and Clock Pulse Width Figure 2. Master Reset Pulse Width, Master Reset to Output elay and Master Reset to Clock Recovery Time /f max t W.3 V.3 V.3 V.3 V t s (H) t h (H) t s (L) t h (L) *.3 V.3 V.3 V.3 V.3 V.3 V Figure 3. ata Setup and Hold Times 5

6 PACKAGE IMENSIONS B N SUFFIX PLASTIC PACKAGE CASE ISSUE M NOTES:. IMENSIONING AN TOLERANCING PER ANSI Y4.5M, CONTROLLING IMENSION: INCH. 3. IMENSION L TO CENTER OF LEAS WHEN FORME PARALLEL. 4. IMENSION B OES NOT INCLUE MOL FLASH. 5. ROUNE CORNERS OPTIONAL. T SEATING PLANE N A INCHES MILLIMETERS IM MIN MAX MIN MAX A F L B C C F G 0.00 BSC 2.54 BSC H J K K J L M 0 0 H G 4 PL M N (0.005) M 6

7 SUFFIX PLASTIC SOIC PACKAGE CASE 75A 03 ISSUE F A B P 7 PL 0.25 (0.00) M B M NOTES:. IMENSIONING AN TOLERANCING PER ANSI Y4.5M, CONTROLLING IMENSION: MILLIMETER. 3. IMENSIONS A AN B O NOT INCLUE MOL PROTRUSION. 4. MAXIMUM MOL PROTRUSION 0.5 (0.006) PER SIE. 5. IMENSION OES NOT INCLUE AMBAR PROTRUSION. ALLOWABLE AMBAR PROTRUSION SHALL BE 0.27 (0.005) TOTAL IN EXCESS OF THE IMENSION AT MAXIMUM MATERIAL CONITION. T SEATING PLANE G 4 PL K C 0.25 (0.00) M T B S A S R X 45 M J F MILLIMETERS INCHES IM MIN MAX MIN MAX A B C F G.27 BSC BSC J K M P R

8 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORERING INFORMATION North America Literature Fulfillment: Literature istribution Center for ON Semiconductor P.O. Box 563, enver, Colorado 8027 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada ONlit@hibbertco.com N. American Technical Support: Toll Free USA/Canada EUROPE: LC for ON Semiconductor European Support German Phone: (+) (M F 2:30pm to 5:00pm Munich Time) ONlit german@hibbertco.com French Phone: (+) (M F 2:30pm to 5:00pm Toulouse Time) ONlit french@hibbertco.com English Phone: (+) (M F :30pm to 5:00pm UK Time) ONlit@hibbertco.com ASIA/PACIFIC: LC for ON Semiconductor Asia Support Phone: (Tue Fri 9:00am to :00pm, Hong Kong Time) Toll Free from Hong Kong ONlit asia@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center 4 32 Nishi Gotanda, Shinagawa ku, Tokyo, Japan Phone: r453@onsemi.com Fax Response Line: Toll Free USA/Canada ON Semiconductor Website: For additional information, please contact your local Sales Representative. 8 SN74LS64/

LOW POWER SCHOTTKY. GUARANTEED OPERATING RANGES ORDERING INFORMATION

LOW POWER SCHOTTKY. GUARANTEED OPERATING RANGES ORDERING INFORMATION The SN74LS298 is a Quad 2-Port Register. It is the logical equivalent of a quad 2-input multiplexer followed by a quad 4-bit edge-triggered register. A Common Select input selects between two 4-bit input