MARKING DIAGRAMS 16 MAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 1.) ORDERING INFORMATION PDIP 16 P SUFFIX CASE 648

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1 查询 CD4553 供应商 The MC14553B 3 digit BCD counter coists of 3 negative edge triggered BCD counters that are cascaded synchronously. A quad latch at the output of each counter permits storage of any given count. The information is then time division multiplexed, providing one BCD number or digit at a time. Digit select outputs provide display control. All outputs are TTL compatible. An on chip oscillator provides the low frequency scanning clock which drives the multiplexer output selector. This device is used in itrumentation counters, clock displays, digital panel meters, and as a building block for general logic applicatio. TTL Compatible Outputs On Chip Oscillator Cascadable Clock Disable Input Pulse Shaping Permits Very Slow Rise Times on Input Clock Output Latches Master Reset PDIP 16 P SUFFIX CASE 648 SOIC 16 DW SUFFIX CASE 751G MARKING DIAGRAMS 16 1 MC14553BCP AWLYYWW B AWLYYWW MAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 1.) Symbol Parameter Value Unit V DD DC Supply Voltage Range 0.5 to V V in, V out Input or Output Voltage Range (DC or Traient) 0.5 to V DD V A WL, L YY, Y WW, W 1 = Assembly Location = Wafer Lot = Year = Work Week I in I out Input Current (DC or Traient) per Pin Output Current (DC or Traient) per Pin ± ma +20 ma ORDERING INFORMATION Device Package Shipping P D Power Dissipation, per Package (Note 2.) 500 mw T A Ambient Temperature Range 55 to +125 C T stg Storage Temperature Range 65 to +0 C T L Lead Temperature (8 Second Soldering) 260 C 1. Maximum Ratings are those values beyond which damage to the device may occur. 2. Temperature Derating: Plastic P and D/DW Packages: 7.0 mw/c From 65C To 125C MC14553BCP PDIP 16 25/Rail MC14553BDW SOIC 16 47/Rail This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, V in and V out should be cotrained to the range V SS (V in or V out ) V DD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V SS or V DD ). Unused outputs must be left open. Semiconductor Components Industries, LLC, 2001 February, 2001 Rev. 5 1 Publication Order Number: MC14553B/D

2 Figure 1. Block Diagram Inputs TRUTH TABLE Master Reset Clock Disable LE Outputs No Change Advance 0 X 1 X No Change Advance No Change 0 0 X X No Change 0 X X Latched 0 X X 1 Latched 1 X X 0 Q0 = Q1 = Q2 = Q3 = 0 X = Don t Care 2

3 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS ) Characteristic Output Voltage V in = V DD or 0 0 Level Symbol V OL V 1 Level V in = 0 or V DD OH Input Voltage 0 Level (V O = 4.5 or 0.5 Vdc) (V O = 9.0 or 1.0 Vdc) (V O = 13.5 or 1.5 Vdc) (V O = 0.5 or 4.5 Vdc) (V O = 1.0 or 9.0 Vdc) (V O = 1.5 or 13.5 Vdc) 1 Level Output Drive Current (V OH = 4.6 Vdc) Source (V OH = 9.5 Vdc) Pin 3 (V OH = 13.5 Vdc) (V OH = 4.6 Vdc) Source (V OH = 9.5 Vdc) Other (V OH = 13.5 Vdc) Outputs (V OL = 0.4 Vdc) Sink (V OL = 0.5 Vdc) Pin 3 (V OL = 1.5 Vdc) (V OL = 0.4 Vdc) Sink Other (V OL = 0.5 Vdc) Outputs (V OL = 1.5 Vdc) V IL V IH I OH 55C 25C 125C V DD Vdc Min Max Min I OL Typ (Note 3.) Max Min Max Unit Input Current I in ±0.1 ± ±0.1 ±1.0 µadc Input Capacitance (V in = 0) C in 7.5 pf Vdc Vdc Vdc Vdc madc madc madc madc Quiescent Current (Per Package) MR = V DD Total Supply Current (Note 4., 5.) (Dynamic plus Quiescent, Per Package) (C L = 50 pf on all outputs, all buffers switching) I DD I T I T = (0.35 µa/khz) f + I DD I T = (0.85 µa/khz) f + I DD I T = (1.50 µa/khz) f + I DD 3. Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance. 4. The formulas given are for the typical characteristics only at 25C. 5. To calculate total supply current at loads other than 50 pf: I T (C L ) = I T (50 pf) + (C L 50) Vfk where: I T is in µa (per package), C L in pf, V = (V DD V SS ) in volts, f in khz is input frequency, and k = µadc µadc 3

4 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS (Note 6.) (C L = 50 pf, T A = 25C) Characteristic Figure Symbol V DD Min Typ (Note 7.) Max Unit Output Rise and Fall Time t TLH, t THL = (1.5 /pf) C L + 25 t TLH, t THL = (0.75 /pf) C L t TLH, t THL = (0.55 /pf) C L a t TLH, t THL Clock to BCD Out 2a t PLH, t PHL Clock to Overflow 2a t PHL Reset to BCD Out 2b t PHL Clock to Latch Enable Setup Time Master Reset to Latch Enable Setup Time Removal Time Latch Enable to Clock 2b t su 2b t rem Clock Pulse Width 2a t WH(cl) Reset Pulse Width 2b t WH(R) Reset Removal Time t rem Input Clock Frequency 2a f cl Input Clock Rise Time 2b t TLH Disable, MR, Latch Enable Rise and Fall Times Scan Oscillator Frequency (C1 measured in µf) t TLH, t THL 1 f osc No Limit 1.5/C1 4.2/C1 7.0/C1 6. The formulas given are for the typical characteristics only at 25C. 7. Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance MHz µs Hz 4

5 Figure 2. 3 Digit Counter Timing Diagram (Reference Figure 4) Figure 3. Switching Time Test Circuits and Waveforms 5

6 OPERATING CHARACTERISTICS The MC14553B three digit counter, shown in Figure 4, coists of three negative edge triggered BCD counters which are cascaded in a synchronous fashion. A quad latch at the output of each of the three BCD counters permits storage of any given count. The three sets of BCD outputs (active high), after going through the latches, are time division multiplexed, providing one BCD number or digit at a time. Digit select outputs (active low) are provided for display control. All outputs are TTL compatible. An on chip oscillator provides the low frequency scanning clock which drives the multiplexer output selector. The frequency of the oscillator can be controlled externally by a capacitor between pi 3 and 4, or it can be overridden and driven with an external clock at pin 4. Multiple devices can be cascaded using the overflow output, which provides one pulse for every 00 counts. The Master Reset input, when taken high, initializes the three BCD counters and the multiplexer scanning circuit. While Master Reset is high the digit scanner is set to digit one; but all three digit select outputs are disabled to prolong display life, and the scan oscillator is inhibited. The Disable input, when high, prevents the input clock from reaching the counters, while still retaining the last count. A pulse shaping circuit at the clock input permits the counters to continue operating on input pulses with very slow rise times. Information present in the counters when the latch input goes high, will be stored in the latches and will be retained while the latch input is high, independent of other inputs. Information can be recovered from the latches after the counters have been reset if Latch Enable remai high during the entire reset cycle. Figure 4. Expanded Block Diagram 6

7 µ Figure 5. Six Digit Display 7

8 PACKAGE DIMENSIONS H A G B F C S K D 16 PL PDIP 16 P SUFFIX PLASTIC DIP PACKAGE CASE ISSUE R T J L M 8

9 PACKAGE DIMENSIONS D A SOIC 16 DW SUFFIX PLASTIC SOIC PACKAGE CASE 751G 03 ISSUE B 8X H E h X 45 16X B 14X e B A1 A T C L 9

10 Notes

11 Notes 11

12 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, coequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specificatio can and do vary in different applicatio and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any licee under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicatio intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless agait all claims, costs, damages, and expees, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION NORTH AMERICA Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada ONlit@hibbertco.com Fax Respoe Line: or Toll Free USA/Canada N. American Technical Support: Toll Free USA/Canada EUROPE: LDC for ON Semiconductor European Support German Phone: (+1) (Mon Fri 2:30pm to 7:00pm CET) ONlit german@hibbertco.com French Phone: (+1) (Mon Fri 2:00pm to 7:00pm CET) ONlit french@hibbertco.com English Phone: (+1) (Mon Fri 12:00pm to 5:00pm GMT) ONlit@hibbertco.com EUROPEAN TOLL FREE ACCESS*: *Available from Germany, France, Italy, UK, Ireland CENTRAL/SOUTH AMERICA: Spanish Phone: (Mon Fri 8:00am to 5:00pm MST) ONlit spanish@hibbertco.com Toll Free from Mexico: Dial for Access then Dial ASIA/PACIFIC: LDC for ON Semiconductor Asia Support Phone: (Tue Fri 9:00am to 1:00pm, Hong Kong Time) Toll Free from Hong Kong & Singapore: ONlit asia@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center Nishi Gotanda, Shinagawa ku, Tokyo, Japan Phone: r14525@oemi.com ON Semiconductor Website: For additional information, please contact your local Sales Representative. 12 MC14553B/D

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