MC10ELT22, MC100ELT22. 5VНDual TTL to Differential PECL Translator
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1 5VНual TTL to ifferential PECL Translator The MC0ELT/00ELT22 is a dual TTL to differential PECL translator. Because PECL (Positive ECL) levels are used only +5 V and ground are required. The small outline -lead package and the low skew, dual gate design of the ELT22 makes it ideal for applications which require the translation of a clock and a data signal..2 ns Typical Propagation elay < 300 ps Typical Output to Output Skew PNP TTL Inputs for Minimal Loading Flow Through Pinouts Operating Range: V CC = 4.75 V to 5.25 V with GN = 0 V No Internal Input Pulldown Resistors SO- SUFFIX CASE 75 HLT22 MARKING IAGRAMS* KLT22 Q0 Q0 2 7 V CC 0 TSSOP- T SUFFIX CASE 94R HT22 KT22 PECL TTL Q 3 6 H = MC0 K = MC00 A = Assembly Location L = Wafer Lot Y = Year W = Work Week Q 4 5 GN *For additional information, see Application Note AN002/. Figure. Logic iagram and Pinout Assignment PIN ESCRIPTION PIN FUNCTION Qn, Qn PECL ifferential Outputs* n TTL Inputs V CC Positive Supply GN Ground * Output state undetermined when inputs are open. ORERING INFORMATION evice Package Shipping** MC0ELT22 SO- 9 Units/Rail MC0ELT22R2 SO- 20 Tape & Reel MC00ELT22 SO- 9 Units/Rail MC00ELT22R2 SO- 20 Tape & Reel MC0ELT22T TSSOP- 9 Units/Rail MC0ELT22TR2 TSSOP- 20 Tape & Reel MC00ELT22T TSSOP- 9 Units/Rail MC00ELT22TR2 TSSOP- 20 Tape & Reel **For additional tape and reel information, see Brochure BR0/. Semiconductor Components Industries, LLC, 2003 March, Rev. 7 Publication Order Number: MC0ELT22/
2 ATTRIBUTES Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ES Protection Human Body Model Machine Model Value N/A N/A > 2 KV > 200 V Moisture Sensitivity, Indefinite Time Out of rypack (Note ) Level Flammability Rating Oxygen Index: 2 to 34 UL in Transistor Count 5 Meets or exceeds JEEC Spec EIA/JES7 IC Latchup Test. For additional information, see Application Note AN003/. MAXIMUM RATINGS (Note 2) Symbol Parameter Condition Condition 2 Rating Units V CC Positive Power Supply GN = 0 V 7 V V IN Input Voltage GN = 0 V V I V CC 7 V I out Output Current Continuous Surge T A Operating Temperature Range -40 to +5 C T stg Storage Temperature Range -65 to + C JA Thermal Resistance (Junction-to-Ambient) 0 LFPM 0 LFPM SOIC SOIC JC Thermal Resistance (Junction-to-Case) Standard Board SOIC 4 to 44 JA Thermal Resistance (Junction-to-Ambient) 0 LFPM 0 LFPM TSSOP TSSOP JC Thermal Resistance (Junction-to-Case) Standard Board TSSOP 4 to 44 ± 5% T sol Wave Solder <2 to 3 24 C 265 C 2. Maximum Ratings are those values beyond which device damage may occur ma ma 2
3 0ELT SERIES PECL C CHARACTERISTICS V CC = 5.0 V; GN = 0.0 V (Note 3) -40 C 25 C 5 C Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit I CC Power Supply Current ma V OH Output HIGH Voltage (Note 4) mv V OL Output LOW Voltage (Note 4) mv NOTE: evices are designed to meet the C specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 0 lfpm is maintained. 3. Output parameters vary : with V CC. V CC can vary ± 0.25 V. 4. Outputs are terminated through a ohm resistor to V CC - 2 volts. 00ELT SERIES PECL C CHARACTERISTICS V CC = 5.0 V; GN = 0.0 V (Note 5) -40 C 25 C 5 C Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit I CC Power Supply Current ma V OH Output HIGH Voltage (Note 6) mv V OL Output LOW Voltage (Note 6) mv NOTE: evices are designed to meet the C specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 0 lfpm is maintained. 5. Output parameters vary : with V CC. V CC can vary ± 0.25 V. 6. Outputs are terminated through a ohm resistor to V CC - 2 volts. TTL INPUT C CHARACTERISTICS V CC = 4.75 V to 5.25 V; T A = -40 C to 5 C Symbol Characteristic Condition Min Typ Max Unit I IH Input HIGH Current V IN = 2.7 V 20 A I IHH Input HIGH Current V IN = 7.0 V 00 A I IL Input LOW Current V IN = 0.5 V -0.6 ma V IK Input Clamp iode Voltage I IN = - ma -.2 V V IH Input HIGH Voltage 2.0 V V IL Input LOW Voltage 0. V AC CHARACTERISTICS V CC = 4.75 V to 5.25 V; GN= 0.0 V -40 C 25 C 5 C Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit f MAX Maximum Input Frequency 0 MHz t PLH Propagation elay (Note 7).5 V to % ns t PHL Propagation elay (Note 7).5 V to % ns t skew Within-evice Skew (Note ) evice-to-evice Skew (Note 9) ps t JITTER Random Clock Jitter (RMS) 0.5 ps t r /t f Output Rise/Fall Time (20-0%) ns 7. Specifications for standard TTL input signal.. Skew is measured between outputs under identical transitions and conditions on any one device. 9. evice-to-evice Skew for identical transitions at identical V CC levels. 3
4 river evice Q Q Receiver evice V TT V TT = V CC V Figure 2. Typical Termination for Output river and evice Evaluation (See Application Note AN020 - Termination of ECL Logic evices.) Resource Reference of Application Notes AN404 - ECLinPS Circuit Performance at Non-Standard V IH Levels AN405 - ECL Clock istribution Techniques AN406 - esigning with PECL (ECL at +5.0 V) AN3 - ECLinPS I/O SPICE Modeling Kit AN4 - Metastability and the ECLinPS Family AN560 - Low Voltage ECLinPS SPICE Modeling Kit AN56 - Interfacing Between LVS and ECL AN596 - ECLinPS Lite Translator ELT Family SPICE I/O Model Kit AN6 - Using Wire-OR Ties in ECLinPS esigns AN672 - The ECL Translator Guide AN00 - Odd Number Counters esign AN002 - Marking and ate Codes AN020 - Termination of ECL Logic evices AN090 - AC Characteristics of ECL evices 4
5 PACKAGE IMENSIONS SO- SUFFIX PLASTIC SOIC PACKAGE CASE ISSUE AA -X- -Y- B A 5 4 S 0.25 (0.00) M Y M K NOTES:. IMENSIONING AN TOLERANCING PER ANSI Y4.5M, CONTROLLING IMENSION: MILLIMETER. 3. IMENSION A AN B O NOT INCLUE MOL PROTRUSION. 4. MAXIMUM MOL PROTRUSION 0.5 (0.006) PER SIE. 5. IMENSION OES NOT INCLUE AMBAR PROTRUSION. ALLOWABLE AMBAR PROTRUSION SHALL BE 0.27 (0.005) TOTAL IN EXCESS OF THE IMENSION AT MAXIMUM MATERIAL CONITION THRU ARE OBSOLETE. NEW STANAR IS Z- H G C 0.25 (0.00) M Z Y S X S SEATING PLANE 0.0 (0.004) N X 45 M J MILLIMETERS INCHES IM MIN MAX MIN MAX A B C G.27 BSC 0.0 BSC H J K M 0 0 N S
6 PACKAGE IMENSIONS TSSOP- T SUFFIX PLASTIC TSSOP PACKAGE CASE 94R-02 ISSUE A 0.5 (0.006) T 0.5 (0.006) T L U U 0.0 (0.004) SEATING PLANE S 2X L/2 PIN IENT S C 5 x K REF (0.004) M T U S V S G ETAIL E ETAIL E F 0.25 (0.00) M B -U- -T- A -V- -W- NOTES:. IMENSIONS AN TOLERANCING PER ASME Y4.5M, CONTROLLING IMENSION: MILLIMETER. 3. IMENSION A OES NOT INCLUE MOL FLASH. PROTRUSIONS OR GATE BURRS. MOL FLASH OR GATE BURRS SHALL NOT EXCEE 0.5 (0.006) PER SIE. 4. IMENSION B OES NOT INCLUE INTERLEA FLASH OR PROTRUSION. INTERLEA FLASH OR PROTRUSION SHALL NOT EXCEE 0.25 (0.00) PER SIE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. IMENSION A AN B ARE TO BE ETERMINE AT ATUM PLANE -W-. MILLIMETERS INCHES IM MIN MAX MIN MAX A B C F G 0.65 BSC BSC K L 4.90 BSC 0.93 BSC M ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORERING INFORMATION Literature Fulfillment: Literature istribution Center for ON Semiconductor P.O. Box 563, enver, Colorado 027 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada ONlit@hibbertco.com N. American Technical Support: Toll Free USA/Canada JAPAN: ON Semiconductor, Japan Customer Focus Center 2-9- Kamimeguro, Meguro-ku, Tokyo, Japan Phone: ON Semiconductor Website: For additional information, please contact your local Sales Representative. 6 MC0ELT22/
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3.3 V Xtal or LVTTL/LVCMOS Input 2:1 MUX to 1:4 LVPECL Fanout Buffer Description The NB3N853531E is a low skew 3.3 V supply 1:4 clock distribution fanout buffer. An input MUX selects either a Fundamental
MJD44H11 (NPN) MJD45H11 (PNP) Complementary Power Transistors. DPAK For Surface Mount Applications
MJDH (NPN) MJD5H (PNP) Complementary Power Transistors For Surface Mount Applications Designed for general purpose power and switching such as output or driver stages in applications such as switching
MC10H603, MC100H Bit Latch ECL to TTL Translator
9 Bit atch EC to TT Tralator escription The MC10/100603 is a 9 bit, dual supply EC to TT tralator. evices in the ON Semiconductor 9 bit tralator series utilize the 28 lead PCC for optimal power pinning,
MARKING DIAGRAMS LOGIC DIAGRAM ORDERING INFORMATION DIP PIN ASSIGNMENT CDIP 16 L SUFFIX CASE 620 MC10124L AWLYYWW
The MC024 is a quad translator for interfacing data and control signals between a saturated logic section and the MECL section of digital systems. The MC024 has TTL compatible inputs, and MECL complementary
NB4L V / 3.3V Differential LVPECL 2x2 Clock Switch and Low Skew Fanout Buffer
2.5V / 3.3V Differential LVPECL 2x2 Clock Switch and Low Skew Fanout Buffer Description The NB4L6254 is a differential 2x2 clock switch and drives precisely aligned clock signals through its LVPECL fanout
NB2879A. Low Power, Reduced EMI Clock Synthesizer
Low Power, Reduced EMI Clock Synthesizer The NB2879A is a versatile spread spectrum frequency modulator designed specifically for a wide range of clock frequencies. The NB2879A reduces ElectroMagnetic
MC10E V, 5V Dual ECL Output Comparator with Latch
5V, 5V Dual ECL Output Comparator with Latch The MC10E1651 is fabricated using ON Semiconductor s advanced MOSAIC III process. The MC10E1651 incorporates a fixed level of input hysteresis as well as output
P SUFFIX CASE 646 Single Supply Split Supplies SO-14 D SUFFIX CASE 751A PIN CONNECTIONS
Dual Operational Amplifier and Dual Comparator The MC05 contains two differential-input operational amplifiers and two comparators, each set capable of single supply operation. This operational amplifier-comparator
EMF5XV6T5G. Power Management, Dual Transistors. NPN Silicon Surface Mount Transistors with Monolithic Bias Resistor Network
Preferred Devices Power Management, Dual Transistors NPN Silicon Surface Mount Transistors with Monolithic Bias Resistor Network Features Simplifies Circuit Design Reduces Board Space Reduces Component
EMC5DXV5T1, EMC5DXV5T5
EMC5DXV5T, EMC5DXV5T5 Preferred Devices Dual Common Base Collector Bias Resistor Transistors NPN and PNP Silicon Surface Mount Transistors with Monolithic Bias Resistor Network The BRT (Bias Resistor Transistor)
MBRD835LT4G. SWITCHMODE Power Rectifier. DPAK Surface Mount Package SCHOTTKY BARRIER RECTIFIER 8.0 AMPERES, 35 VOLTS
MBRD8L Preferred Device SWITCHMODE Power Rectifier Surface Mount Package This SWITCHMODE power rectifier which uses the Schottky Barrier principle with a proprietary barrier metal, is designed for use
The MC10109 is a dual 4 5 input OR/NOR gate. P D = 30 mw typ/gate (No Load) t pd = 2.0 ns typ t r, t f = 2.0 ns typ (20% 80%)
The MC10109 is a dual 5 input OR/NOR gate. P D = 0 mw typ/gate (No Load) t pd =.0 ns typ t r, t f =.0 ns typ (0% 0%) LOGIC DIAGRAM MARKING DIAGRAMS CDIP 16 L SUFFIX CASE 60 PDIP 16 P SUFFIX CASE 6 PLCC
NCP304A. Voltage Detector Series
Voltage Detector Series The NCP0A is a second generation ultralow current voltage detector. This device is specifically designed for use as a reset controller in portable microprocessor based systems where
MC100EPT V LVTTL/LVCMOS to LVPECL Translator
MCEPT622 3.3V VTT/VCMOS to VPEC Translator Description The MCEPT622 is a 0 Bit VTT/VCMOS to VPEC translator. Because VPEC (Positive EC) levels are used only +3.3 V and ground are required. The device has
P3P85R01A. 3.3V, 75 MHz to 200 MHz LVCMOS TIMING SAFE Peak EMI Reduction Device
3.3V, 75 MHz to 200 MHz LVCMOS TIMING SAFE Peak EMI Reduction Device Functional Description P3P85R0A is a versatile, 3.3 V, LVCMOS, wide frequency range, TIMING SAFE Peak EMI reduction device. TIMING SAFE
UMC2NT1, UMC3NT1, UMC5NT1
UMCNT, UMC3NT, UMC5NT Preferred Devices Dual Common BaseCollector Bias Resistor Transistors NPN and PNP Silicon Surface Mount Transistors with Monolithic Bias Resistor Network The Bias Resistor Transistor
PCS2P2309/D. 3.3V 1:9 Clock Buffer. Functional Description. Features. Block Diagram
3.3V 1:9 Clock Buffer Features One-Input to Nine-Output Buffer/Driver Buffers all frequencies from DC to 133.33MHz Low power consumption for mobile applications Less than 32mA at 66.6MHz with unloaded
LM339S, LM2901S. Single Supply Quad Comparators
LM339S, LM290S Single Supply Quad Comparators These comparators are designed for use in level detection, low level sensing and memory applications in consumer and industrial electronic applications. Features
NCN Differential Channel 1:2 Mux/Demux Switch for PCI Express Gen3
4-Differential Channel 1:2 Mux/Demux Switch for PCI Express Gen3 The NCN3411 is a 4 Channel differential SPDT switch designed to route PCI Express Gen3 signals. When used in a PCI Express application,
BAV70DXV6T1, BAV70DXV6T5 Preferred Device. Monolithic Dual Switching Diode Common Cathode. Lead-Free Solder Plating.
BAV70DXV6T1, BAV70DXV6T5 Preferred Device Monolithic Dual Switching Diode Common Cathode LeadFree Solder Plating MAXIMUM RATINGS (EACH DIODE) Rating Symbol Value Unit Reverse Voltage V R 70 Vdc Forward
MC100EPT V LVTTL/LVCMOS to LVPECL Translator Description The MC100EPT622 is a 10- Bit LVTTL/LVCMOS to LVPECL translator. Because LVPECL (Positiv
3.3V VTT/VCMOS to VPEC Translator Description The is a 0- Bit VTT/VCMOS to VPEC translator. Because VPEC (Positive EC) levels are used only +3.3 V and ground are required. The device has an OR- ed enable
MUN5211DW1T1 Series. NPN Silicon Surface Mount Transistors with Monolithic Bias Resistor Network
MUNDWT Series Preferred Devices Dual Bias Resistor Transistors NPN Silicon Surface Mount Transistors with Monolithic Bias Resistor Network The BRT (Bias Resistor Transistor) contains a single transistor
MJD44H11 (NPN) MJD45H11 (PNP)
MJDH (NPN) MJD5H (PNP) Preferred Device Complementary Power Transistors For Surface Mount Applications Designed for general purpose power and switching such as output or driver stages in applications such
MJD6039, NJVMJD6039T4G. Darlington Power Transistors. DPAK For Surface Mount Applications SILICON POWER TRANSISTORS 4 AMPERES, 80 VOLTS, 20 WATTS
Darlington Power Transistors For Surface Mount Applications Designed for general purpose power and switching such as output or driver stages in applications such as switching regulators, convertors, and
MC10ELT24, MC100ELT24. 5V TTL to Differential ECL Translator
M0ELT24, M00ELT24 5V TTL to ifferential EL Translator escription The M0ELT/00ELT24 is a TTL to differential EL translator. Because EL levels are used a +5 V, 5.2 V (or 4.5 V) and ground are required. The
NTS2101P. Power MOSFET. 8.0 V, 1.4 A, Single P Channel, SC 70
NTS11P Power MOSFET 8. V, 1.4 A, Single P Channel, SC 7 Features Leading Trench Technology for Low R DS(on) Extending Battery Life 1.8 V Rated for Low Voltage Gate Drive SC 7 Surface Mount for Small Footprint
NCV1009ZG. 2.5 Volt Reference
V9 2.5 Volt Reference The V9 is a precision trimmed 2.5 V ±5. mv shunt regulator diode. The low dynamic impedance and wide operating current range enhances its versatility. The tight reference tolerance
NB3N106K. 3.3V Differential 1:6 Fanout Clock Driver with HCSL Outputs
3.3V Differential 1:6 Fanout Clock Driver with HCSL Outputs Description The is a differential 1:6 Clock fanout buffer with High speed Current Steering Logic (HCSL) outputs optimized for ultra low propagation
NSQA6V8AW5T2 Series Transient Voltage Suppressor
Transient Voltage Suppressor ESD Protection Diode with Low Clamping Voltage This integrated transient voltage suppressor device (TVS) is designed for applications requiring transient overvoltage protection.
MC10EP142, MC100EP V / 5 VНECL 9 Bit Shift Register
MC0EP42, MCEP42 3.3 V / 5 VНECL Bit Shift Register The MC0EP/EP42 is a bit shift register, designed with byte-parity applications in mind. The MC0/EP42 is capable of performing serial/parallel data into
MC10E V, -5V Dual ECL Output Comparator with Latch
5V, -5V Dual ECL Output Comparator with Latch The MC10E1652 is fabricated using ON Semiconductor s advanced MOSAIC III process and is output compatible with 10H logic devices. In addition, the device is
NTMS5838NL. Power MOSFET 40 V, 7.5 A, 20 m
Power MOSFET V, 7.5 A, 2 m Features Low R DS(on) Low Capacitance Optimized Gate Charge These Devices are Pb Free, Halogen Free/BFR Free and are RoHS Compliant MAXIMUM RATINGS ( unless otherwise stated)
LOW POWER SCHOTTKY. GUARANTEED OPERATING RANGES ORDERING INFORMATION
The SN74LS298 is a Quad 2-Port Register. It is the logical equivalent of a quad 2-input multiplexer followed by a quad 4-bit edge-triggered register. A Common Select input selects between two 4-bit input
NSV2029M3T5G. PNP Silicon General Purpose Amplifier Transistor PNP GENERAL PURPOSE AMPLIFIER TRANSISTORS SURFACE MOUNT
PNP Silicon General Purpose Amplifier Transistor This PNP transistor is designed for general purpose amplifier applications. This device is housed in the package which is designed for low power surface
NTTFS5116PLTWG. Power MOSFET 60 V, 20 A, 52 m. Low R DS(on) Fast Switching These Devices are Pb Free and are RoHS Compliant
Power MOSFET 6 V, 2 A, 52 m Features Low R DS(on) Fast Switching These Devices are Pb Free and are RoHS Compliant Applications Load Switches DC Motor Control DC DC Conversion MAXIMUM RATINGS ( unless otherwise
NTMS4801NR2G. Power MOSFET 30 V, 12 A, N Channel, SO 8
NTMSN Power MOSFET 3 V, A, N Channel, SO Features Low R DS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses This is a Pb Free
MUN5311DW1T1G Series.
MUNDWTG Series Preferred Devices Dual Bias Resistor Transistors NPN and PNP Silicon Surface Mount Transistors with Monolithic Bias Resistor Network The Bias Resistor Transistor (BRT) contains a single
NTMS5835NL. Power MOSFET 40 V, 12 A, 10 m
Power MOSFET V, 2 A, m Features Low R DS(on) Low Capacitance Optimized Gate Charge These Devices are Pb Free, Halogen Free/BFR Free and are RoHS Compliant MAXIMUM RATINGS ( unless otherwise stated) Parameter
MMBZ15VDLT3G MMBZ27VCLT1G SZMMBZ15VDLT3G. SZMMBZ27VCLT1G 40 Watt Peak Power Zener Transient Voltage Suppressors
MMBZ15VDLT1G, MMBZ27VCLT1G, SZMMBZ15VDLT1G, SZMMBZ27VCLT1G 40 Watt Peak Power Zener Transient Voltage Suppressors Dual Common Cathode Zeners for ESD Protection These dual monolithic silicon zener diodes