NBXSBA024, NBXSBB024, NBXMBB V / 3.3 V, MHz LVPECL Clock Oscillator
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1 NBXSBA0, NBXSBB0, NBXMBB0.5 V /. V, 6.08 MHz LVPECL Clock Oscillator The single frequency, crystal oscillator (XO) is designed to meet today s requirements for.5 V /. V LVPECL clock generation applications. The device uses a high Q fundamental crystal and Phase Lock Loop (PLL) multiplier to provide 6.08 MHz, ultra low jitter and phase noise LVPECL differential output. This device is a member of ON Semiconductor s PureEdge clock family that provides accurate and precision clock solutions. Frequency stability options available as either ±50 PPM NBXSBA0 (Industrial Temperature Range) or ±0 PPM NBXSBB0/NBXMBB0 (Commercial Temperature Range). Available in 5 mm x 7 mm SM (CLCC) package on 16 mm tape and reel in quantities of 1,000 and 100. Features LVPECL ifferential Output Uses High Q Fundamental Mode Crystal and PLL Multiplier Ultra Low Jitter and Phase Noise 0.5 ps (1 khz 0 MHz) Output Frequency 6.08 MHz Hermetically Sealed Ceramic SM Package RoHS Compliant Operating Range:.5 V ±5% or. V ±10% Total Frequency Stability ±0 PPM; ±50 PPM This is a Pb Free evice Applications SONET Line Card Networking Optical Systems V 6 5 Crystal PLL Clock Multiplier 1 OE NC GN NC* OE* *NBXMBB0 device pinout Figure 1. Simplified Logic iagram 6 PIN CLCC LN SUFFIX CASE 88AB ORERING INFORMATION evice Package Shipping NBXSBA0LN1TAG MARKING IAGRAM NBXSBx0 = Specific evice Code x = A or B y = S or M = NBXSBA0 (±50 PPM) = NBXSBB0 (±0 PPM) = Output Frequency (MHz) AA = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb Free Package NBXSBB0LN1TAG* NBXSBA0LNHTAG NBXMBB0LN1TAG NBXMBB0LNHTAG NBXyBx AAWLYYWWG 1000/ 1000/ 100/ 1000/ 100/ For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BR8011/. * Please contact sales office for availability Semiconductor Components Industries, LLC, 01 July, 01 Rev. 5 1 Publication Order Number: NBXSBA0/
2 OE 1 6 V NC 1 6 V NC 5 OE 5 GN GN NBXSxxxxx NBXMxxxxx Figure. Pin Connections (Top View) Table 1. PIN ESCRIPTION Pin No. Symbol I/O escription 1 OE/NC* LVTTL/LVCMOS Output Enable Pin. When left floating pin defaults to logic HIGH and output is active. ÁÁ Control InputÁÁ See OE pin description Table. ÁÁÁÁ NC/OE* N/A ÁÁ No Connect. ÁÁÁÁ GN Power SupplyÁÁ Ground 0 V ÁÁÁÁ LVPECL OutputÁÁ Non Inverted Clock Output. Typically loaded with 50 receiver termination resistor to V TT = V V. 5 LVPECL Output Inverted Clock Output. Typically loaded with 50 receiver termination resistor to V TT = V V. 6 ÁÁÁ Power SupplyÁÁ Positive power supply voltage. Voltage should not exceed.5 V ±5% or. V ±10%. V *NBXMBA0 device pinout Table. OUTPUT ENABLE TRI STATE FUNCTION OE Pin Output Pins Open Active HIGH Level Active LOW Level High Z Table. ATTRIBUTES Characteristic Internal efault State Resistor ES Protection Human Body Model Machine Model Value 170 k kv 00 V Meets or Exceeds JEEC Standard EIA/JES78 IC Latchup Test 1. For additional Moisture Sensitivity information, refer to Application Note AN800/. Table. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition Rating Units V Positive Power Supply GN = 0 V.6 V I out LVPECL Output Current Continuous Surge T A Operating Temperature Range 0 to +85 C T stg Storage Temperature Range 55 to +10 C T sol Wave Solder See Figure 5 60 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability ma
3 Table 5. C CHARACTERISTICS (V =.5 V ± 5%;. V ± 10%, GN = 0 V, T A = 0 C to +85 C) (Note ) Symbol Characteristic Conditions Min. Typ. Max. Units I Power Supply Current ma V IH OE Input HIGH Voltage 000 V mv V IL OE Input LOW Voltage GN mv I IH Input HIGH Current OE A I IL Input LOW Current OE A V OH Output HIGH Voltage V 1195 V 95 mv V OL Output LOW Voltage V 195 V 1600 mv V OUTPP Output Voltage Amplitude 700 mv NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit values are applied individually under normal operating conditions and not valid simultaneously.. Measurement taken with outputs terminated with 50 to V.0 V. See Figure. Table 6. AC CHARACTERISTICS (V =.5 V ± 5%;. V ± 10%, GN = 0 V, T A = 0 C to +85 C) (Note ) Symbol Characteristic Conditions Min. Typ. Max. Units f OUT Output Clock Frequency 6.08 MHz f NOISE Frequency Stability NBXSBB0, NBXMBB0 NBXSBA0 Phase Noise Performance f out = 6.08 MHz (See Figure ) 0 C to +70 C 0 C to +85 C (Note ) ±0 ±50 ppm 100 Hz of Carrier 88 dbc/hz 1 khz of Carrier 108 dbc/hz 10 khz of Carrier 115 dbc/hz 100 khz of Carrier 116 dbc/hz 1 MHz of Carrier 1 dbc/hz 10 MHz of Carrier 19 dbc/hz t jit ( ) RMS Phase Jitter 1 khz to 0 MHz ps t jitter Cycle to Cycle, RMS 1000 Cycles ps Cycle to Cycle, Peak to Peak 1000 Cycles 15 0 ps Period, RMS 10,000 Cycles 1 ps Period, Peak to Peak 10,000 Cycles 10 0 ps t OE/O Output Enable/isable Time 00 ns t UTY_CYCLE Output Clock uty Cycle (Measured at Cross Point) % t R Output Rise Time (0% and 80%) ps t F Output Fall Time (80% and 0%) ps t start Start up Time 1 5 ms Aging 1 st Year ppm Every Year After 1 st 1 ppm NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit values are applied individually under normal operating conditions and not valid simultaneously.. Measurement taken with outputs terminated with 50 to V.0 V. See Figure.. Parameter guarantee 10 years aging. Includes initial stability at 5 C, shock, vibration, and first year aging.
4 Figure. Typical Phase Noise Plot Table 7. RELIABILITY COMPLIANCE Parameter Standard Method Shock MIL ST 8, Method 00, Condition B Solderability MIL ST 8, Method 00 Vibration MIL ST 8, Method 007, Condition A Solvent Resistance MIL ST 0, Method 15 Á Thermal Shock Environment ÁÁÁÁ MIL ST 8, Method 1011, Condition A Moisture Level Sensitivity Environment MSL1 60 C per IPC/JEEC J ST 00
5 NBXSBA0 river evice Q Q Z o = 50 Z o = 50 Receiver evice V TT V TT = V.0 V Figure. Typical Termination for Output river and evice Evaluation (See Application Note AN800/ Termination of ECL Logic evices.) Temperature ( C) temp. 60 C 0 0 sec. max. peak C/sec. max. 6 C/sec. max pre heat ramp up cooling reflow Time sec sec. Figure 5. Recommended Reflow Soldering Profile 5
6 PACKAGE IMENSIONS 6 PIN CLCC, 7x5,.5P CASE 88AB 01 ISSUE C X 0.15 C 1 A B NOTES: 1. IMENSIONING AN TOLERANCING PER ASME Y1.5M, CONTROLLING IMENSION: MILLIMETERS. TERMINAL 1 INICATOR 0.10 C A1 E A TOP VIEW SIE VIEW H E1 A A E C SEATING PLANE MILLIMETERS IM MIN NOM MAX A A REF A 0.6 REF A b BSC BSC E 5.00 BSC E E E.9 BSC e.5 BSC H 1.80 REF L R 0.70 REF SOLERING FOOTPRINT* 1 e R E 6X C A B 0.05 C 6X b 6 5 BOTTOM VIEW 6X L.5 PITCH 6X 1.50 IMENSION: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLERRM/. PureEdge is a trademark of Semiconductor Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORERING INFORMATION LITERATURE FULFILLMENT: Literature istribution Center for ON Semiconductor P.O. Box 516, enver, Colorado 8017 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative NBXSBA0/
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High Voltage Transistor PNP Silicon Features These Devices are Pb Free, Halogen Free/BFR Free and are RoHS Compliant MAXIMUM RATINGS (T C = 25 C unless otherwise noted) Rating Symbol Value Unit Collector-Emitter
MURS320T3G, SURS8320T3G, MURS340T3G, SURS8340T3G, MURS360T3G, SURS8360T3G. Surface Mount Ultrafast Power Rectifiers
MURS32T3G, SURS832T3G, MURS34T3G, SURS834T3G, MURS36T3G, Surface Mount Ultrafast Power Rectifiers This series employs the state of the art epitaxial construction with oxide passivation and metal overlay
NTD5865NL. N-Channel Power MOSFET 60 V, 46 A, 16 m
N-Channel Power MOSFET 6 V, 6 A, 6 m Features Low Gate Charge Fast Switching High Current Capability % Avalanche Tested These Devices are Pb Free, Halogen Free and are RoHS Compliant MAXIMUM RATINGS (
NB7V52M. 1.8V / 2.5V Differential D Flip-Flop w/ Reset and CML Outputs. Multi Level Inputs w/ Internal Termination
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LOGIC DIAGRAM AND PINOUT ASSIGNMENT V CC TTL PECL 3. MARKING DIAGRAMS* ORDERING INFORMATION PIN DESCRIPTION HLT20 ALYW KLT20 ALYW
The MC0ELT/00ELT20 is a TTL to differential PECL translator. Because PECL (Positive ECL) levels are used, only +5 V and ground are required. The small outline -lead package and the single gate of the ELT20
MMSD301T1G SMMSD301T1G, MMSD701T1G SMMSD701T1G, SOD-123 Schottky Barrier Diodes
MMSD3TG, SMMSD3TG, MMSD7TG, SMMSD7TG, SOD-3 Schottky Barrier Diodes The MMSD3T, and MMSD7T devices are spinoffs of our popular MMBD3LT, and MMBD7LT SOT3 devices. They are designed for highefficiency UHF
NTHD4502NT1G. Power MOSFET. 30 V, 3.9 A, Dual N Channel ChipFET
NTHDN Power MOSFET V,.9 A, Dual N Channel ChipFET Features Planar Technology Device Offers Low R DS(on) and Fast Switching Speed Leadless ChipFET Package has % Smaller Footprint than TSOP. Ideal Device
NTHS2101P. Power MOSFET. 8.0 V, 7.5 A P Channel ChipFET
NTHSP Power MOSFET. V,. A P Channel ChipFET Features Offers an Ultra Low R S(on) Solution in the ChipFET Package Miniature ChipFET Package % Smaller Footprint than TSOP making it an Ideal evice for Applications
NB3N108K. 3.3V Differential 1:8 Fanout Clock Data Driver with HCSL Outputs
3.3V Differential 1:8 Fanout Clock Data with HCSL Outputs Description The is a differential 1:8 Clock fanout buffer with High speed Current Steering Logic (HCSL) outputs optimized for ultra low propagation
MMSZ5221BT1 Series. Zener Voltage Regulators. 500 mw SOD 123 Surface Mount
MMSZ5BT Series Preferred Device Zener Voltage Regulators 5 mw SOD 3 Surface Mount Three complete series of Zener diodes are offered in the convenient, surface mount plastic SOD 3 package. These devices
MURS120T3G Series, SURS8120T3G Series. Surface Mount Ultrafast Power Rectifiers
MURS12T3G Series, SURS812T3G Series Surface Mount Ultrafast Power Rectifiers MURS5T3G, MURS1T3G, MURS115T3G, MURS12T3G, MURS14T3G, MURS16T3G, SURS85T3G, SURS81T3G, SURS8115T3G, SURS812T3G, SURS814T3G,
NB3N853531E. 3.3 V Xtal or LVTTL/LVCMOS Input 2:1 MUX to 1:4 LVPECL Fanout Buffer
3.3 V Xtal or LVTTL/LVCMOS Input 2:1 MUX to 1:4 LVPECL Fanout Buffer Description The NB3N853531E is a low skew 3.3 V supply 1:4 clock distribution fanout buffer. An input MUX selects either a Fundamental
NLHV18T Channel Level Shifter
18-Channel Level Shifter The NLHV18T3244 is an 18 channel level translator designed for high voltage level shifting applications such as displays. The 18 channels are divided into twelve and two three
NUF6400MNTBG. 6-Channel EMI Filter with Integrated ESD Protection
6-Channel EMI Filter with Integrated ESD Protection The NUF64MU is a six channel (C R C) Pi style EMI filter array with integrated ESD protection. Its typical component values of R = and C = 5 pf deliver
P2042A LCD Panel EMI Reduction IC
LCD Panel EMI Reduction IC Features FCC approved method of EMI attenuation Provides up to 15dB of EMI suppression Generates a low EMI spread spectrum clock of the input frequency Input frequency range:
NVTFS4C13N. Power MOSFET. 30 V, 9.4 m, 40 A, Single N Channel, 8FL Features
NVTFS4C3N Power MOSFET 3 V, 9.4 m, 4 A, Single N Channel, 8FL Features Low R DS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses
NCP A, Low Dropout Linear Regulator with Enhanced ESD Protection
3.0 A, Low Dropout Linear Regulator with Enhanced ESD Protection The NCP5667 is a high performance, low dropout linear regulator designed for high power applications that require up to 3.0 A current. A
NTJS4405N, NVJS4405N. Small Signal MOSFET. 25 V, 1.2 A, Single, N Channel, SC 88
NTJSN, NVJSN Small Signal MOSFET V,. A, Single, N Channel, SC 88 Features Advance Planar Technology for Fast Switching, Low R DS(on) Higher Efficiency Extending Battery Life AEC Q Qualified and PPAP Capable
NCP5504, NCV ma Dual Output Low Dropout Linear Regulator
25 ma Dual Output Low Dropout Linear Regulator The NCP554/NCV554 are dual output low dropout linear regulators with 2.% accuracy over the operating temperature range. They feature a fixed output voltage
NTLUD3A260PZ. Power MOSFET 20 V, 2.1 A, Cool Dual P Channel, ESD, 1.6x1.6x0.55 mm UDFN Package
NTLUDAPZ Power MOSFET V,. A, Cool Dual P Channel, ESD,.x.x. mm UDFN Package Features UDFN Package with Exposed Drain Pads for Excellent Thermal Conduction Low Profile UDFN.x.x. mm for Board Space Saving
ASM3P2669/D. Peak EMI Reducing Solution. Features. Product Description. Application. Block Diagram
Peak EMI Reducing Solution Features Generates a X low EMI spread spectrum clock of the input frequency. Integrated loop filter components. Operates with a 3.3V / 2.5V supply. Operating current less than
NTA4001N, NVA4001N. Small Signal MOSFET. 20 V, 238 ma, Single, N Channel, Gate ESD Protection, SC 75
Small Signal MOSFET V, 8 ma, Single, N Channel, Gate ESD Protection, SC 75 Features Low Gate Charge for Fast Switching Small.6 x.6 mm Footprint ESD Protected Gate AEC Q Qualified and PPAP Capable NVA4N
NDD60N360U1 35G. N-Channel Power MOSFET. 100% Avalanche Tested These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS Compliant.
NDDN3U N-Channel Power MOSFET V, 3 m Features % Avalanche Tested These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS Compliant ABSOLUTE MAXIMUM RATINGS ( unless otherwise noted) V (BR)DSS R DS(ON)
NLAS7222B, NLAS7222C. High-Speed USB 2.0 (480 Mbps) DPDT Switches
High-Speed USB 2.0 (480 Mbps) DPDT Switches ON Semiconductor s NLAS7222B and NLAS7222C are part of a series of analog switch circuits that are produced using the company s advanced sub micron CMOS technology,
NTD5867NL. N-Channel Power MOSFET 60 V, 20 A, 39 m
N-Channel Power MOSFET 6 V, A, 39 m Features Low R DS(on) High Current Capability % Avalanche Tested These Devices are Pb Free, Halogen Free/BFR Free and are RoHS Compliant MAXIMUM RATINGS ( unless otherwise
MMBTA06W, SMMBTA06W, Driver Transistor. NPN Silicon. Moisture Sensitivity Level: 1 ESD Rating: Human Body Model 4 kv ESD Rating: Machine Model 400 V
Driver Transistor NPN Silicon Moisture Sensitivity Level: 1 ESD Rating: Human Body Model 4 kv ESD Rating: Machine Model 400 V Features S Prefix for Automotive and Other Applications Requiring Unique Site
NB6N11S. 3.3 V 1:2 AnyLevel Input to LVDS Fanout Buffer / Translator
NB6NS 3.3 V :2 AnyLevel Input to LVS Fanout Buffer / Translator escription The NB6NS is a differential :2 Clock or ata Receiver and will accept AnyLevel input signals: LVPECL, CML, LVCMOS, LVTTL, or LVS.
NTLUS3A90PZ. Power MOSFET 20 V, 5.0 A, Cool Single P Channel, ESD, 1.6x1.6x0.55 mm UDFN Package
NTLUS3A9PZ Power MOSFET V, 5. A, Cool Single P Channel, ESD,.x.x.55 mm UDFN Package Features UDFN Package with Exposed Drain Pads for Excellent Thermal Conduction Low Profile UDFN.x.x.55 mm for Board Space
NSBC114EDP6T5G Series. Dual Digital Transistors (BRT) NPN Silicon Surface Mount Transistors with Monolithic Bias Resistor Network
Preferred Devices Dual Digital Transistors (BRT) NPN Silicon Surface Mount Transistors with Monolithic Bias Resistor Network This new series of digital transistors is designed to replace a single device
NVD5117PLT4G. Power MOSFET 60 V, 16 m, 61 A, Single P Channel
Power MOSFET 6 V, 16 m, 61 A, Single P Channel Features Low R DS(on) to Minimize Conduction Losses High Current Capability Avalanche Energy Specified AEC Q11 Qualified These Devices are Pb Free, Halogen
MUR405, MUR410, MUR415, MUR420, MUR440, MUR460. SWITCHMODE Power Rectifiers ULTRAFAST RECTIFIERS 4.0 AMPERES, VOLTS
MUR45, MUR4, MUR415, MUR42, MUR44, MUR46 SWITCHMODE Power Rectifiers These state of the art devices are a series designed for use in switching power supplies, inverters and as free wheeling diodes. Features
NB3N106K. 3.3V Differential 1:6 Fanout Clock Driver with HCSL Outputs
3.3V Differential 1:6 Fanout Clock Driver with HCSL Outputs Description The is a differential 1:6 Clock fanout buffer with High speed Current Steering Logic (HCSL) outputs optimized for ultra low propagation
NTS4172NT1G. Power MOSFET. 30 V, 1.7 A, Single N Channel, SC 70. Low On Resistance Low Gate Threshold Voltage Halide Free This is a Pb Free Device
Power MOSFET V,.7 A, Single N Channel, SC 7 Features Low On Resistance Low Gate Threshold Voltage Halide Free This is a Pb Free Device V (BR)DSS R DS(on) MAX I D MAX Applications Low Side Load Switch DC
MUN5332DW1, NSBC143EPDXV6, NSBC143EPDP6. Complementary Bias Resistor Transistors R1 = 4.7 k, R2 = 4.7 k
MUN5DW, NSBCEPDXV6, NSBCEPDP6 Complementary Bias Resistor Transistors R =.7 k, R =.7 k NPN and PNP Transistors with Monolithic Bias Resistor Network () PIN CONNECTIONS () () This series of digital transistors
NTLUF4189NZ Power MOSFET and Schottky Diode
NTLUF89NZ Power MOSFET and Schottky Diode V, N Channel with. A Schottky Barrier Diode,. x. x. mm Cool Package Features Low Qg and Capacitance to Minimize Switching Losses Low Profile UDFN.x. mm for Board
MBRA320T3G Surface Mount Schottky Power Rectifier
Surface Mount Schottky Power Rectifier Power Surface Mount Package Employing the Schottky Barrier principle in a large area metal to silicon power diode. State of the art geometry features epitaxial construction