NB7L32M. 2.5V/3.3V, 14GHz 2 Clock Divider w/cml Output and Internal Termination

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1 2.5V/3.3V, 14GHz 2 Clock ivider w/cml Output and Internal Termination escription The NB7L32M is an integrated 2 divider with differential clock inputs and asynchronous reset. ifferential clock inputs incorporate internal termination resistors and accept LVPECL (Positive ECL), CML, or LVS. The high frequency reset pin is asserted on the rising edge. Upon power up, the internal flip flops will attain a random state; the reset allows for the synchronization of multiple NB7L32M s in a system. The differential 16 ma CML output provides matching internal termination which guarantees 400 mv output swing when externally receiver terminated to (See Figure 15). The device is housed in a small 3x3 mm 16 pin FN package. Features Maximum Input Clock Frequency 14 GHz Typical ps Max Propagation elay 30 ps Typical Rise and Fall Times < ps Maximum (RMS) Random Clock Jitter Operating Range: = V to V with = 0 V CML Output Level (400 mv Peak to Peak Output), ifferential Output Only Internal Input and Output Termination Resistors Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP, EP, and SG evices These are Pb Free evices FN 16 MN SUFFIX CASE 485G A L Y W MARKING IAGRAM* = Assembly Location = Wafer Lot = Year = Work Week = Pb Free Package *For additional marking information, refer to Application Note AN8002/. VT VT 1 FUNCTIONAL BLOCK IAGRAM 1 16 R Reset R1 ivide by 2 NB7L 32M ALYW TRUTH TABLE R x x H Z W L Z = LOW to HIGH Transition W = HIGH to LOW Transition x = on t Care L H 2 2 ORERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. Semiconductor Components Industries, LLC, 2011 January, 2011 Rev. 3 1 Publication Order Number: NB7L32M/

2 R Exposed Pad (EP) VT NB7L32M VT NC Figure 1. Pin Configuration (Top View) Table 1. PIN ESCRIPTION Pin Name I/O escription 1 VT Internal termination pin. In the differential configuration when the input termination pin (VT, VT) are connected to a common termination voltage or left open, and if no signal is applied on / input then the device will be susceptible to self oscillation. 2 ECL, CML, LVS Input Noninverted differential input. In the differential configuration when the input termination pin (VT, VT) are connected to a common termination voltage or left open and if no signal is applied on / input, then the device will be susceptible to self oscillation. 3 ECL, CML, LVS Input Inverted differential input. In the differential configuration when the input termination pin (VT, VT) are connected to a common termination voltage or left open and if no signal is applied on / input, then the device will be susceptible to self oscillation. 4 VT Internal termination pin. In the differential configuration when the input termination pin (VT, VT) are connected to a common termination voltage or left open and if no signal is applied on / input, then the device will be susceptible to self oscillation. 5 NC No connect. NC pin must be left open. 6, 7, 8 Negative supply voltage. 9, 12, 13, 14, 16 Positive supply voltage. 10 CML Output Inverted differential output. Typically terminated with resistor to. 11 CML Output Noninverted differential output. Typically terminated with resistor to. 15 R LVTTL/LVCMOS Reset Input. Internal pulldown to 75 k to. EP Exposed Pad. The thermally exposed pad (EP) on package bottom (see case drawing) must be attached to a heat sinking conduit. EP is electrically isolated from and. 2

3 Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor R1 75 k ES Protection Human Body Model Machine Model > 500 V > 30 V Moisture Sensitivity (Note 1) FN 16 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V in Transistor Count 349 Meets or exceeds JEEC Spec EIA/JES78 IC Latchup Test 1. For additional information, see Application Note AN8003/. Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit Positive Power Supply = 0 V 3.6 V Negative Power Supply = 0 V 3.6 V V I Positive Input Negative Input = 0 V = 0 V V I 3.6 V I 3.6 V V V INPP ifferential Input Voltage 2.8 V I IN Input Current Through R T ( Resistor) Static Surge I out Output Current Continuous Surge ma ma ma ma T A Operating Temperature Range FN to +85 C T stg Storage Temperature Range 65 to +150 C JA Thermal Resistance (Junction to Ambient) (Note 2) 0 lfpm 500 lfpm FN 16 FN C/W C/W JC Thermal Resistance (Junction to Case) 1S2P FN C/W T sol Wave Solder Pb Free <3 260 C 265 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 2. JEEC standard multilayer board 1S2P (1 signal, 2 power) with 8 filled thermal vias under exposed pad. 3

4 Table 4. C CHARACTERISTICS, CLOCK INPUTS, CML OUTPUTS = V to V, = 0 V, T A = 40 C to +85 C Symbol Characteristic Min Typ Max Unit I CC Power Supply Current (Note 3) ma V OH Output HIGH Voltage (Note 4) mv V OL Output LOW Voltage (Note 4) mv R TOUT Internal Output Termination Resistor R Temp Coef Internal I/O Termination Resistor Temperature Coefficient 6.38 m / C IFFERENTIAL / INPUT RIVEN SINGLE ENE (see Figure 9 and 11) V th Input Threshold Reference Voltage Range (Note 6) 1050 mv V IH Single ended Input HIGH Voltage V th mv V IL Single ended Input LOW Voltage V th 150 mv IFFERENTIAL / INPUTS RIVEN IFFERENTIALLY (see Figure 10 and 12) V IH ifferential Input HIGH Voltage mv V IL ifferential Input LOW Voltage 75 mv V CMR Input Common Mode Range (ifferential Configuration, Note 7) 1125 mv V I ifferential Input Voltage (V IH V IL ) mv I IH Input HIGH Current / (VT/R/VT/R Open) A I IL Input LOW Current /(VT/R/VT/R Open) 50 0 A R TIN Internal Input Termination Resistor LVTTL/LVCMOS RESET INPUT V IH Single ended Input HIGH Voltage 0 mv V IL Single ended Input LOW Voltage 800 mv I IH Input HIGH Current R A I IL Input LOW Current R A NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. Input termination pins open and all outputs loaded with external R L = receiver termination resistor. 4. CML outputs require R L = receiver termination resistors to for proper operation. (See Figure 8) 5. Input and output parameters vary 1:1 with. 6. V th is applied to the complementary input when operating in single ended mode. 7. V CMR(MIN) varies 1:1 with, V CMR max varies 1:1 with. The V CMR range is referenced to the most positive side of the differential input signal. 4

5 Table 6. AC CHARACTERISTICS = V to V, = 0 V (Note 8) 40 C 25 C 85 C Symbol Characteristic V OUTPP Output Voltage Amplitude (@ V INPP(MIN) ) f in 7 GHz (See Figures 2, 3, 4, 5, and 6) f in 12 GHz Min Typ Max Min Typ Max Min Typ Max Unit mv f IN Maximum Input Clock Frequency (See Figure 2) GHz t PLH, Propagation elay to to t PHL Output ifferential (See Figure 7) R to ps t skew uty Cycle Skew (Note 9) evice to evice Skew (Note 12) t RR Reset Recovery (See Figure 7) ps t PW Minimum Pulse Width R ps t JITTER Random Clock Jitter (RMS) f in 7 GHz (Note 11) f in = 12 GHz ps V INPP Input Voltage Swing/Sensitivity (ifferential Configuration) (Note 10) mv t r t f Output Rise/Fall 1 GHz (20% 80%) ps NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. Measured by forcing V INPP(MIN) from a 50% duty cycle clock source. All loading with an external R L = to. Input edge rates 40 ps (20% 80%). 9. uty cycle skew is measured between differential outputs using the deviations of the sum of Tpw and Tpw+ 1 GHz. 10.V INPP(MAX) cannot exceed. Input voltage swing is a single ended measurement operating in differential mode. 11. Additive RMS jitter with 50% duty cycle input clock signal. 12. evice to device skew is measured between outputs under identical 1 GHz. OUTPUT VOLTAGE AMPLITUE (mv) = 3.3 V = 2.5 V INPUT CLOCK FREUENCY (GHz) Figure 2. Output Voltage Amplitude (V OUTPP ) versus Input Clock Frequency (f OUT ) at Ambient Temperature (V INPP = 150 mv) 5

6 TIME (190 ps/div) Figure 3. Typical Output Waveform with f IN = 7 GHz( = 2.5 V, V INPP = 400 mv, Room Temperature, V OUTPP = 357 mv, t r = 33 ps, t f = 30 ps, f OUT = GHz) TIME (190 ps/div) Figure 4. Typical Output Waveform with f IN = 7 GHz( = 3.3 V, V INPP = 400 mv, Room Temperature, V OUTPP = 387 mv, t r = 32 ps, t f = 29.8 ps, f OUT = GHz) VOLTAGE (50 mv/div) VOLTAGE (50 mv/div) VOLTAGE (50 mv/div) VOLTAGE (50 mv/div) TIME (52 ps/div) Figure 5. Typical Output Waveform with f IN = 14 GHz( = 2.5 V, V INPP = 400 mv, Room Temperature, V OUTPP = 292 mv, t r = 25 ps, t f = 27 ps, f OUT = 7.01 GHz) TIME (52 ps/div) Figure 6. Typical Output Waveform with f IN = 14 GHz( = 3.3 V, V INPP = 400 mv, Room Temperature, V OUTPP = 319 mv, tr = 25 ps, t f = 26 ps, f OUT = 7.01 GHz) 50% 50% V OUTPP = V OH () V OL () t PLH t PHL 50% 50% V INPP = V IH () V IL () R t RR(MIN) 50% Figure 7. AC Reference Measurement (Timing iagram) 6

7 river evice Z o = Z o = Receiver evice Figure 8. Typical Termination for Output river and evice Evaluation (See Application Note AN8073/ Termination of CML Logic evices.) V th V th Figure 9. ifferential Input riven Single Ended Figure 10. ifferential Inputs riven ifferentially V th Vthmax V IHmax V ILmax V IH V th V IL V CMR V CMmax V IHmax V ILmax V I = V IH V IL V IHtyp V ILtyp V thmin GN V IHmin V ILmin NOTE: Figure 11. V th iagram V IHmin V CMmin V ILmin GN V IN mv; V IH > V IL Figure 12. V CMR iagram 16 ma Figure 13. CML Output Structure 7

8 APPLICATION INFORMATION All NB7L32M inputs can accept PECL, CML, and LVS signal levels. The limitations for differential input signal (LVS, PECL, or CML) are minimum input swing of 150 mv and the maximum input swing of 2500 mv. Within these conditions, the input voltage can range from to 1.2 V. Examples interfaces are illustrated below in a environment (Z = ). For output termination and interface, refer to application note AN8020/. Table 5. INTERFACING OPTIONS Interfacing Options Connections CML Connect VT and VT to (See Figure 14) LVS Connect VT and VT Together (See Figure 16) AC COUPLE Bias VT and VT Inputs within Common Mode Range (V CMR ) (See Figure 15) RSECL, PECL, NECL Standard ECL Termination Techniques (See Figure 8) Z = CML river Z = VT VT NB7L32M Figure 14. CML to NB7L32M Interface Z = C Recommended R T Values PECL river Z = V Bias * V Bias * C VT VT NB7L32M R T 5.0 V 290 R T R T 3.3 V V 80 *V Bias must be within common mode range limits (V CMR ) Figure 15. PECL to NB7L32M Interface 8

9 APPLICATION INFORMATION Z = LVS river Z = VT VT NB7L32M Figure 16. LVS to NB7L32M Interface ORERING INFORMATION NB7L32MMNG NB7L32MMNR2G evice Package Shipping FN 16 (Pb Free) FN 16 (Pb Free) 123 Units / Rail 3000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BR8011/. 9

10 PACKAGE IMENSIONS FN16 3x3, P CASE 485G 01 ISSUE F 2X PIN 1 LOCATION 2X NOTE C 0.05 C 0.05 C 0.10 C ETAIL A 16X L ÇÇÇ ÇÇÇ TOP VIEW ETAIL B SIE VIEW 2 8 (A3) A B E A1 A C 0.10 C A B L1 EXPOSE Cu SEATING PLANE L ETAIL A ALTERNATE TERMINAL CONSTRUCTIONS ÉÉ MOL CMP A1 ETAIL B ALTERNATE CONSTRUCTIONS PACKAGE OUTLINE L ÉÉ A3 NOTES: 1. IMENSIONING AN TOLERANCING PER ASME Y14.5M, CONTROLLING IMENSION: MILLIMETERS. 3. IMENSION b APPLIES TO PLATE TERMINAL AN IS MEASURE BETWEEN 0.25 AN 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSE PA AS WELL AS THE TERMINALS. MILLIMETERS IM MIN NOM MAX A A A REF b BSC E 3.00 BSC E e 0 BSC K 0.18 TYP L L RECOMMENE SOLERING FOOTPRINT* 16X X K 1 E2 2X 2X e e/2 BOTTOM VIEW 16X b 0.10 C 0.05 C A B NOTE 3 16X PITCH IMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLERRM/. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORERING INFORMATION LITERATURE FULFILLMENT: Literature istribution Center for ON Semiconductor P.O. Box 5163, enver, Colorado USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative NB7L32M/