MC10EP142, MC100EP V / 5 VНECL 9 Bit Shift Register
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- Clinton Wilfrid Francis
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1 MC0EP42, MCEP V / 5 VНECL Bit Shift Register The MC0EP/EP42 is a bit shift register, designed with byte-parity applications in mind. The MC0/EP42 is capable of performing serial/parallel data into serial/parallel out and shifting in only one direction. The nine inputs D0 D8 accept parallel input data, while S IN accepts serial input data. The QT0:87 outputs do not need to be terminated for the shift operation to function. To minimize power, any Q output not used should be left unterminated. The SEL (Select) input pin is used to switch between the two modes of operation SHIFT and LOAD. The shift direction is from Bit 0 to Bit 8. Input data is accepted by the registers a set up time before the positive going edge of CLK0 or CLK; shifting is also accomplished on the positive clock edge. A HIGH on the Master Reset pin (MR) asynchronously resets all the registers to zero, overriding CLK0 and CLK inputs. The Series contains temperature compensation. Features Shift Frequency >2.8 GHz (Typical) -Bit for Byte Parity Applications Asynchronous Master Reset Dual Clocks PECL Mode Operating Range: V CC = 3.0 V to 5.5 V with V EE = 0 V NECL Mode Operating Range: V CC = 0 V with V EE = 3.0 V to 5.5 V Open Input Default State Safety Clamp on Inputs Pb Free Packages are Available FA SUFFIX CASE 873A 32 QFN32 MN SUFFIX CASE 488AM 32 MARKING DIAGRAM* MCxxx EP42 AWLYYWWG xxx = 0 or A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or = Pb Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. MCxxx EP42 AWLYYWW ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page of this data sheet. Semiconductor Components Industries, LLC, 2006 Publication Order Number: MC0EP42/D
2 MC0EP42, MCEP42 Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor (R) 75 k Internal Input Pullup Resistor (R2) 37.5 k ESD Protection Moisture Sensitivity (Note 3) Human Body Model Machine Model Charged Device Model LQFP QFN > 2 kv > V > 2 kv Level 2 Level Flammability Rating Oxygen Index: 28 to 34 UL 4 V 0.25 in Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, refer to Application Note AND8003/D. 405 Devices Table 4. MAXIMUM RATINGS Symbol Parameter Condition Condition 2 Rating Unit V CC Positive Power Supply V EE = 0 V 8 V V EE Negative Power Supply V CC = 0 V 8 V V I PECL Mode Input Voltage NECL Mode Input Voltage V EE = 0 V V CC = 0 V I out Output Current Continuous Surge V I V CC 6 V I V EE 6 T A Operating Temperature Range 40 to +85 C T stg Storage Temperature Range 65 to + C JA Thermal Resistance (Junction to Ambient) 0 lfpm 0 lfpm JC Thermal Resistance (Junction to Case) Standard Board 2 to 7 C/W JA Thermal Resistance (Junction to Ambient) 0 lfpm 0 lfpm JC Thermal Resistance (Junction to Case) 2S2P 2 C/W T sol Wave Solder Pb Pb Free C C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability V ma C/W C/W C 5
3 MC0EP42, MCEP42 Table 7. 0EP DC CHARACTERISTICS, NECL V CC = 0 V, V EE = 5.5 V to 3.0 V (Note ) I EE Negative Power Supply Current (Note 2) ma V OH Output HIGH Voltage (Note 3) mv V OL Output LOW Voltage (Note 3) mv V IH Input HIGH Voltage (Single Ended) mv V IL Input LOW Voltage (Single Ended) mv (Note 4) V EE V EE V EE V I IH Input HIGH Current (@ V IH ) CLK0, CLK, D, S IN CLK0, CLK, S IN board with maintained transverse airflow greater than 0 lfpm. Electrical parameters are guaranteed only over the declared. Input and output parameters vary : with V CC. 2.Required 0 lfpm air flow when using 5 V power supply. For (V CC V EE ) >3.3 V, 5 to 0 in line with V EE required for maximum thermal protection at elevated temperatures. Recommend V CC V EE operation at 3.3 V. 3.All loading with to V CC 2.0 V. 4. min varies : with V EE, max varies : with V CC. The range is referenced to the most positive side of the differential Table 8. EP DC CHARACTERISTICS, PECL V CC = 3.3 V, V EE = 0 V (Note 5) I EE Negative Power Supply Current ma V OH Output HIGH Voltage (Note 6) mv V OL Output LOW Voltage (Note 6) mv V IH Input HIGH Voltage (Single Ended) mv V IL Input LOW Voltage (Single Ended) mv (Note 7) V I IH Input HIGH Current (@ V IH ) CLK0, CLK, D, S IN CLK0, CLK, S IN board with maintained transverse airflow greater than 0 lfpm. Electrical parameters are guaranteed only over the declared 5.Input and output parameters vary : with V CC. V EE can vary +0.3 V to 2.2 V. 6.All loading with to V CC 2.0 V. 7. min varies : with V EE, max varies : with V CC. The range is referenced to the most positive side of the differential 7
4 MC0EP42, MCEP42 Table. EP DC CHARACTERISTICS, PECL V CC = 5.0 V, V EE = 0 V (Note 8) I EE Negative Power Supply Current (Note ) ma V OH Output HIGH Voltage (Note 20) mv V OL Output LOW Voltage (Note 20) mv V IH Input HIGH Voltage (Single Ended) mv V IL Input LOW Voltage (Single Ended) mv (Note 2) V I IH Input HIGH Current (@ V IH ) CLK0, CLK, D, S IN CLK0, CLK, S IN board with maintained transverse airflow greater than 0 lfpm. Electrical parameters are guaranteed only over the declared 8.Input and output parameters vary : with V CC. V EE can vary +2.0 V to V..Required 0 lfpm air flow when using +5 V power supply. For (V CC V EE ) >3.3 V, 5 to 0 in line with V EE required for maximum thermal protection at elevated temperatures. Recommend V CC V EE operation at 3.3 V. 20.All loading with to V CC 2.0 V. 2. min varies : with V EE, max varies : with V CC. The range is referenced to the most positive side of the differential Table 0. EP DC CHARACTERISTICS, NECL V CC = 0 V, V EE = 5.5 V to 3.0 V (Note 22) I EE Negative Power Supply Current (Note 23) ma V OH Output HIGH Voltage (Note 24) mv V OL Output LOW Voltage (Note 24) mv V IH Input HIGH Voltage (Single Ended) mv V IL Input LOW Voltage (Single Ended) mv (Note 25) V EE V EE V EE V I IH Input HIGH Current (@ V IH ) CLK0, CLK, D, S IN CLK0, CLK, S IN board with maintained transverse airflow greater than 0 lfpm. Electrical parameters are guaranteed only over the declared 22.Input and output parameters vary : with V CC. 23.Required 0 lfpm air flow when using 5 V power supply. For (V CC V EE ) >3.3 V, 5 to 0 in line with V EE required for maximum thermal protection at elevated temperatures. Recommend V CC V EE operation at 3.3 V. 24.All loading with to V CC 2.0 V. 25. min varies : with V EE, max varies : with V CC. The range is referenced to the most positive side of the differential 8
5 MC0EP42, MCEP42 Table. AC CHARACTERISTICS V CC = 3.0 V to 5.5 V; V EE = 0.0 V or V CC = 0.0 V; V EE = 3.0 V to 5.5 V (Note 26) Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max f SHIFT Maximum Shift Frequency 2.8 GHz t PLH, t PHL t s t h Propagation Delay to Output Setup Time Hold Time CLKx MR D SEL D SEL t RR Reset Recovery Time 800 t pw Minimum Pulse Width 200 t SKEW Within-Device Skew (Note 27) Q, Q Duty Cycle Skew (Note 28) 5.0 t JITTER Random Clock Jitter (Figure 4) V inpp Input Voltage Swing/Sensitivity (Differential Configuration) mv 20 Unit t r, t f Rise/Fall MHz (20-80%) board with maintained transverse airflow greater than 0 lfpm. Electrical parameters are guaranteed only over the declared 26.Measured using a 7 mv source, % duty cycle clock source. All loading with to V CC 2.0 V. 27. Within-device skew is defined as identical transitions on similar paths through a device. 28. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point of the outputs. 00 Output Voltage Amplitude (mv) É INPUT FREQUENCY (MHz) JITTER OUT (RMS) Figure 4. Output Voltage Amplitude / RMS Jitter vs. Input Frequency at Ambient Temperature (Typical)
6 MC0EP42, MCEP42 ORDERING INFORMATION Device Package Shipping MC0EP42FA 2 Units / Tray MC0EP42FAG 2 Units / Tray MC0EP42FAR / Tape & Reel MC0EP42FAR2G MC0EP42MNG MC0EP42MNR4G 2000 / Tape & Reel 74 Units / Rail 0 / Tape & Reel MCEP42FA 2 Units / Tray MCEP42FAG 2 Units / Tray MCEP42FAR / Tape & Reel MCEP42FAR2G MCEP42MNG 2000 / Tape & Reel 74 Units / Rail MCEP42MNR4G 0 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD80/D. Resource Reference of Application Notes AN405/D ECL Clock Distribution Techniques AN406/D Designing with PECL (ECL at +5.0 V) AN3/D ECLinPS I/O SPiCE Modeling Kit AN4/D Metastability and the ECLinPS Family AN568/D Interfacing Between LVDS and ECL AN672/D The ECL Translator Guide AND800/D Odd Number Counters Design AND8002/D Marking and Date Codes AND8020/D Termination of ECL Logic Devices AND8066/D Interfacing with ECLinPS AND800/D AC Characteristics of ECL Devices
7 MC0EP42, MCEP42 PACKAGE DIMENSIONS 32 LEAD LQFP CASE 873A 02 ISSUE C A 32 A 25 4X 0.20 (0.008) AB T U Z T, U, Z T U P AE B SEATING PLANE B AB AC 8 S DETAIL Y Z S G 0.0 (0.004) AC 7 4X V V 0.20 (0.008) AC T U Z DETAIL AD C E 8X M DETAIL Y AE R BASE METAL N F J D 0.20 (0.008) M AC T U Z SECTION AE AE H W DETAIL AD X K Q GAUGE PLANE 0.2 (0.00) NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE AB IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS T, U, AND Z TO BE DETERMINED AT DATUM PLANE AB. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE AC. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.2 (0.00) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE AB. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 20 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE (0.0003).. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MILLIMETERS INCHES DIM MIN MAX MIN MAX A BSC BSC A 3.0 BSC 0.38 BSC B BSC BSC B 3.0 BSC 0.38 BSC C D E F G BSC 0.03 BSC H J K M 2 REF 2 REF N P BSC 0.06 BSC Q 5 5 R S.000 BSC BSC S 4.0 BSC 0.77 BSC V.000 BSC BSC V 4.0 BSC 0.77 BSC W REF REF X.000 REF 0.03 REF 2
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ECL/PECL Dual Differential 2:1 Multiplexer
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Features. Truth Table (1)
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Features. Applications
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