MC10EP195, MC100EP V ECL Programmable Delay Chip

Transcription

1 MC1EP195, MC1EP V ECL Programmable Delay Chip The MC1/1EP195 is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The delay section consists of a programmable matrix of gates and multiplexers as shown in the logic diagram, Figure 3. The delay increment of the EP195 has a digitally selectable resolution of about 1 ps and a net range of up to 1.2 ns. The required delay is selected by the 1 data select inputs D[9:] values and controlled by the (pin 1). A LOW level on allows a transparent LOAD mode of real time delay values by D[9:]. A LOW to HIGH transition on will LOCK and HOLD current values present against any subsequent changes in D[1:]. The approximate delay values for varying tap numbers correlating to D (LSB) through D9 (MSB) are shown in Table 6 and Figure 4. Because the EP195 is designed using a chain of multiplexers it has a fixed minimum delay of 2.2 ns. An additional pin D1 is provided for controlling Pins 14 and 15, CASCADE and CASCADE, also latched by, in cascading multiple PDCs for increased programmable range. The cascade logic allows full control of multiple PDCs. Switching devices from all 1 states on D[:9] with SETMAX LOW to all states on D[:9] with SETMAX HIGH will increase the delay equivalent to D, the minimum increment. Select input pins D[1:] may be threshold controlled by combinations of interconnects between V EF (pin 7) and V CF (pin 8) for LVCMOS, ECL, or LVTTL level signals. For LVCMOS input levels, leave V CF and V EF open. For ECL operation, short V CF and V EF (Pins 7 and 8). For LVTTL level operation, connect a 1.5 V supply reference to V CF and leave open V EF pin. The 1.5 V reference voltage to V CF pin can be accomplished by placing a 2.2 k resistor between V CF and for a 3.3 V power supply. The V BB pin, an internally generated voltage supply, is available to this device only. For single ended input conditions, the unused differential input is connected to V BB as a switching reference voltage. V BB may also rebias AC coupled inputs. When used, decouple V BB and via a.1 F capacitor and limit current sourcing or sinking to.5 ma. When not used, V BB should be left open. The 1 Series contains temperature compensation. Maximum Input Clock Frequency >1.2 GHz Typical Programmable Range: ns to 1 ns Delay Range: 2.2 ns to 12.2 ns 1 ps Increments PECL Mode Operating Range: = 3. V to 3.6 V with = V NECL Mode Operating Range: = V with = 3. V to 3.6 V LFP 32 FA SUFFIX CASE 873A 1 32 FN32 MN SUFFIX CASE 488AM Open Input Default State Safety Clamp on Inputs A Logic High on the EN Pin Will Force to Logic Low D[1:] Can Accept Either ECL, LVCMOS, or LVTTL Inputs V BB Output Reference Voltage Pb Free Packages are Available 32 MARKG DIAGRAM* MCXXX EP195 AWLYYWWG XXX = 1 or 1 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or = Pb Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND82/D. ORDERG FORMATION See detailed ordering and shipping information in the package dimensions section on page 17 of this data sheet. 1 1 MCXXX EP195 AWLYYWW Semiconductor Components Industries, LLC, 29 April, 29 Rev Publication Order Number: MC1EP195/D

2 MC1EP195, MC1EP195 D1 D2 D3 D4 D5 D6 D7 D D D D MC1EP195 MC1EP V BB 6 19 V EF 7 18 V CF NC EN CASCADE CASCADE SETMAX SETM Figure Lead LFP Pinout (Top View) D1 D2 D3 D4 D5 D6 D D D D D V BB 6 19 V EF 7 18 V CF 8 17 NC SETM SETMAX CASCADE CASCADE EN Exposed Pad (EP) Figure Lead FN (Top View) 2

3 MC1EP195, MC1EP195 Table 1. P DESCRIPTION Pin Name I/O Default State Description 23, 25, 26, 27, 29, 3, 31, 32, 1, 2 D[:9] LVCMOS, LVTTL, ECL Input Low Single Ended Parallel Data Inputs [:9]. Internal 75 k to. (Note 1) 3 D[1] LVCMOS, LVTTL, ECL Input Low Single Ended CASCADE/CASCADE Control Input. Internal 75 k to. (Note 1) 4 ECL Input Low Noninverted Differential Input. Internal 75 k to. 5 ECL Input High Inverted Differential Input. Internal 75 k to and 36.5 k to. 6 V BB ECL Reference Voltage Output 7 V EF Reference Voltage for ECL Mode Connection 8 V CF LVCMOS, ECL, OR LVTTL Input Mode Select 9, 24, 28 Negative Supply Voltage. All Pins must be Externally Connected to Power Supply to Guarantee Proper Operation. (Note 2) 13, 18, 19, 22 Positive Supply Voltage. All Pins must be externally Connected to Power Supply to Guarantee Proper Operation. (Note 2) 1 ECL Input Low Single ended D pins LOAD / HOLD input. Internal 75 k to. 11 SETM ECL Input Low Single ended Minimum Delay Set Logic Input. Internal 75 k to. (Note 1) 12 SETMAX ECL Input Low Single ended Maximum Delay Set Logic Input. Internal 75 k to. (Note 1) 14 CASCADE ECL Output Inverted Differential Cascade Output for D[1]. Typically Terminated with 5 to V TT = 2 V. 15 CASCADE ECL Output Noninverted Differential Cascade Output. for D[1] Typically Terminated with 5 to V TT = 2 V. 16 EN ECL Input Low Single ended Output Enable Pin. Internal 75 k to. 17 NC No Connect. The NC Pin is Electrically Connected to the Die and MUST BE Left Open 21 ECL Output Noninverted Differential Output. Typically Terminated with 5 to V TT = 2 V. 2 ECL Output Inverted Differential Output. Typically Terminated with 5 to V TT = 2 V. 1. SETM will override SETMAX if both are high. SETMAX and SETM will override all D[:1] inputs. 2. All and pins must be externally connected to Power Supply to guarantee proper operation. 3

4 MC1EP195, MC1EP195 Table 2. CONTROL P Pin State Function EN LOW (Note 3) Input Signal is Propagated to the Output HIGH Output Holds Logic Low State LOW (Note 3) Transparent or LOAD mode for real time delay values present on D[:1]. HIGH SETM LOW (Note 3) Output Delay set by D[:1] HIGH LOCK and HOLD mode for delay values on D[:1]; further changes on D[:1] are not recognized and do not affect delay. Set Minimum Output Delay SETMAX LOW (Note 3) Output Delay set by D[:1] HIGH Set Maximum Output Delay D1 LOW (Note 3) CASCADE Output LOW, CASCADE Output HIGH HIGH 3. Internal pulldown resistor will provide a logic LOW if pin is left unconnected. CASCADE Output LOW, CASCADE Output HIGH Table 3. CONTROL D[:1] TERFACE V CF V EF Pin (Note 4) ECL Mode V CF No Connect LVCMOS Mode V CF 1.5 V 1 mv LVTTL Mode (Note 5) 4. Short V CF (pin 8) and V EF (pin 7). 5. When Operating in LVTTL Mode, the reference voltage can be provided by connecting an external resistor, R CF (suggested resistor value is 2.2 k 5%), between V CF and pins. Table 4. DATA PUT ALLOWED OPERATG VOLTAGE MODE TABLE CONTROL DATA SELECT PUTS PS (D [:1]) POWER SUPPLY LVCMOS LVTTL LVPECL LVNECL PECL Mode Operating Range YES YES YES N/A NECL Mode Operating Range N/A N/A N/A YES Table 5. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor () 75 k ESD Protection Human Body Model Machine Model Charged Device Model > 2 kv > 1 V > 2 kv Moisture Sensitivity, Indefinite Time Out of Drypack (Note 6) Pb Pkg Pb Free Pkg LFP 32 Level 2 Level 2 FN 32 Level 1 Flammability Rating Oxygen Index: 28 to 34 Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 6. For additional information, see Application Note AND83/D. UL 94 in 1217 Devices 4

5 MC1EP195, MC1EP EN SET M SET MAX V BB V CF V EF D9 Latch D D8 D7 CASCADE CASCADE BIT LATCH D6 D5 D4 D3 D2 D1 D *GD = (GATE DELAY) APPROXIMATELY 1 ps DELAY PER GATE (MIMUM FIXED DELAY APPROX. 2.2 ns) Figure 3. Logic Diagram 5

6 MC1EP195, MC1EP195 Table 6. THEORETICAL DELAY VALUES D(9:) Value SETM SETMAX Programmable Delay* XXXXXXXXXX H L ps L L ps 1 L L 1 ps 1 L L 2 ps 11 L L 3 ps 1 L L 4 ps 11 L L 5 ps 11 L L 6 ps 111 L L 7 ps 1 L L 8 ps 1 L L 16 ps 1 L L 32 ps 1 L L 64 ps 1 L L 128 ps 1 L L 256 ps 1 L L 512 ps L L 123 ps XXXXXXXXXX L H 124 ps *Fixed minimum delay not included. 6

7 MC1EP195, MC1EP DELAY ( ps) C C 1. 4 C 9. = V 8. = 3.3 V Decimal Value of Select Inputs (D[9:]) Figure 4. Measured Delay vs. Select Inputs Table 7. MAXIMUM RATGS Symbol Parameter Condition 1 Condition 2 Rating Unit Positive Mode Power Supply = V 6 V Negative Mode Power Supply = V 6 V V I Positive Mode Input Voltage Negative Mode Input Voltage = V = V I out Output Current Continuous Surge V I 6 V I 6 I BB V BB Sink/Source ±.5 ma T A Operating Temperature Range 4 to +85 C T stg Storage Temperature Range 65 to +15 C JA Thermal Resistance (Junction to Ambient) lfpm 5 lfpm LFP 23 LFP 23 JC Thermal Resistance (Junction to Case) Standard Board LFP to 17 C/W JA Thermal Resistance (Junction to Ambient) lfpm 5 lfpm FN 32 FN 32 JC Thermal Resistance (Junction to Case) 2S2P FN C/W T sol Wave Solder Pb Pb Free <2 to C <2 to 3 26 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability V V ma ma C/W C/W C/W C/W C 7

8 MC1EP195, MC1EP195 Table 8. 1EP DC CHARACTERISTICS, PECL = 3.3 V, = V (Note 7) Symbol Characteristic 4 C 25 C 85 C Min Typ Max Min Typ Max Min Typ Max I EE Negative Power Supply Current ma V OH Output HIGH Voltage (Note 8) mv V OL Output LOW Voltage (Note 8) mv V IH V IL Input HIGH Voltage (Single Ended) Input LOW Voltage (Single Ended) LVPECL LVCMOS LVTTL LVPECL LVCMOS LVTTL V BB ECL Output Voltage Reference mv V CF LVTTL Mode Input Detect Voltage V V EF Reference Voltage for ECL Mode Connection mv V IHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 9) V I IH Input HIGH Current (@ V IH ) A Unit mv mv I IL Input LOW Current (@ V IL ) A NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 5 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. Input and output parameters vary 1:1 with. can vary +.3 V to.3 V. 8. All loading with 5 to 2. V. 9. V IHCMR min varies 1:1 with, V IHCMR max varies 1:1 with. The V IHCMR range is referenced to the most positive side of the differential input signal. 8

9 MC1EP195, MC1EP195 Table 9. 1EP DC CHARACTERISTICS, NECL = V, = 3.3 V to 3. V (Note 1) Symbol Characteristic 4 C 25 C 85 C Min Typ Max Min Typ Max Min Typ Max I EE Negative Power Supply Current ma V OH Output HIGH Voltage (Note 11) mv V OL Output LOW Voltage (Note 11) mv V IH Input HIGH Voltage (Single Ended) LVNECL Unit mv V IL Input LOW Voltage (Single Ended) LVNECL mv V BB ECL Output Voltage Reference mv V EF Reference Voltage for ECL Mode Connection mv V IHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 12) V I IH Input HIGH Current (@ V IH ) A I IL Input LOW Current (@ V IL ).5 15 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 5 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1.Input and output parameters vary 1:1 with. can vary +.3 V to.3 V. 11. All loading with 5 to 2. V. 12.V IHCMR min varies 1:1 with, V IHCMR max varies 1:1 with. The V IHCMR range is referenced to the most positive side of the differential input signal A 9

10 MC1EP195, MC1EP195 Table 1. 1EP DC CHARACTERISTICS, PECL = 3.3 V, = V (Note 13) Symbol Characteristic 4 C 25 C 85 C Min Typ Max Min Typ Max Min Typ Max I EE Negative Power Supply Current ma V OH Output HIGH Voltage (Note 14) mv V OL Output LOW Voltage (Note 14) mv V IH V IL Input HIGH Voltage (Single Ended) Input LOW Voltage (Single Ended) LVPECL CMOS TTL LVPECL CMOS TTL V BB ECL Output Voltage Reference mv V CF LVTTL Mode Input Detect Voltage V V EF Reference Voltage for ECL Mode Connection mv V IHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 15) V I IH Input HIGH Current (@ V IH ) A Unit mv mv I IL Input LOW Current (@ V IL ) A NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 5 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 13.Input and output parameters vary 1:1 with. can vary +.3 V to.3 V. 14.All loading with 5 to 2. V. 15.V IHCMR min varies 1:1 with, V IHCMR max varies 1:1 with. The V IHCMR range is referenced to the most positive side of the differential input signal. 1

11 MC1EP195, MC1EP195 Table 11. 1EP DC CHARACTERISTICS, NECL = V, = 3.3 V (Note 16) 4 C 25 C 85 C Symbol I EE Characteristic Negative Power Supply Current (Note 17) Min Typ Max Min Typ Max Min Typ Max ma Unit V OH Output HIGH Voltage (Note 18) mv V OL Output LOW Voltage (Note 18) mv V IH V IL Input HIGH Voltage (Single Ended) LVNECL Input LOW Voltage (Single Ended) LVNECL mv mv V BB ECL Output Voltage Reference mv V EF Reference Voltage for ECL Mode Connection mv V IHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 19) V I IH Input HIGH Current (@ V IH ) A I IL Input LOW Current (@ V IL ).5 15 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 5 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 16.Input and output parameters vary 1:1 with. can vary +.3 V to.3 V. 17.Recommended operation at 3. V 3.6 V. 18.All loading with 5 to 2. V. 19.V IHCMR min varies 1:1 with, V IHCMR max varies 1:1 with. The V IHCMR range is referenced to the most positive side of the differential input signal A 11

12 MC1EP195, MC1EP195 Table 12. AC CHARACTERISTICS = V; = 3. V to 3.6 V or = 3. V to 3.6 V; = V (Note 2) Symbol Characteristic 4 C 25 C 85 C Min Typ Max Min Typ Max Min Typ Max f max Maximum Frequency GHz t PLH t PHL Propagation Delay to ; D( 1) = to ; D( 1) = 123 EN to ; D( 1) = D to CASCADE Unit ps t RANGE Programmable Range t PD (max) t PD (min) t Step Delay (Note 21) D High D1 High D2 High D3 High D4 High D5 High D6 High D7 High D8 High D9 High mono Monotonicity (Note 27) TBD t SKEW Duty Cycle Skew (Note 22) t s t h t R Setup Time Hold Time Release Time t PHL t PLH D to D to (Note 23) EN to (Note 24) to D to EN (Note 25) EN to (Note 26) SET MAX to SET M to ps ps ps ps ps ps t jitter V PP t r t f RMS Random Clock 1.2 GHz to ; D(:1) = or SETM to ; D(:1) = 123 or SETMAX Input Voltage Swing (Differential Configuration) Output Rise/Fall 5 MHz 2 8% () 2 8% (CASCADE) mv NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 5 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2.Measured using a 75 mv source, 5% duty cycle clock source. All loading with 5 to 2. V. 21. Specification limits represent the amount of delay added with the assertion of each individual delay control pin. The various combinations of asserted delay control inputs will typically realize D resolution steps across the specified programmable range. 22. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output. 23.This setup time defines the amount of time prior to the input signal the delay tap of the device must be set. 24.This setup time is the minimum time that EN must be asserted prior to the next transition of / to prevent an output response greater than ±75 mv to that / transition. 25.This hold time is the minimum time that EN must remain asserted after a negative going or positive going to prevent an output response greater than ±75 mv to that / transition. 26.This release time is the minimum time that EN must be deasserted prior to the next / transition to ensure an output response that meets the specified to propagation delay and transition times. 27. The monotonicity indicates the increasing delay value for each binary count increment on the control inputs D[9:] ps ps 12

13 MC1EP195, MC1EP195 V PP = V IH (D) V IL (D) V OUTPP = V OH () V OL () t PHL t PLH Figure 5. AC Reference Measurement Cascading Multiple EP195s To increase the programmable range of the EP195, internal cascade circuitry has been included. This circuitry allows for the cascading of multiple EP195s without the need for any external gating. Furthermore, this capability requires only one more address line per added E195. Obviously, cascading multiple programmable delay chips will result in a larger programmable range: however, this increase is at the expense of a longer minimum delay. Figure 6 illustrates the interconnect scheme for cascading two EP195s. As can be seen, this scheme can easily be expanded for larger EP195 chains. The D1 input of the EP195 is the CASCADE control pin. With the interconnect scheme of Figure 6 when D1 is asserted, it signals the need for a larger programmable range than is achievable with a single device and switches output pin CASCADE HIGH and pin CASCADE LOW. The A11 address can be added to generate a cascade output for the next EP195. For a 2 device configuration, A11 is not required. Need if Chip #3 is used ADDRESS BUS A11 A1 A9 A8 A7 A6 A5 A4 A3 A2 A1 A D7 D6 D5 D4 D3 D2 D1 D7 D6 D5 D4 D3 D2 D1 D8 D8 D9 D D9 D PUT D1 V BB EP195 CHIP #2 D1 V BB EP195 CHIP #1 OUTPUT V EF V EF V CF SETM SETMAX CASCADE CASCADE EN NC V CF SETM SETMAX CASCADE CASCADE EN NC Figure 6. Cascading Interconnect Architecture 13

14 MC1EP195, MC1EP195 An expansion of the latch section of the block diagram is pictured in Figure 7. Use of this diagram will simplify the explanation of how the cascade circuitry works. When D1 of chip #1 in Figure 6 is LOW this device s CASCADE output will also be low while the CASCADE output will be high. In this condition the SET M pin of chip #2 will be asserted HIGH and thus all of the latches of chip #2 will be reset and the device will be set at its minimum delay. Chip #1, on the other hand, will have both SET M and SET MAX deasserted so that its delay will be controlled entirely by the address bus A A9. If the delay needed is greater than can be achieved with 123 gate delays ( on the A A9 address bus) D1 will be asserted to signal the need to cascade the delay to the next EP195 device. When D1 is asserted, the SET M pin of chip #2 will be deasserted and SET MAX pin asserted resulting in the device delay to be the maximum delay. Table 13 shows the delay time of two EP195 chips in cascade. To expand this cascading scheme to more devices, one simply needs to connect the D1 pin from the next chip to the address bus and CASCADE outputs to the next chip in the same manner as pictured in Figure 6. The only addition to the logic is the increase of one line to the address bus for cascade control of the second programmable delay chip. TO SELECT MULTIPLEXERS BIT BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 9 D D1 1 D2 2 D3 3 D4 4 D5 5 D6 6 D7 7 D8 8 D9 9 SET M Set Reset Set Reset Set Reset Set Reset Set Reset Set Reset Set Reset Set Reset Set Reset Set Reset SET MAX Figure 7. Expansion of the Latch Section of the EP195 Block Diagram 14

15 MC1EP195, MC1EP195 Table 13. Delay Value of Two EP195 Cascaded VARIABLE PUT TO CHIP #1 AND SETM FOR CHIP #2 PUT FOR CHIP #1 Total D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D Delay Value Delay Value ps 44 ps 1 1 ps 441 ps 1 2 ps 442 ps ps 443 ps 1 4 ps 444 ps ps 445 ps ps 446 ps ps 447 ps 1 8 ps 448 ps 1 16 ps 456 ps 1 22 ps 472 ps 1 64 ps 54 ps ps 568 ps ps 696 ps ps 952 ps ps 1463 ps VARIABLE PUT TO CHIP #1 AND SETMAX FOR CHIP #2 PUT FOR CHIP #1 Total D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D Delay Value Delay Value ps 1464 ps ps 1465 ps ps 1466 ps ps 1467 ps ps 1468 ps ps 1469 ps ps 147 ps ps 1471 ps ps 1472 ps ps 148 ps ps 1496 ps ps 1528 ps ps 1592 ps ps 172 ps ps 1976 ps ps 2487 ps 15

16 MC1EP195, MC1EP195 Multi Channel Deskewing The most practical application for EP195 is in multiple channel delay matching. Slight differences in impedance and cable length can create large timing skews within a high speed system. To deskew multiple signal channels, each channel can be sent through each EP195 as shown in Figure 8. One signal channel can be used as reference and the other EP195s can be used to adjust the delay to eliminate the timing skews. Nearly any high speed system can be fine tuned (as small as 1 ps) to reduce the skew to extremely tight tolerances. EP195 #1 EP195 #2 Control Logic Digital Data EP195 #N Figure 8. Multiple Channel Deskewing Diagram Measure Unknown High Speed Device Delays EP195s provide a possible solution to measure the unknown delay of a device with a high degree of precision. By combining two EP195s and EP31 as shown in Figure 9, the delay can be measured. The first EP195 can be set to SETM and its output is used to drive the unknown delay device, which in turn drives the input of a D flip flop of EP31. The second EP195 is triggered along with the first EP195 and its output provides a clock signal for EP31. The programmed delay of the second EP195 is varied to detect the output edge from the unknown delay device. If the programmed delay through the second EP195 is too long, the flip flop output will be at logic high. On the other hand, if the programmed delay through the second EP195 is too short, the flip flop output will be at a logic low. If the programmed delay is correctly fine tuned in the second EP195, the flip flop will bounce between logic high and logic low. The digital code in the second EP195 can be directly correlated into an accurate device delay. CLOCK CLOCK EP195 #1 Unknown Delay Device D EP31 EP195 #2 CLK Control Logic Figure 9. Multiple Channel Deskewing Diagram 16

17 MC1EP195, MC1EP195 Driver Device Z o = 5 Z o = 5 D D Receiver Device 5 5 V TT V TT = 2. V Figure 1. Typical Termination for Output Driver and Device Evaluation (See Application Note AND82/D Termination of ECL Logic Devices.) ORDERG FORMATION Device Package Shipping MC1EP195FA LFP Units / Tray MC1EP195FAG LFP 32 (Pb Free) 25 Units / Tray MC1EP195FAR2 LFP 32 2 / Tape & Reel MC1EP195FAR2G MC1EP195MNG MC1EP195MNR4G LFP 32 (Pb Free) FN 32 (Pb Free) FN 32 (Pb Free) 2 / Tape & Reel 74 Units / Rail 1 / Tape & Reel MC1EP195FA LFP Units / Tray MC1EP195FAG LFP 32 (Pb Free) 25 Units / Tray MC1EP195FAR2 LFP 32 2 / Tape & Reel MC1EP195FAR2G MC1EP195MNG LFP 32 (Pb Free) FN 32 (Pb Free) 2 / Tape & Reel 74 Units / Rail MC1EP195MNR4G FN 32 (Pb Free) 1 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD811/D. 17

18 MC1EP195, MC1EP195 Resource Reference of Application Notes AN145/D ECL Clock Distribution Techniques AN146/D Designing with PECL (ECL at +5. V) AN153/D ECLinPS I/O SPiCE Modeling Kit AN154/D Metastability and the ECLinPS Family AN1568/D Interfacing Between LVDS and ECL AN1672/D The ECL Translator Guide AND81/D Odd Number Counters Design AND82/D Marking and Date Codes AND82/D Termination of ECL Logic Devices AND866/D Interfacing with ECLinPS AND89/D AC Characteristics of ECL Devices 18

19 MC1EP195, MC1EP195 PACKAGE DIMENSIONS 32 LEAD LFP CASE 873A 2 ISSUE C A1 32 A 25 4X.2 (.8) AB T-U Z T, U, Z T 1 U P AE B 9 SEATG PLANE B1 AB AC 8 9 S1 G S DETAIL Y Z.1 (.4) AC 17 4X V1 V.2 (.8) AC T-U Z DETAIL AD C E 8X M DETAIL Y AE R BASE METAL N ÉÉ F ÉÉ J D.2 (.8) M AC T-U Z SECTION AE AE NOTES: 1. DIMENSIONG AND TOLERANCG PER ANSI Y14.5M, CONTROLLG DIMENSION: MILLIMETER. 3. DATUM PLANE AB IS LOCATED AT BOTTOM OF LEAD AND IS COCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTG LE. 4. DATUMS T, U, AND Z TO BE DETERMED AT DATUM PLANE AB. 5. DIMENSIONS S AND V TO BE DETERMED AT SEATG PLANE AC. 6. DIMENSIONS A AND B DO NOT CLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS.25 (.1) PER SIDE. DIMENSIONS A AND B DO CLUDE MOLD MISMATCH AND ARE DETERMED AT DATUM PLANE AB. 7. DIMENSION D DOES NOT CLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED.52 (.2). 8. MIMUM SOLDER PLATE THICKNESS SHALL BE.76 (.3). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. H W DETAIL AD X MILLIMETERS CHES DIM M MAX M MAX A 7. BSC.276 BSC A1 3.5 BSC.138 BSC B 7. BSC.276 BSC B1 3.5 BSC.138 BSC C D E F G.8 BSC.31 BSC H J K M 12 REF 12 REF N P.4 BSC.16 BSC R S 9. BSC.354 BSC S1 4.5 BSC.177 BSC V 9. BSC.354 BSC V1 4.5 BSC.177 BSC W.2 REF.8 REF X 1. REF.39 REF K GAUGE PLANE.25 (.1) 19

20 MC1EP195, MC1EP195 PACKAGE DIMENSIONS FN32 5*5*1.5 P CASE 488AM 1 ISSUE O 2 X 32 X 2 X P ONE LOCATION.15 C.1 C.8 C.15 C L 32 X ÉÉ 8 D TOP VIEW SIDE VIEW (A3) A1 D E A B A C EXPOSED PAD K 32 X SEATG PLANE NOTES: 1. DIMENSIONS AND TOLERANCG PER ASME Y14.5M, CONTROLLG DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMAL AND IS MEASURED BETWEEN.25 AND.3 MM TERMAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMALS. MILLIMETERS DIM M NOM MAX A A A3.2 REF b D 5. BSC D E 5. BSC E e.5 BSC K.2 L SOLDERG FOOTPRT* E2 32 X X b.1 C A B.5 C e BOTTOM VIEW 32 X X.5 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ECLinPS is a trademark of Semiconductor Components Industries, LLC. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERG FORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 8217 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative MC1EP195/D