NB7L14M. MARKING DIAGRAM* Features
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1 2.5V/3.3V Differential :4 Clock/Data Fanout Buffer/ Translator with CML Outputs and Internal Termination Description The NB7L4M is a differential to 4 clock/data distribution chip with internal source terminated CML output structures, optimized for minimal skew and jitter. Device produces four identical output copies of clock or data operating up to 8 GHz or 2 Gb/s, respectively. As such, NB7L4M is ideal for SONET, GigE, Fiber Channel, Backplane and other clock/data distribution applications. Inputs incorporate internal termination resistors and accept LVPECL, CML, LVCMOS, LVTTL, or LVDS (See Table 6). Differential 6 ma CML outputs provide matching internal terminations, and 400 mv output swings when externally terminated with to (See Figure 4). The device is offered in a low profile 3x3 mm 6 pin FN package. Application notes, models, and support documentation are available at Features Maximum Input Clock Frequency up to 8 GHz Typical Maximum Input Data Rate up to 2 Gb/s Typical < ps of RMS Clock Jitter < ps of Data Dependent Jitter 30 ps Typical Rise and Fall Times ps Typical Propagation Delay 6 ps Typical Within Device Skew Operating Range: = V to V with = 0 V CML Output Level (400 mv Peak to Peak Output) Differential Output Only Internal Input and Output Termination Resistors Functionally Compatible with Existing 2.5 V/3.3 V LVEL, LVEP, EP and SG Devices These are Pb Free Devices V T 0 0 FN 6 MN SUFFIX CASE 485G A L Y W MARKING DIAGRAM* *For additional marking information, refer to Application Note AND8002/D. 6 NB7L 4M ALYW = Assembly Location = Wafer Lot = Year = Work Week = Pb Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page of this data sheet. 2 V T Figure. Logic Diagram Semiconductor Components Industries, LLC, 202 June, 202 Rev. 6 Publication Order Number: NB7L4M/D
2 Exposed Pad (EP) V T NB7L4M 2 V T Figure 2. FN 6 Pinout (Top View) Table. PIN DESCRIPTION Pin Name I/O Description V T Internal Termination Pin for. 2 LVPECL, CML, LVCMOS, LVTTL, LVDS 3 LVPECL, CML, LVCMOS, LVTTL, LVDS Inverted Differential Clock/Data Input. (Note ) Non inverted Differential Clock/Data Input. (Note ) 4 V T Internal Termination Pin for. 5,6 Power Supply Negative Supply Voltage. All pins must be externally connected to a Power Supply to guarantee proper operation. 6 3 CML Output Inverted Differential Output 3 with Internal Source Termination Resistor. (Note 2) 7 3 CML Output Non inverted Differential Output 3 with Internal Source Termination Resistor. (Note 2) 8,3 Power Supply Positive Supply Voltage. All pins must be externally connected to a Power Supply to guarantee proper operation. 9 2 CML Output Inverted Differential Output 2 with Internal Source Termination Resistor. (Note 2) 2 CML Output Non inverted Differential Output 2 with Internal Source Termination Resistor. (Note 2) CML Output Inverted Differential Output with Internal Source Termination Resistor. (Note 2) 2 CML Output Non inverted Differential Output with Internal Source Termination Resistor. (Note 2) 4 0 CML Output Inverted Differential Output 0 with Internal Source Termination Resistor. (Note 2) 5 0 CML Output Non inverted Differential Output 0 with Internal Source Termination Resistor. (Note 2) EP Exposed Pad. Thermal pad on the package bottom must be attached to a heatsinking conduit to improve heat transfer. It is recommended to connect the EP to the lower potential ( ).. In the differential configuration when the input termination pins (V T, V T ) are connected to a common termination voltage or left open, and if no signal is applied on and, then the device will be susceptible to self oscillation. 2. CML outputs require receiver termination resistors to for proper operation. 2
3 Table 2. ATTRIBUTES ESD Protection Characteristics Human Body Model Machine Model Charged Device Model Value > 500 V > 50 V > 500 V Moisture Sensitivity (Note 3) Pb Pkg Pb Free Pkg FN 6 Level Level Flammability Rating Oxygen Index: 28 to 34 UL 94 V 0.25 in Transistor Count 387 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, see Application Note AND8003/D. Table 3. MAXIMUM RATINGS Symbol Parameter Condition Condition 2 Rating Units Positive Power Supply = 0 V 3.6 V V I Input Voltage = 0 V V I 3.6 V V INPP Differential Input Voltage 2.8 V < 2.8 V I IN Input Current Through R T ( Resistor) Static Surge I out Output Current Continuous Surge 2.8 T A Operating Temperature Range FN 6 40 to +85 C T stg Storage Temperature Range 65 to +50 C JA Thermal Resistance (Junction to Ambient) (Note 4) 0 lfpm 500 lfpm FN 6 FN 6 JC Thermal Resistance (Junction to Case) 2S2P (Note 4) FN 6 3 to 4 C/W T sol Wave Solder Pb Pb Free Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 4. JEDEC standard multilayer board 2S2P (2 signal, 2 power) V V ma ma ma ma C/W C/W C 3
4 Table 4. DC CHARACTERISTICS, CLOCK Inputs, CML Outputs ( = V to V, = 0 V, T A = 40 C to +85 C) (Note 5) Symbol Characteristic Min Typ Max Unit I CC Power Supply Current (Inputs and Outputs Open) ma V OH Output HIGH Voltage (Note 6) mv V OL Output LOW Voltage (Note 6) mv Differential Input Driven Single Ended (see Figures & 2) (Note 8) V th Input Threshold Reference Voltage Range (Note 7) mv V IH Single ended Input HIGH Voltage 200 mv V IL Single ended Input LOW Voltage 50 mv V ISE Single Ended Input Voltage (V IH V IL ) mv Differential Inputs Driven Differentially (see Figures & 3) (Note 9) V IH Differential Input HIGH Voltage 200 mv V IL Differential Input LOW Voltage 75 mv V CMR Input Common Mode Range (Differential Configuration) (Note ) mv V ID Differential Input Voltage (V IH V IL ) mv I IH Input HIGH Current / (V T /V T Open) A I IL Input LOW Current / (V T /V T Open) 0 A R TIN Internal Input Termination Resistor R TOUT Internal Output Termination Resistor R Temp Coef Internal I/O Termination Resistor Temperature Coefficient 6.38 m / C NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and output parameters vary : with. 6. CML outputs require receiver termination resistors to for proper operation. 7. V th is applied to the complementary input when operating in single ended mode. V th = (V IH V IL )/2. 8. Vth, V IH, V IL,, and V ISE parameters must be complied with simultaneously. 9. V IHD, V ILD, V ID and V CMR parameters must be complied with simultaneously..v CMR min varies : with, V CMR max varies : with. The V CMR range is referenced to the most positive side of the differential input signal. 4
5 Table 5. AC CHARACTERISTICS ( = V to V, = 0 V; Note ) Symbol V OUTPP Characteristic Output Voltage Amplitude (@V INPPmin )f in 6 GHz (See Figure 4) f in 8 GHz 40 C 25 C 85 C Min Typ Max Min Typ Max Min Typ Max f data Maximum Operating Data Rate Gb/s t PLH, Propagation Delay to Output Differential ps t PHL Unit mv t SKEW Duty Cycle Skew (Note 2) Within Device Skew Device to Device Skew (Note 3) ps t JITTER RMS Random Clock Jitter (Note 4) f in = 6 GHz f in = 8 GHz Peak/Peak Data Dependent Jitter f in = Gb/s (Note 5) f data = 5 Gb/s f data = Gb/s V INPP Input Voltage Swing/Sensitivity (Differential Configuration) (Note 6) t r Output Rise/Fall GHz, t f (20% 80%) mv ps ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.. Measured by forcing V INPP (TYP) from a 50% duty cycle clock source. All loading with an external R L = to. Input edge rates 40 ps (20% 80%). 2.Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw and GHz. 3. Device to device skew is measured between outputs under identical GHz. 4.Additive RMS jitter with 50% duty cycle clock signal at GHz. 5.Additive peak to peak data dependent jitter with input NR data at PRBS 2^23. 6.V INPP (MAX) cannot exceed. Input voltage swing is a single ended measurement operating in differential mode. OUTPUT VOLTAGE AMPLITUDE (mv) = 3.3 V = 2.5 V INPUT FREUENCY (GHz) Figure 3. Output Voltage Amplitude (V OUTPP ) versus Input Clock Frequency (f in ) at Ambient Temperature (Typical) (V INPP = 400 mv) 5
6 Voltage (50 mv/div) DDJ =.6 ps* Voltage (50 mv/div) DDJ = 2.8 ps** Time (80 ps/div) Time (40 ps/div) Figure 4. Typical Output Waveform at Gb/s with PRBS 2^23 (V inpp = 75 mv) Figure 5. Typical Output Waveform at 5 Gb/s with PRBS 2^23 (V inpp = 75 mv) *Input signal DDJ = 6.4 ps **Input signal DDJ = 7.2 ps Voltage (50 mv/div) DDJ = 2 ps*** Voltage (50 mv/div) DDJ = 6 ps*** Time (8 ps/div) Time (8.2 ps/div) Figure 6. Typical Output Waveform at.7 Gb/s with PRBS 2^23 (V inpp = 75 mv) Figure 7. Typical Output Waveform at 2 Gb/s with PRBS 2^23 (V inpp = 75 mv) ***Input signal DDJ = ps ***Input signal DDJ = 3 ps 6
7 V INPP = V IH () V IL () V OUTPP = V OH () V OL () t PHL t PLH Figure 8. AC Reference Measurement NB7L4M Receiver Device = = Figure 9. Typical Termination for 6 ma Output Driver and Device Evaluation (Refer to Application Notes AND8020/D and AND873/D) V th V th Figure. Differential Input Driven Single Ended Figure. Differential Inputs Driven Differentially Vthmax V th V IHmax V ILmax V IH V th V IL V CMmax V CMR V IHmax V ILmax V () = V IH V IL V IHtyp V ILtyp V thmin GND V IHmin V ILmin V CMmax GND V IHmin V ILmin Figure 2. V th Diagram Figure 3. V CMR Diagram 7
8 6 ma Figure 4. CML Output Structure Table 6. INTERFACING OPTIONS INTERFACING OPTIONS CML LVDS AC COUPLED RSECL, LVPECL LVTTL, LVCMOS CONNECTIONS Connect V T and V T to Connect V T, V T Together for Input Bias V T, V T Inputs within (VCMR) Common Mode Range Standard ECL Termination Techniques. See AND8020/D. An external voltage should be applied to the unused complementary differential input. Nominal voltage is.5 V for LVTTL and /2 for LVCMOS inputs. 8
9 Application Information All NB7L4M inputs can accept PECL, CML, LVTTL, LVCMOS and LVDS signal levels. The limitations for differential input signal (LVDS, PECL, or CML) are minimum input swing of 75 mv and the maximum input swing of 2500 mv. Within these conditions, the input voltage can range from to.2 V. Examples interfaces are illustrated below in a environment ( = ). CML Driver V T NB7L4M V T Figure 5. CML to CML Interface Recommended R T Values R T PECL Driver V Bias V Bias V T V T NB7L4M V 290 R T R T 3.3 V 2.5 V 80 Figure 6. PECL to CML Receiver Interface 9
10 LVDS Driver V T NB7L4M V T Figure 7. LVDS to CML Receiver Interface LVTTL/ LVCMOS Driver No Connect* No Connect V REF *or 60 pf to GND V T V T Figure 8. LVCMOS/LVTTL to CML Receiver Interface NB7L4M Recommended V REF Values LVCMOS LVTTL V REF 2.5 V ORDERING INFORMATION Device Package Shipping NB7L4MMNG FN 6 (Pb Free) 23 Units/Rail NB7L4MMNR2G FN 6 (Pb Free) 3000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD80/D.
11 PACKAGE DIMENSIONS FN6 3x3, P CASE 485G ISSUE F 2X PIN LOCATION 2X NOTE 4 0. C 0.05 C 0.05 C 0. C DETAIL A 6X L D ÇÇÇ ÇÇÇ TOP VIEW DETAIL B SIDE VIEW D2 8 (A3) A B E A A C 0. C A B L EXPOSED Cu SEATING PLANE L DETAIL A ALTERNATE TERMINAL CONSTRUCTIONS ÉÉÉ MOLD CMPD A DETAIL B ALTERNATE CONSTRUCTIONS PACKAGE OUTLINE L ÉÉ A3 NOTES:. DIMENSIONING AND TOLERANCING PER ASME Y4.5M, CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 5 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS DIM MIN NOM MAX A A A3 0 REF b D 3.00 BSC D E 3.00 BSC E e 0 BSC K 0.8 TYP L L RECOMMENDED SOLDERING FOOTPRINT* 6X X K 6 e e/2 BOTTOM VIEW E2 6X b 0. C 0.05 C A B NOTE 3 6X X 2X PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 563, Denver, Colorado 8027 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative NB7L4M/D
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Schottky Barrier Diode Schottky barrier diodes are optimized for very low forward voltage drop and low leakage current and are used in a wide range of dc dc converter, clamping and protection applications
NTK3139P. Power MOSFET. 20 V, 780 ma, Single P Channel with ESD Protection, SOT 723
NTK9P Power MOSFET V, 78 ma, Single P Channel with ESD Protection, SOT 7 Features P channel Switch with Low R DS(on) % Smaller Footprint and 8% Thinner than SC 89 Low Threshold Levels Allowing.5 V R DS(on)
MC100EPT22/D. MARKING DIAGRAMS* ORDERING INFORMATION SO 8 D SUFFIX CASE 751 KPT22 ALYW TSSOP 8 DT SUFFIX CASE 948R KA22 ALYW
The MC00EPT22 is a dual LVTTL/LVCMOS to differential LVPECL translator. Because LVPECL (Positive ECL) levels are used only +3.3 V and ground are required. The small outline lead package and the single
NSVEMD4DXV6T5G. Dual Bias Resistor Transistors. NPN and PNP Silicon Surface Mount Transistors with Monolithic Bias Resistor Network
Dual Bias Resistor Transistors NPN and PNP Silicon Surface Mount Transistors with Monolithic Bias Resistor Network The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias
NB4L V / 3.3V Differential LVPECL 2x2 Clock Switch and Low Skew Fanout Buffer
2.5V / 3.3V Differential LVPECL 2x2 Clock Switch and Low Skew Fanout Buffer Description The NB4L6254 is a differential 2x2 clock switch and drives precisely aligned clock signals through its LVPECL fanout
MC GHz Low Power Prescaler With Stand-By Mode
2.5 GHz Low Power Prescaler With Stand-By Mode Description The M1295 is a single modulus prescaler for low power frequency division of a 2.5 GHz high frequency input signal. MOSAI V technology is utilized
NCP304A. Voltage Detector Series
Voltage Detector Series The NCP0A is a second generation ultralow current voltage detector. This device is specifically designed for use as a reset controller in portable microprocessor based systems where
NTJD1155LT1G. Power MOSFET. 8 V, 1.3 A, High Side Load Switch with Level Shift, P Channel SC 88
NTJDL Power MOSFET V,.3 A, High Side Load Switch with Level Shift, P Channel SC The NTJDL integrates a P and N Channel MOSFET in a single package. This device is particularly suited for portable electronic
NTLUS3A90PZ. Power MOSFET 20 V, 5.0 A, Cool Single P Channel, ESD, 1.6x1.6x0.55 mm UDFN Package
NTLUS3A9PZ Power MOSFET V, 5. A, Cool Single P Channel, ESD,.x.x.55 mm UDFN Package Features UDFN Package with Exposed Drain Pads for Excellent Thermal Conduction Low Profile UDFN.x.x.55 mm for Board Space
NTTFS3A08PZTWG. Power MOSFET 20 V, 15 A, Single P Channel, 8FL
NTTFS3A8PZ Power MOSFET V, 5 A, Single P Channel, 8FL Features Ultra Low R DS(on) to Minimize Conduction Losses 8FL 3.3 x 3.3 x.8 mm for Space Saving and Excellent Thermal Conduction ESD Protection Level
MC10ELT22, MC100ELT22. 5VНDual TTL to Differential PECL Translator
5VНual TTL to ifferential PECL Translator The MC0ELT/00ELT22 is a dual TTL to differential PECL translator. Because PECL (Positive ECL) levels are used only +5 V and ground are required. The small outline
NTLUD3A260PZ. Power MOSFET 20 V, 2.1 A, Cool Dual P Channel, ESD, 1.6x1.6x0.55 mm UDFN Package
NTLUDAPZ Power MOSFET V,. A, Cool Dual P Channel, ESD,.x.x. mm UDFN Package Features UDFN Package with Exposed Drain Pads for Excellent Thermal Conduction Low Profile UDFN.x.x. mm for Board Space Saving
NTK3043N. Power MOSFET. 20 V, 285 ma, N Channel with ESD Protection, SOT 723
NTKN Power MOSFET V, 8 ma, N Channel with ESD Protection, SOT 7 Features Enables High Density PCB Manufacturing % Smaller Footprint than SC 89 and 8% Thinner than SC 89 Low Voltage Drive Makes this Device
MUN5216DW1, NSBC143TDXV6. Dual NPN Bias Resistor Transistors R1 = 4.7 k, R2 = k. NPN Transistors with Monolithic Bias Resistor Network
MUN526DW, NSBC43TDXV6 Dual NPN Bias Resistor Transistors R = 4.7 k, R2 = k NPN Transistors with Monolithic Bias Resistor Network This series of digital transistors is designed to replace a single device
NBXSBA024, NBXSBB024, NBXMBB V / 3.3 V, MHz LVPECL Clock Oscillator
NBXSBA0, NBXSBB0, NBXMBB0.5 V /. V, 6.08 MHz LVPECL Clock Oscillator The single frequency, crystal oscillator (XO) is designed to meet today s requirements for.5 V /. V LVPECL clock generation applications.
NLAS5157. Ultra-Low 0.4 SPDT Analog Switch
Ultra-Low.4 SPDT Analog Switch The NLAS5157 is Single Pole Double Throw (SPDT) switch designed for audio systems in portable applications. The NLAS5157 features Ultra Low R ON of.4 typical at = V and.15
MC100EPT V LVTTL/LVCMOS to LVPECL Translator
MCEPT622 3.3V VTT/VCMOS to VPEC Translator Description The MCEPT622 is a 0 Bit VTT/VCMOS to VPEC translator. Because VPEC (Positive EC) levels are used only +3.3 V and ground are required. The device has
LM339S, LM2901S. Single Supply Quad Comparators
LM339S, LM290S Single Supply Quad Comparators These comparators are designed for use in level detection, low level sensing and memory applications in consumer and industrial electronic applications. Features
PIN CONNECTIONS MAXIMUM RATINGS (T J = 25 C unless otherwise noted) SC 75 (3 Leads) Parameter Symbol Value Unit Drain to Source Voltage V DSS 30 V
NTA7N, NVTA7N Small Signal MOSFET V, 4 ma, Single, N Channel, Gate ESD Protection, SC 7 Features Low Gate Charge for Fast Switching Small.6 x.6 mm Footprint ESD Protected Gate NV Prefix for Automotive
NLAS7222B, NLAS7222C. High-Speed USB 2.0 (480 Mbps) DPDT Switches
High-Speed USB 2.0 (480 Mbps) DPDT Switches ON Semiconductor s NLAS7222B and NLAS7222C are part of a series of analog switch circuits that are produced using the company s advanced sub micron CMOS technology,
NTTFS5116PLTWG. Power MOSFET 60 V, 20 A, 52 m. Low R DS(on) Fast Switching These Devices are Pb Free and are RoHS Compliant
Power MOSFET 6 V, 2 A, 52 m Features Low R DS(on) Fast Switching These Devices are Pb Free and are RoHS Compliant Applications Load Switches DC Motor Control DC DC Conversion MAXIMUM RATINGS ( unless otherwise
MJD44H11 (NPN) MJD45H11 (PNP) Complementary Power Transistors. DPAK For Surface Mount Applications
MJDH (NPN) MJD5H (PNP) Complementary Power Transistors For Surface Mount Applications Designed for general purpose power and switching such as output or driver stages in applications such as switching
NTNUS3171PZ. Small Signal MOSFET. 20 V, 200 ma, Single P Channel, 1.0 x 0.6 mm SOT 1123 Package
NTNUS7PZ Small Signal MOSFET V, ma, Single P Channel,. x.6 mm SOT Package Features Single P Channel MOSFET Offers a Low R DS(on) Solution in the Ultra Small. x.6 mm Package. V Gate Voltage Rating Ultra
NBXDBA V, 75 MHz / 150 MHz LVPECL Clock Oscillator
. V, 75 MHz / 150 MHz LVPECL Clock Oscillator The NBXBA009 dual frequency crystal oscillator (XO) is designed to meet today s requirements for. V LVPECL clock generation applications. The device uses a
MRA4003T3G Series, NRVA4003T3G Series. Surface Mount Standard Recovery Power Rectifier. SMA Power Surface Mount Package
MRA43T3G Series, NRVA43T3G Series Surface Mount Standard Recovery Power Rectifier Power Surface Mount Package Features construction with glass passivation. Ideally suited for surface mounted automotive
MJD44H11 (NPN) MJD45H11 (PNP)
MJDH (NPN) MJD5H (PNP) Preferred Device Complementary Power Transistors For Surface Mount Applications Designed for general purpose power and switching such as output or driver stages in applications such
PCS2P2309/D. 3.3V 1:9 Clock Buffer. Functional Description. Features. Block Diagram
3.3V 1:9 Clock Buffer Features One-Input to Nine-Output Buffer/Driver Buffers all frequencies from DC to 133.33MHz Low power consumption for mobile applications Less than 32mA at 66.6MHz with unloaded
MC100EPT V LVTTL/LVCMOS to LVPECL Translator Description The MC100EPT622 is a 10- Bit LVTTL/LVCMOS to LVPECL translator. Because LVPECL (Positiv
3.3V VTT/VCMOS to VPEC Translator Description The is a 0- Bit VTT/VCMOS to VPEC translator. Because VPEC (Positive EC) levels are used only +3.3 V and ground are required. The device has an OR- ed enable
NTLUF4189NZ Power MOSFET and Schottky Diode
NTLUF89NZ Power MOSFET and Schottky Diode V, N Channel with. A Schottky Barrier Diode,. x. x. mm Cool Package Features Low Qg and Capacitance to Minimize Switching Losses Low Profile UDFN.x. mm for Board
MUN5332DW1, NSBC143EPDXV6, NSBC143EPDP6. Complementary Bias Resistor Transistors R1 = 4.7 k, R2 = 4.7 k
MUN5DW, NSBCEPDXV6, NSBCEPDP6 Complementary Bias Resistor Transistors R =.7 k, R =.7 k NPN and PNP Transistors with Monolithic Bias Resistor Network () PIN CONNECTIONS () () This series of digital transistors
NLAS7213. High-Speed USB 2.0 (480 Mbps) DPST Switch
High-Speed USB 2.0 (480 Mbps) DPST Switch The NLAS723 is a DPST switch optimized for high speed USB 2.0 applications within portable systems. It features ultra low off capacitance, C OFF = 3.0 pf (typ),
MC3488A. Dual EIA 423/EIA 232D Line Driver
Dual EIA423/EIA232D Line Driver The MC34A dual is singleended line driver has been designed to satisfy the requirements of EIA standards EIA423 and EIA232D, as well as CCITT X.26, X.2 and Federal Standard
NUF8401MNT4G. 8-Channel EMI Filter with Integrated ESD Protection
8-Channel EMI Filter with Integrated ESD Protection The NUF841MN is an eight channel (C R C) Pi style EMI filter array with integrated ESD protection. Its typical component values of R = 1 and C = 12 pf
MC100EP16VS. 3.3V / 5V ECL Differential Receiver/Driver with Variable Output Swing
3.3V / 5V ECL ifferential Receiver/river with Variable Output Swing escription The MC00EP6VS is a differential receiver with variable output amplitude. The device is functionally equivalent to the 00EP6
PZTA92T1. High Voltage Transistor. PNP Silicon SOT 223 PACKAGE PNP SILICON HIGH VOLTAGE TRANSISTOR SURFACE MOUNT
High Voltage Transistor PNP Silicon Features These Devices are Pb Free, Halogen Free/BFR Free and are RoHS Compliant MAXIMUM RATINGS (T C = 25 C unless otherwise noted) Rating Symbol Value Unit Collector-Emitter
MUN5311DW1T1G Series.
MUNDWTG Series Preferred Devices Dual Bias Resistor Transistors NPN and PNP Silicon Surface Mount Transistors with Monolithic Bias Resistor Network The Bias Resistor Transistor (BRT) contains a single
NTTFS5820NLTWG. Power MOSFET. 60 V, 37 A, 11.5 m. Low R DS(on) Low Capacitance Optimized Gate Charge These Devices are Pb Free and are RoHS Compliant
NTTFS582NL Power MOSFET 6 V, 37 A,.5 m Features Low R DS(on) Low Capacitance Optimized Gate Charge These Devices are Pb Free and are RoHS Compliant MAXIMUM RATINGS ( unless otherwise stated) Parameter
NSBC114EDP6T5G Series. Dual Digital Transistors (BRT) NPN Silicon Surface Mount Transistors with Monolithic Bias Resistor Network
Preferred Devices Dual Digital Transistors (BRT) NPN Silicon Surface Mount Transistors with Monolithic Bias Resistor Network This new series of digital transistors is designed to replace a single device
MC10E V, -5V Dual ECL Output Comparator with Latch
5V, -5V Dual ECL Output Comparator with Latch The MC10E1652 is fabricated using ON Semiconductor s advanced MOSAIC III process and is output compatible with 10H logic devices. In addition, the device is
NCN1154. DP3T USB 2.0 High Speed / Audio Switch with Negative Swing Capability
DP3T USB 2.0 High Speed / Audio Switch with Negative Swing Capability The NCN1154 is a DP3T switch for combined true ground audio, USB 2.0 high speed data, and UART applications. It allows portable systems
NBXDBA019, NBXHBA019, NBXSBA V, 125 MHz / 250 MHz LVPECL Clock Oscillator
NBXBA019, NBXHBA019, NBXSBA019. V, 15 MHz / 50 MHz LVPECL Clock Oscillator The single and dual frequency crystal oscillator (XO) is designed to meet today s requirements for. V LVPECL clock generation
NTA4001N, NVA4001N. Small Signal MOSFET. 20 V, 238 ma, Single, N Channel, Gate ESD Protection, SC 75
Small Signal MOSFET V, 8 ma, Single, N Channel, Gate ESD Protection, SC 75 Features Low Gate Charge for Fast Switching Small.6 x.6 mm Footprint ESD Protected Gate AEC Q Qualified and PPAP Capable NVA4N
Distributed by: www.jameco.com 1-800-831-44 The content and copyrights of the attached material are the property of its owner. Transient Voltage Suppressors Micro Packaged Diodes for ESD Protection The
MC10E V, 5V Dual ECL Output Comparator with Latch
5V, 5V Dual ECL Output Comparator with Latch The MC10E1651 is fabricated using ON Semiconductor s advanced MOSAIC III process. The MC10E1651 incorporates a fixed level of input hysteresis as well as output
NTS4172NT1G. Power MOSFET. 30 V, 1.7 A, Single N Channel, SC 70. Low On Resistance Low Gate Threshold Voltage Halide Free This is a Pb Free Device
Power MOSFET V,.7 A, Single N Channel, SC 7 Features Low On Resistance Low Gate Threshold Voltage Halide Free This is a Pb Free Device V (BR)DSS R DS(on) MAX I D MAX Applications Low Side Load Switch DC
NCN1154. USB 2.0 High Speed, UART and Audio Switch with Negative Signal Capability
USB 2.0 High Speed, UART and Audio Switch with Negative Signal Capability The NCN1154 is a DP3T switch for combined true ground audio, USB 2.0 high speed data, and UART applications. It allows portable
NBXDBA V, 62.5 MHz / 125 MHz LVPECL Clock Oscillator
. V, 62.5 MHz / 125 MHz LVPECL Clock Oscillator The NBXBA014 dual frequency crystal oscillator (XO) is designed to meet today s requirements for. V LVPECL clock generation applications. The device uses
MUN5211T1 Series. NPN Silicon Surface Mount Transistor with Monolithic Bias Resistor Network NPN SILICON BIAS RESISTOR TRANSISTORS
MUNT Series Preferred Devices Bias Resistor Transistor NPN Silicon Surface Mount Transistor with Monolithic Bias Resistor Network This new series of digital transistors is designed to replace a single
NUF8001MUT2G. 8-Channel EMI Filter with Integrated ESD Protection
8-Channel EMI Filter with Integrated ESD Protection The NUF8MU is a eight channel (C R C) Pi style EMI filter array with integrated ESD protection. Its typical component values of R = and C = 2 pf deliver
MMBTA06W, SMMBTA06W, Driver Transistor. NPN Silicon. Moisture Sensitivity Level: 1 ESD Rating: Human Body Model 4 kv ESD Rating: Machine Model 400 V
Driver Transistor NPN Silicon Moisture Sensitivity Level: 1 ESD Rating: Human Body Model 4 kv ESD Rating: Machine Model 400 V Features S Prefix for Automotive and Other Applications Requiring Unique Site
NTGD4167C. Power MOSFET Complementary, 30 V, +2.9/ 2.2 A, TSOP 6 Dual
Power MOSFET Complementary, 3 V, +.9/. A, TSOP 6 Dual Features Complementary N Channel and P Channel MOSFET Small Size (3 x 3 mm) Dual TSOP 6 Package Leading Edge Trench Technology for Low On Resistance
MMBZxxVAWT1G Series, SZMMBZxxVAWT1G Series. 40 Watt Peak Power Zener Transient Voltage Suppressors. SC 70 Dual Common Anode Zeners for ESD Protection
MMBZxxVAWTG Series, SZMMBZxxVAWTG Series 4 Watt Peak Power Zener Transient Voltage Suppressors SC 7 Dual Common Anode Zeners for ESD Protection These dual monolithic silicon Zener diodes are designed for
NTJS4405N, NVJS4405N. Small Signal MOSFET. 25 V, 1.2 A, Single, N Channel, SC 88
NTJSN, NVJSN Small Signal MOSFET V,. A, Single, N Channel, SC 88 Features Advance Planar Technology for Fast Switching, Low R DS(on) Higher Efficiency Extending Battery Life AEC Q Qualified and PPAP Capable
NGB18N40CLB, NGB18N40ACLB. Ignition IGBT 18 Amps, 400 Volts. N Channel D 2 PAK. 18 AMPS, 400 VOLTS V CE(on) 2.0 I C = 10 A, V GE 4.
NGB8N4CLB, NGB8N4ACLB Ignition IGBT 8 Amps, 4 Volts N Channel D PAK This Logic Level Insulated Gate Bipolar Transistor (IGBT) features monolithic circuitry integrating ESD and Over Voltage clamped protection
NSQA6V8AW5T2 Series Transient Voltage Suppressor
Transient Voltage Suppressor ESD Protection Diode with Low Clamping Voltage This integrated transient voltage suppressor device (TVS) is designed for applications requiring transient overvoltage protection.