NB7V52M. 1.8V / 2.5V Differential D Flip-Flop w/ Reset and CML Outputs. Multi Level Inputs w/ Internal Termination

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1 1.8V / 2.5V ifferential Flip-Flop w/ Reset and CML Outputs Multi Level Inputs w/ Internal Termination escription The is a 10 GHz differential flip flop with a differential asynchronous Reset. The differential /, / and R/R inputs incorporate dual internal termination resistors and will accept LVPECL, CML, LVS logic levels. When Clock transitions from logic Low to High, ata will be transferred to the differential CML outputs. The differential Clock inputs allow the to also be used as a negative edge triggered device. The 16 ma differential CML outputs provide matching internal termination and produce 400 mv output swings when externally receiver terminated with a resistor to. The is offered in a low profile 3 mm x 3 mm 16 pin FN package. The is a member of the GigaComm family of high performance clock products. Application notes, models, and support documentation are available at Features Maximum Input Clock Frequency > 10 GHz Maximum Input ata Rate > 10 Gb/s Random Clock Jitter < 0.8 ps RMS, Max 200 ps Typical Propagation elay 35 ps Typical Rise and Fall Times ifferential CML Outputs, 400 mv Peak to Peak, Typical Operating Range: = 1.71 V to V with = 0 V Internal Input Termination Resistors FN 16 Package, 3mm x 3mm 40 C to +85 C Ambient Operating Temperature These are Pb Free evices 1 FN 16 MN SUFFIX CASE 485G MARKING IAGRAM* A = Assembly Location L = Wafer Lot Y = Year W = Work Week = Pb Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AN8002/. VT VT VT VT 1 16 Flip Flop RESET NB7V 52M ALYW VTR R R VTR Figure 1. Logic iagram ORERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. Semiconductor Components Industries, LLC, 2009 September, 2009 Rev. 3 1 Publication Order Number: /

2 VTR R R VTR Exposed Pad (EP) Table 1. INPUT/OUTPUT SELECT TRUTH TABLE R VT 1 12 VCC H x x L L L Z L L H Z H Z = LOW to HIGH Transition x = on t care VT 4 9 VEE VT VT Figure 2. Pin Configuration (Top View) Table 1. Pin escription Pin Name I/O escription 1 VT Internal Termination Pin for 2 LVPECL, CML, LVS Input 3 LVPECL, CML, LVS Input Noninverted ifferential ata Input. (Note 1) Inverted ifferential ata Input. (Note 1) 4 VT Internal Termination Pin for 5 VT Internal Termination Pin for 6 LVPECL, CML, LVS Input 7 LVPECL, CML, LVS Input Noninverted ifferential Clock Input. (Note 1) Inverted ifferential Clock Input. (Note 1) 8 VT Internal Termination Pin for 9 VEE Negative Supply Voltage. (Note 2) 10 CML Output Inverted ifferential Output 11 CML Output Noninverted ifferential Output 12 VCC Positive Supply Voltage. (Note 2) 13 VTR Internal Termination Pin for R 14 R LVPECL, CML, LVS Input 15 R LVPECL, CML, LVS Input Noninverted Asynchronous ifferential Reset Input. (Note 1) Inverted Asynchronous ifferential Reset Input. (Note 1) 16 VTR Internal Termination Pin for R EP The Exposed Pad (EP) on the FN 16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat sinking conduit. The pad is not electrically connected to the die, but is recommended to be electrically and thermally connected to VEE on the PC board. 1. In the differential configuration when the input termination pins (VTx, VTx) are connected to a common termination voltage or left open, and if no signal is applied on / input, then the device will be susceptible to self oscillation. 2. All VCC and GN pins must be externally connected to a power supply for proper operation. 2

3 Table 2. ATTRIBUTES Characteristics Value ES Protection Human Body Model Machine Model > 2 kv > 200 V Moisture Sensitivity 16 FN Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V in Transistor Count 173 Meets or exceeds JEEC Spec EIA/JES78 IC Latchup Test For additional information, see Application Note AN8003/. Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit Positive Power Supply = 0 V 3.0 V V IO Positive Input/Output Voltage = 0 V 0.5 VIO VCC to +0.5 V V INPP ifferential Input Voltage,, R R 1.89 V I OUT Output Current Through R TOUT ( Resistor) Continuous Surge ma I IN Input Current Through R TIN ( Resistor) 40 ma T A Operating Temperature Range 40 to +85 C T stg Storage Temperature Range 65 to +150 C JA Thermal Resistance (Junction to Ambient) (Note 3) 0 lfpm 500 lfpm FN 16 FN C/W C/W JC Thermal Resistance (Junction to Case) (Note 3) FN 16 4 C/W T sol Wave Solder Pb Free 265 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 3. JEEC standard multilayer board 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. 3

4 Table 4. C CHARACTERISTICS, Multi Level Inputs = 1.71 V to V, = 0 V, T A = 40 C to +85 C (Note 4) Symbol Characteristic Min Typ Max Unit POWER SUPPLY CURRENT I CC Power Supply Current (Inputs and Outputs Open) = 2.5 V = 1.8 V ma CML OUTPUTS V OH Output HIGH Voltage (Note 5) = 2.5 V = 1.8 V mv V OL Output LOW Voltage (Note 5) = 2.5 V mv = 1.8 V IFFERENTIAL CLOCK INPUTS RIVEN SINGLE ENE (Note 6) (Figures 5 and 7) Input Threshold Reference Voltage Range (Note 7) mv V IH Single Ended Input HIGH Voltage mv V IL Single Ended Input LOW Voltage 100 mv V ISE Single Ended Input Voltage (V IH V IL ) mv IFFERENTIAL /, /, R/R INPUTS RIVEN IFFERENTIALLY (Figures 6 and 8) (Note 8) V IH ifferential Input HIGH Voltage 1100 mv V IL ifferential Input LOW Voltage 100 mv V I ifferential Input Voltage (V IH V IL ) mv V CMR Input Common Mode Range (ifferential Configuration, Note 9) (Figure 10) mv I IH Input HIGH Current (VT x /VT x Open) 250 2A I IL Input LOW Current (VT x /VT x Open) 250 2A TERMINATION RESISTORS R TIN Internal Input Termination Resistor R TOUT Internal Output Termination Resistor NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. Input and output parameters vary 1:1 with. 5. CML outputs loaded with to for proper operation. 6., V IH, V IL,, and V ISE parameters must be complied with simultaneously. 7. is applied to the complementary input when operating in single ended mode. 8. V IH, V IL, V I and V CMR parameters must be complied with simultaneously. 9. V CMR min varies 1:1 with, V CMR max varies 1:1 with. The V CMR range is referenced to the most positive side of the differential input signal. 4

5 Table 5. AC CHARACTERISTICS = 1.71 V to V; = 0 V; T A = 40 C to 85 C (Note 10) Symbol Characteristic Min Typ Max Unit f MAX Maximum Input Clock Frequency GHz f ATA MAX Maximum Input ata Rate (PRBS23) Gbps V OUTPP Output Voltage Amplitude (@ V INPPmin ) fin 7 GHz (See Figures 3 and 10, Note 11) fin 10 GHz mv t PLH, t PHL Propagation elay to ifferential 1 GHz, Measured at ifferential Cross point / to / R/R to / ps t S Setup Time ( to ) ps t H Hold Time ( to ) ps t RR Reset Recovery ps t PW Minimum Pulse Width R/R 1 ns t JITTER RJ Output Random Jitter (Note 12) fin 10 GHz ps RMS V INPP Input Voltage Swing (ifferential Configuration) (Note 13) mv t r,, t f Output Rise/Fall 1 GHz (20% 80%),, ps NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10.Measured using a 400 mv V INPP source, 50% duty cycle clock source. All output loading with external to. Input edge rates 40 ps (20% 80%). 11. Output voltage swing is a single ended measurement operating in differential mode. 12. Additive RMS jitter with 50% duty cycle clock signal. 13. Input voltage swing is a single ended measurement operating in differential mode. OUTPUT VOLTAGE AMPLITUE (mv) / Output fin, Clock Input Frequency (GHz) Figure 3. Clock Output Voltage Amplitude (V OUTPP ) vs. Input Frequency (f in ) at Ambient Temperature (Typ) VT R TIN R C R C I R TIN VT Figure 4. Simplified Input Structure 5

6 V IH //R V IL //R Figure 5. ifferential Input riven Single Ended Figure 6. ifferential Inputs riven ifferentially max V IHmax V ILmax V IH V IL V I = V IH() V IL() V IH V IL min V IHmin V ILmin Figure 7. iagram Figure 8. ifferential Inputs riven ifferentially V IHmax V CMRmax V CMR V CMRmin V ILmax V IHtyp V I = V IH V IL V ILtyp V IHmin V INPP = V IH () V IL () V OUTPP = V OH () V OL () t PHL V ILmin t PLH Figure 9. V CMR iagram Figure 10. AC Reference Measurement 6

7 Receiver R TOUT R TOUT 16 ma Figure 11. Typical CML Output Structure and Termination UT river evice Z = Z = Receiver evice Figure 12. Typical Termination for CML Output river and evice Evaluation 7

8 Z O = Z O = LVPECL river Z O = V T V T LVS river Z O = V T V T = 2 V GN/ Figure 13. LVPECL Interface GN Figure 14. LVS Interface Z O = CML river Z O = V T V T V T = V T = GN Figure 15. Standard Load CML Interface Z O = Z O = ifferential river Z O = V T V T Single Ended river V T V T = External V REFAC = External V REFAC GN/ GN/ Figure 16. Capacitor Coupled ifferential Interface (V T /V T Connected to External V REFAC ; V REFAC Bypassed to Ground with 0.1 F Capacitor) Figure 17. Capacitor Coupled Single Ended Interface (V T /V T Connected to External V REFAC ; V REFAC Bypassed to Ground with 0.1 F Capacitor) 8

9 ORERING INFORMATION MNG evice Package Shipping FN 16 (Pb free) 123 Units / Rail MNHTBG FN 16 (Pb free) 100 / Tape & Reel MNTXG FN 16 (Pb free) 3000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BR8011/. 9

10 PACKAGE IMENSIONS 16 PIN FN CASE 485G 01 ISSUE PIN 1 LOCATION ÇÇÇ ÇÇÇ A B E L1 L ETAIL A ALTERNATE TERMINAL CONSTRUCTIONS L NOTES: 1. IMENSIONING AN TOLERANCING PER ASME Y14.5M, CONTROLLING IMENSION: MILLIMETERS. 3. IMENSION b APPLIES TO PLATE TERMINAL AN IS MEASURE BETWEEN 0.25 AN 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSE PA AS WELL AS THE TERMINALS. 5. L max CONITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEA TIP AN FLAG 16 X 0.15 C 0.10 C 0.08 C 0.15 C TOP VIEW ETAIL B SIE VIEW (A3) A1 A EXPOSE Cu C SEATING PLANE ÉÉ MOL CMP A1 ETAIL B ALTERNATE CONSTRUCTIONS ÇÇ A3 MILLIMETERS IM MIN MAX A A A REF b BSC E 3.00 BSC E e 0.50 BSC K 0.18 TYP L L SOLERING FOOTPRINT* 16X L NOTE 5 ETAIL A e EXPOSE PA EXPOSE PA X K 1 16X b 0.10 C A B 0.05 C NOTE BOTTOM VIEW e 12 E SCALE 10: mm inches *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLERRM/. The products described herein (), may be covered by U.S. patents including 6,362,644. There may be other patents pending. GigaComm is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORERING INFORMATION LITERATURE FULFILLMENT: Literature istribution Center for ON Semiconductor P.O. Box 5163, enver, Colorado USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center Kamimeguro, Meguro ku, Tokyo, Japan Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative. /