NB3N853531E. 3.3 V Xtal or LVTTL/LVCMOS Input 2:1 MUX to 1:4 LVPECL Fanout Buffer
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1 3.3 V Xtal or LVTTL/LVCMOS Input 2:1 MUX to 1:4 LVPECL Fanout Buffer Description The NB3N853531E is a low skew 3.3 V supply 1:4 clock distribution fanout buffer. An input MUX selects either a Fundamental Parallel Mode Crystal or a LVCMOS/LVTTL Clock by using the CLK_SEL pin (HIGH for Crystal, LOW for Clock) with LVCMOS / LVTTL levels. The single ended CLK input is translated to four LVPECL Outputs. Using the crystal input, the NB3N853531E can be a Clock Generator. A CLK_EN pin can enable or disable the outputs synchronously to eliminate runt pulses using LVCMOS/LVTTL levels (HIGH to enable outputs, LOW to disable outputs). Features Four Differential 3.3 V LVPECL Outputs Selectable Crystal or LVCMOS/LVTTL CLOCK Inputs Up to 266 MHz Clock Operation Output to Output Skew: 30 ps (Max) Device to Device Skew 200 ps (Max) Propagation Delay 1.8 ns (Max) Operating Range: V CC = 3.3 ±5% V( to V) Additive Phase Jitter, RMS: ps (Typ) Synchronous Clock Enable Control Industrial Temp. Range ( 40 C to 85 C) Pb Free TSSOP 20 Package Ambient Operating Temperature Range 40 C to +85 C These are Pb Free Devices TSSOP 20 DT SUFFIX CASE 948E A L Y W = Assembly Location = Wafer Lot = Year = Work Week = Pb Free Package MARKING DIAGRAM NB3N 531E ALYW (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. CLK_EN Pullup D Q Q0 CLK Pulldown 0 Q0 XTAL_IN XTAL_OUT OSC 1 Q1 Q1 Q2 CLK_SEL Pulldown Q2 Q3 Q3 Figure 1. Simplified Logic Diagram Semiconductor Components Industries, LLC, 2012 March, 2012 Rev. 6 1 Publication Order Number: NB3N853531E/D
2 V EE 1 20 Q0 CLK_EN 2 19 Q0 CLK_SEL 3 18 V CC CLK 4 17 Q1 nc 5 16 Q1 XTAL_IN XTAL_OUT Q2 Q2 nc nc V CC Q3 V CC Q3 Figure 2. Pinout Diagram (Top View) Table 1. PIN DESCRIPTION Pin Name I/O Open Default Description 1 V EE Negative (Ground) Power Supply pin must be externally connected to power supply to guarantee proper operation. 2 CLK_EN LVCMOS / LVTTL 3 CLK_SEL LVCMOS / LVTTL 4 CLK LVCMOS / LVTTL Pullup Pulldown Pulldown Synchronized Clock Enable when HIGH. When LOW, outputs are disabled (Qx HIGH, Qx LOW) Clock Input Select (HIGH selects crystal, LOW selects CLK input) Clock Input. Float open when unused. 5, 8, 9 nc No Connect 6 XTAL_IN Crystal Crystal Oscillator Input (used with pin 7). Float open when unused. 7 XTAL_OUT Crystal Crystal Oscillator Output (used with pin 6). Float open when unused. 10, 13, 18 V CC Positive Power Supply pins must be externally connected to power supply to guarantee proper operation. 11, 14, 16, 19 12, 15, 17, 20 Q[3:0] LVPECL Complement Differential Outputs (See AND8020 for termination) Q[3:0] LVPECL True Differential Outputs (See AND8020 for termination) Table 2. FUNCTIONS Inputs Outputs CLK_EN CLK_SEL Input Function Output Function Qx Qx 0 0 CLK input selected Disabled LOW HIGH 0 1 Crystal Inputs Selected Disabled LOW HIGH 1 0 CLK input selected Enabled CLK0 Invert of CLK1 1 1 Crystal Inputs Selected Enabled CLK1 Invert of CLK1 1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show in Figure 3. 2
3 CLK CLK_EN Disabled Enabled Q[0:3] Q[0:3] Figure 3. CLK_EN Timing Diagram Table 3. ATTRIBUTES (Note 2) Characteristics Internal Input Pullup Resistor Internal Input Pulldown Resistor C in Input Capacitance ESD Protection Human Body Model Machine Model Value 50 k 50 k 4 pf > 2 kv > 200 V Moisture Sensitivity, Indefinite Time Out of Drypack (Note 2) Level 1 Flammability Rating Oxygen Index Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 2. For additional information, see Application Note AND8003/D. UL 94 V in 28 to Devices Table 4. MAXIMUM RATINGS (Note 3) Symbol Parameter Condition 1 Condition 2 Rating Unit V CC Supply Voltage 4.6 V V in Input Voltage 0.5 V I VCC V I out Output Current Continuous Surge ma T A Operating Temperature Range, Industrial 40 to +85 C T stg Storage Temperature Range 65 to +150 C θ JA Thermal Resistance (Junction to Ambient) 0 lfpm Single Layer PCB (700 mm 2, 2 oz) 200 lfpm Multi Layer PCB (700 mm 2, 2 oz) 128 C/W 94 θ JC Thermal Resistance (Junction to Case) (Note 4) TSSOP to 41 C/W T sol Wave Solder 265 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 3. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously. If stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected. 4. JEDEC standard multilayer board 2S2P (2 signal, 2 power). 3
4 Table 5. CRYSTAL CHARACTERISTICS AND CONNECTIONS Parameter Min Typ Max Unit Mode of Oscillation Fundamental Parallel Frequency MHz Equivalent Series Resistance (ESR) 50 Shunt Capacitance 7 pf Drive Level 1 mw Table 6. DC CHARACTERISTICS V CC = 3.3 ±5% V (3.135 to V), V EE = 0 V, T A = 40 C to +85 C (Note 5) Symbol Characteristic Min Typ Max Unit I EE Power Supply Current 60 ma V IH Input HIGH Voltage 2 V CC V V IL Input LOW Voltage V I IH Input High Current (V CC = V) CLK, CLK_SEL = V CLK_EN = V A I IL Input LOW Current (V CC = V) CLK, CLK_SEL = V CLK_EN = V A V OH Output HIGH Voltage V CC 1.4 V CC 0.9 V V OL Output LOW Voltage V CC 2.0 V CC 1.7 V VOUT SWING Output Voltage Swing (peak to peak) V NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Outputs terminated 50 to V CC 2.0 V, see Figure 4. Table 7. AC CHARACTERISTICS V CC = 3.3 ±5% V (3.135 to V), V EE = 0 V, TA = 40 C to +85 C (Note 6) Symbol Characteristic Min Typ Max Unit F MAX Maximum Operating Frequency MHz t PD Propagation Delay (Notes 7 and 9) ns tskew DC Duty Cycle Skew same path similar conditions at 50 MHz (Notes 7, 8 and 9) % tskew O O Output to Output Skew Within A Device (Notes 7, 8 and 9) 30 ps tskew D D Device to Device Skew similar path and conditions (Notes 7, 8 and 9) 200 ps t JIT Additive Phase Noise Jitter MHz (Integrated from 12 khz to 20 MHz) See Figure 6. (Note 9) ps t r /t f Output rise and fall times (20% and 80% points) (Note 9) ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 6. Outputs terminated 50 to V CC 2.0 V, see Figure Measured under the same supply voltage, output loading, and input conditions. 8. Similar conditions. 9. Limits do not apply to overdriving XTAL_IN. 4
5 2 V V CC Z o = 50 Qx LVPECL 50 V EE Z o = 50 Qx ± V Figure 4. Typical Test Setup and Termination for Evaluation. A split supply of V CC = 2.0 V and V EE = V allows a convenient direct connection termination into typical oscilloscope 50 to GND impedance modules. For Application termination schemes see AND8020. Input V CC /2 V CC /2 Output t PW t PD t PD Output 80% 80% 20% t R Propagation Delay t PD 20% t F t Period tskew DC % tpw t Period 100 Duty Cycle Skew t SKEWDC Input Input CLKx Part #1 Output tskew 0 0 tskew 0 0 tskew D D tskew D D CLKy Part #2 Output Output to Output Skew tskew 0 0 Device to Device Skew, tskew D D Figure 5. AC Measurement Reference 5
6 NB3N853531E Source Generator Figure 6. For MHz Carrier, the NB3N853531E Additive Phase Noise (dbc/hz) verses SSB Offset Frequency (Hz) Integrated Jitter from 12 khz to 20 MHz (Upper Heavy Line) is 88.1 fs RMS. The E8663B Source Generator Additive Phase Noise (Lower Light Line) is 70.1 fs RMS. Where t JIT = (t JIToutput ) 2 (t JITinput ) 2 = 53 fs Application Crystal Input Interface Figure 7 shows the NB3N853531E device crystal oscillator interface using a typical parallel resonant crystal. A parallel crystal with loading capacitance C L = 18 pf could use Series Load Caps C1 = 32 pf and C2 = 32 pf as nominal values, after subtracting a typical 4 pf of stray cap per line. The frequency accuracy and duty cycle skew can be fine tuned by adjusting the C1 and C2 values. For example, increasing the C1 and C2 values will reduce the operational frequency. Note R1 is optional and may be pf 32 pf C1 C2 X1 18 pf Parallel Resonant Crystal R1* XTAL_IN/CLK XTAL_OUT Figure 7. NB3N853531E Crystal Oscillator Interface *R1 is optional. Assuming 4 pf stray cap per pin. 6
7 Figure 8. NB3N853531E Phase Noise with 25 MHz Crystal ORDERING INFORMATION NB3N853531EDTG NB3N853531EDTR2G Device Package Shipping TSSOP 20 (Pb Free) TSSOP 20 (Pb Free) 75 Units / Rail 2500 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 7
8 PACKAGE DIMENSIONS TSSOP 20 CASE 948E 02 ISSUE C 0.15 (0.006) T L 0.15 (0.006) T U 2X L/2 PIN 1 IDENT U S S C (0.004) T SEATING PLANE 20X K REF 0.10 (0.004) M T U S V S A V D G H B U N J J1 N K K1 ÍÍÍÍ ÍÍÍÍ SECTION N N F DETAIL E 0.25 (0.010) DETAIL E SOLDERING FOOTPRINT* M W NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE W. MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G 0.65 BSC BSC H J J K K L 6.40 BSC BSC M PITCH 16X X 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 8
9 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative NB3N853531E/D
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. V, 62.5 MHz / 125 MHz LVPECL Clock Oscillator The NBXBA014 dual frequency crystal oscillator (XO) is designed to meet today s requirements for. V LVPECL clock generation applications. The device uses
MJD31, MJD31C (NPN), MJD32, MJD32C (PNP) Complementary Power Transistors. DPAK For Surface Mount Applications
MJD3, MJD3C (NPN), MJD3, MJD3C (PNP) Complementary Power Transistors For Surface Mount Applications Designed for general purpose amplifier and low speed switching applications. Features Lead Formed for
NSR0340V2T1/D. Schottky Barrier Diode 40 VOLT SCHOTTKY BARRIER DIODE
Schottky Barrier Diode Schottky barrier diodes are optimized for very low forward voltage drop and low leakage current and are used in a wide range of dc dc converter, clamping and protection applications
NBXDPA V / 3.3 V, MHz / MHz LVDS Clock Oscillator
2.5 V / 3.3 V, 156.25 MHz / 312.5 MHz LVS Clock Oscillator The NBXPA017 dual frequency crystal oscillator (XO) is designed to meet today s requirements for 2.5 V and 3.3 V LVS clock generation applications.
MMBTA06W, SMMBTA06W, Driver Transistor. NPN Silicon. Moisture Sensitivity Level: 1 ESD Rating: Human Body Model 4 kv ESD Rating: Machine Model 400 V
Driver Transistor NPN Silicon Moisture Sensitivity Level: 1 ESD Rating: Human Body Model 4 kv ESD Rating: Machine Model 400 V Features S Prefix for Automotive and Other Applications Requiring Unique Site
NBVSPA V, MHz LVDS Voltage-Controlled Clock Oscillator (VCXO) PureEdge Product Series
2.5 V, 212.00 MHz LVS Voltage-Controlled Clock Oscillator (VCXO) PureEdge Product Series The NBVSPA01 voltage controlled crystal oscillator (VCXO) is designed to meet today s requirements for 2.5 V LVS
MUN5332DW1, NSBC143EPDXV6, NSBC143EPDP6. Complementary Bias Resistor Transistors R1 = 4.7 k, R2 = 4.7 k
MUN5DW, NSBCEPDXV6, NSBCEPDP6 Complementary Bias Resistor Transistors R =.7 k, R =.7 k NPN and PNP Transistors with Monolithic Bias Resistor Network () PIN CONNECTIONS () () This series of digital transistors
NCN Differential Channel 1:2 Mux/Demux Switch for PCI Express Gen3
4-Differential Channel 1:2 Mux/Demux Switch for PCI Express Gen3 The NCN3411 is a 4 Channel differential SPDT switch designed to route PCI Express Gen3 signals. When used in a PCI Express application,
NTK3139P. Power MOSFET. 20 V, 780 ma, Single P Channel with ESD Protection, SOT 723
NTK9P Power MOSFET V, 78 ma, Single P Channel with ESD Protection, SOT 7 Features P channel Switch with Low R DS(on) % Smaller Footprint and 8% Thinner than SC 89 Low Threshold Levels Allowing.5 V R DS(on)
NTS4173PT1G. Power MOSFET. 30 V, 1.3 A, Single P Channel, SC 70
NTS17P Power MOSFET V, 1. A, Single P Channel, SC 7 Features V BV ds, Low R DS(on) in SC 7 Package Low Threshold Voltage Fast Switching Speed This is a Halide Free Device This is a Pb Free Device Applications
NCN1154. USB 2.0 High Speed, UART and Audio Switch with Negative Signal Capability
USB 2.0 High Speed, UART and Audio Switch with Negative Signal Capability The NCN1154 is a DP3T switch for combined true ground audio, USB 2.0 high speed data, and UART applications. It allows portable
NTTFS3A08PZTWG. Power MOSFET 20 V, 15 A, Single P Channel, 8FL
NTTFS3A8PZ Power MOSFET V, 5 A, Single P Channel, 8FL Features Ultra Low R DS(on) to Minimize Conduction Losses 8FL 3.3 x 3.3 x.8 mm for Space Saving and Excellent Thermal Conduction ESD Protection Level
MUN5211T1 Series. NPN Silicon Surface Mount Transistor with Monolithic Bias Resistor Network NPN SILICON BIAS RESISTOR TRANSISTORS
MUNT Series Preferred Devices Bias Resistor Transistor NPN Silicon Surface Mount Transistor with Monolithic Bias Resistor Network This new series of digital transistors is designed to replace a single
Distributed by: www.jameco.com 1-800-831-44 The content and copyrights of the attached material are the property of its owner. Transient Voltage Suppressors Micro Packaged Diodes for ESD Protection The
NTS4172NT1G. Power MOSFET. 30 V, 1.7 A, Single N Channel, SC 70. Low On Resistance Low Gate Threshold Voltage Halide Free This is a Pb Free Device
Power MOSFET V,.7 A, Single N Channel, SC 7 Features Low On Resistance Low Gate Threshold Voltage Halide Free This is a Pb Free Device V (BR)DSS R DS(on) MAX I D MAX Applications Low Side Load Switch DC
LM339S, LM2901S. Single Supply Quad Comparators
LM339S, LM290S Single Supply Quad Comparators These comparators are designed for use in level detection, low level sensing and memory applications in consumer and industrial electronic applications. Features
NLAS7222B, NLAS7222C. High-Speed USB 2.0 (480 Mbps) DPDT Switches
High-Speed USB 2.0 (480 Mbps) DPDT Switches ON Semiconductor s NLAS7222B and NLAS7222C are part of a series of analog switch circuits that are produced using the company s advanced sub micron CMOS technology,
PCS3P8103A General Purpose Peak EMI Reduction IC
General Purpose Peak EMI Reduction IC Features Generates a 4x low EMI spread spectrum clock Input Frequency: 16.667MHz Output Frequency: 66.66MHz Tri-level frequency Deviation Selection: Down Spread, Center
NSVEMD4DXV6T5G. Dual Bias Resistor Transistors. NPN and PNP Silicon Surface Mount Transistors with Monolithic Bias Resistor Network
Dual Bias Resistor Transistors NPN and PNP Silicon Surface Mount Transistors with Monolithic Bias Resistor Network The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias
NTR4502P, NVTR4502P. Power MOSFET. 30 V, 1.95 A, Single, P Channel, SOT 23
NTRP, NVTRP Power MOSFET V,.9 A, Single, P Channel, SOT Features Leading Planar Technology for Low Gate Charge / Fast Switching Low R DS(ON) for Low Conduction Losses SOT Surface Mount for Small Footprint
PZTA92T1. High Voltage Transistor. PNP Silicon SOT 223 PACKAGE PNP SILICON HIGH VOLTAGE TRANSISTOR SURFACE MOUNT
High Voltage Transistor PNP Silicon Features These Devices are Pb Free, Halogen Free/BFR Free and are RoHS Compliant MAXIMUM RATINGS (T C = 25 C unless otherwise noted) Rating Symbol Value Unit Collector-Emitter
NTJS4405N, NVJS4405N. Small Signal MOSFET. 25 V, 1.2 A, Single, N Channel, SC 88
NTJSN, NVJSN Small Signal MOSFET V,. A, Single, N Channel, SC 88 Features Advance Planar Technology for Fast Switching, Low R DS(on) Higher Efficiency Extending Battery Life AEC Q Qualified and PPAP Capable
MMBZxxxALT1G Series, SZMMBZxxxALT1G Series. 24 and 40 Watt Peak Power Zener Transient Voltage Suppressors
MMBZxxxALTG Series, SZMMBZxxxALTG Series 24 and 4 Watt Peak Power Zener Transient Voltage Suppressors Dual Common Anode Zeners for ESD Protection These dual monolithic silicon Zener diodes are designed
NTMS4801NR2G. Power MOSFET 30 V, 12 A, N Channel, SO 8
NTMSN Power MOSFET 3 V, A, N Channel, SO Features Low R DS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses This is a Pb Free
NLAS323. Dual SPST Analog Switch, Low Voltage, Single Supply A4 D
Dual SPST Analog Switch, Low Voltage, Single Supply The NLAS323 is a dual SPST (Single Pole, Single Throw) switch, similar to /2 a standard 466. The device permits the independent selection of 2 analog/digital
MMUN2111LT1 Series. Bias Resistor Transistors. PNP Silicon Surface Mount Transistors with Monolithic Bias Resistor Network
MMUNLT Series Preferred Devices Bias Resistor Transistors PNP Silicon Surface Mount Transistors with Monolithic Bias Resistor Network This new series of digital transistors is designed to replace a single
NBXDPA V / 3.3 V, 125 MHz / 250 MHz LVDS Clock Oscillator
2.5 V / 3.3 V, 125 MHz / 250 MHz LVS Clock Oscillator The NBXPA019 dual frequency crystal oscillator (XO) is designed to meet today s requirements for 2.5 V and 3.3 V LVS clock generation applications.
NDF10N60Z. N-Channel Power MOSFET 600 V, 0.75
NDFNZ N-Channel Power MOSFET V,.7 Features Low ON Resistance Low Gate Charge ESD Diode Protected Gate % Avalanche Tested % R g Tested These Devices are Pb Free, Halogen Free/BFR Free and are RoHS Compliant
NBXSBA024, NBXSBB024, NBXMBB V / 3.3 V, MHz LVPECL Clock Oscillator
NBXSBA0, NBXSBB0, NBXMBB0.5 V /. V, 6.08 MHz LVPECL Clock Oscillator The single frequency, crystal oscillator (XO) is designed to meet today s requirements for.5 V /. V LVPECL clock generation applications.
MMUN2211LT1 Series. NPN Silicon Surface Mount Transistor with Monolithic Bias Resistor Network
MMUNLT Series Preferred Devices Bias Resistor Transistor NPN Silicon Surface Mount Transistor with Monolithic Bias Resistor Network This new series of digital transistors is designed to replace a single
NTK3043N. Power MOSFET. 20 V, 285 ma, N Channel with ESD Protection, SOT 723
NTKN Power MOSFET V, 8 ma, N Channel with ESD Protection, SOT 7 Features Enables High Density PCB Manufacturing % Smaller Footprint than SC 89 and 8% Thinner than SC 89 Low Voltage Drive Makes this Device
NVD5865NL. Power MOSFET 60 V, 46 A, 16 m, Single N Channel
Power MOSFET 6 V, 6 A, 16 m, Single N Channel Features Low R DS(on) to Minimize Conduction Losses High Current Capability Avalanche Energy Specified AEC Q1 Qualified These Devices are Pb Free, Halogen
NTTD4401F. FETKY Power MOSFET and Schottky Diode. 20 V, 3.3 A P Channel with 20 V, 1.0 A Schottky Diode, Micro8 Package
NTTDF FETKY Power MOSFET and Schottky Diode V,. A P Channel with V,. A Schottky Diode, Micro Package The FETKY product family incorporates low R DS(on), true logic level MOSFETs packaged with industry
MMSZ4678ET1 Series. Zener Voltage Regulators. 500 mw SOD 123 Surface Mount
MMSZ4678ET Series Zener Voltage Regulators 5 mw SOD 3 Surface Mount Three complete series of Zener diodes are offered in the convenient, surface mount plastic SOD 3 package. These devices provide a convenient
MMBZxxVAWT1G Series, SZMMBZxxVAWT1G Series. 40 Watt Peak Power Zener Transient Voltage Suppressors. SC 70 Dual Common Anode Zeners for ESD Protection
MMBZxxVAWTG Series, SZMMBZxxVAWTG Series 4 Watt Peak Power Zener Transient Voltage Suppressors SC 7 Dual Common Anode Zeners for ESD Protection These dual monolithic silicon Zener diodes are designed for
NTNS3164NZT5G. Small Signal MOSFET. 20 V, 361 ma, Single N Channel, SOT 883 (XDFN3) 1.0 x 0.6 x 0.4 mm Package
NTNS36NZ Small Signal MOSFET V, 36 ma, Single N Channel, SOT 883 (XDFN3). x.6 x. mm Package Features Single N Channel MOSFET Ultra Low Profile SOT 883 (XDFN3). x.6 x. mm for Extremely Thin Environments
MMBZ15VDLT3G MMBZ27VCLT1G SZMMBZ15VDLT3G. SZMMBZ27VCLT1G 40 Watt Peak Power Zener Transient Voltage Suppressors
MMBZ15VDLT1G, MMBZ27VCLT1G, SZMMBZ15VDLT1G, SZMMBZ27VCLT1G 40 Watt Peak Power Zener Transient Voltage Suppressors Dual Common Cathode Zeners for ESD Protection These dual monolithic silicon zener diodes
PIN CONNECTIONS MAXIMUM RATINGS (T J = 25 C unless otherwise noted) SC 75 (3 Leads) Parameter Symbol Value Unit Drain to Source Voltage V DSS 30 V
NTA7N, NVTA7N Small Signal MOSFET V, 4 ma, Single, N Channel, Gate ESD Protection, SC 7 Features Low Gate Charge for Fast Switching Small.6 x.6 mm Footprint ESD Protected Gate NV Prefix for Automotive
NL27WZ07. Dual Buffer with Open Drain Outputs
Dual Buffer with Open Drain Outputs The N27WZ07 is a high performance dual buffer with open drain outputs operating from a.5 to 5.5 V supply. The internal circuit is composed of multiple stages, including
NSTB1005DXV5T1, NSTB1005DXV5T5. Dual Common Base Collector Bias Resistor Transistors
NSTB005DXV5T, NSTB005DXV5T5 Preferred Devices Dual Common Base Collector Bias Resistor Transistors NPN and PNP Silicon Surface Mount Transistors with Monolithic Bias Resistor Network The BRT (Bias Resistor
PCS2P2309/D. 3.3V 1:9 Clock Buffer. Functional Description. Features. Block Diagram
3.3V 1:9 Clock Buffer Features One-Input to Nine-Output Buffer/Driver Buffers all frequencies from DC to 133.33MHz Low power consumption for mobile applications Less than 32mA at 66.6MHz with unloaded
NTHD4502NT1G. Power MOSFET. 30 V, 3.9 A, Dual N Channel ChipFET
NTHDN Power MOSFET V,.9 A, Dual N Channel ChipFET Features Planar Technology Device Offers Low R DS(on) and Fast Switching Speed Leadless ChipFET Package has % Smaller Footprint than TSOP. Ideal Device
MMSZxxxET1G Series, SZMMSZxxxET1G Series. Zener Voltage Regulators. 500 mw SOD 123 Surface Mount
MMSZxxxETG Series, SZMMSZxxxETG Series Zener Voltage Regulators mw SOD Surface Mount Three complete series of Zener diodes are offered in the convenient, surface mount plastic SOD package. These devices
MUN5216DW1, NSBC143TDXV6. Dual NPN Bias Resistor Transistors R1 = 4.7 k, R2 = k. NPN Transistors with Monolithic Bias Resistor Network
MUN526DW, NSBC43TDXV6 Dual NPN Bias Resistor Transistors R = 4.7 k, R2 = k NPN Transistors with Monolithic Bias Resistor Network This series of digital transistors is designed to replace a single device
MBRM110LT3G NRVBM110LT1G NRVBM110LT3G. Surface Mount Schottky Power Rectifier. POWERMITE Power Surface Mount Package
MBRM11LT1G, NRVBM11LT1G, NRVBM11LT3G Surface Mount Schottky Power Rectifier Power Surface Mount Package The Schottky employs the Schottky Barrier principle with a barrier metal and epitaxial construction
MBRS360T3, MBRS360BT3G. Surface Mount Schottky Power Rectifier SCHOTTKY BARRIER RECTIFIERS 3.0 AMPERES, 60 VOLTS
Surface Mount Schottky Power Rectifier This device employs the Schottky Barrier principle in a large area metal to silicon power diode. State of the art geometry features epitaxial construction with oxide