MC100LVELT20 Product Preview 3.3VНLVTTL/LVCMOS to Differential LVPECL Translator Description The MC100LVELT20 is a 3.3 V TTL/CMOS to differential PECL
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1 Product Preview 3.3VНLVTTL/LVCMOS to ifferential LVPECL Translator escription The is a 3.3 V TTL/CMOS to differential PECL translator. Because PECL (Positive ECL) levels are used, only V and ground are required. The small outline SOIC package and the single gate of the makes it ideal for those applications where space, performance, and low power are at a premium. The 00 Series contains temperature compensation. Features 390 ps Typical Propagation elay Maximum Input Clock Frequency > 0. GHz Typical Operating Range V CC = 3.0 V to 3.6 V with GN = 0 V PNP TTL Input for Minimal Loading Output will efault HIGH with Input Open Pb Free Packages are Available SO SUFFIX CASE 75 MARKING IAGRAM KVT20 ALYW A = Assembly Location L = Wafer Lot Y = Year W = Work Week = Pb Free Package *For additional marking information, refer to Application Note AN002/. ORERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. m/on/ Semiconductor Components Industries, LLC, 2006 Publication Order Number: November, 2006 Rev. P3 /
2 Table. PIN ESCRIPTION V CC Pin Function, ifferential PECL Outputs 2 LVTTL 7 V CC LVTTL Input Positive Supply GN Ground 3 6 No Connect LVPECL 4 5 GN (Top View) Figure. Lead Pinout and Logic iagram Table 2. ATTRIBUTES Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ES Protection Human Body Model Machine Model Charged evice Model >.5 kv > 200 V > 2 kv Moisture Sensitivity, Indefinite Time Out of rypack (Note ) Pb Pkg Pb Free Pkg SOIC Level Level Flammability Rating Oxygen Index: 2 to 34 UL 94 V 0.25 in Transistor Count Meets or exceeds JEEC Spec EIA/JES7 IC Latchup Test. For additional information, see Application Note AN003/. Value N/A N/A 50 evices Table 3. MAXIMUM RATINGS Symbol Parameter Condition Condition 2 Rating Unit V CC Power Supply GN = 0 V 6 V V I Input Voltage GN = 0 V V I V CC 6 V I out Output Current Continuous Surge ma ma T A Operating Temperature Range 40 to +5 C T stg Storage Temperature Range 65 to +50 C JA Thermal Resistance (Junction to Ambient) 0 lfpm 500 lfpm SOIC SOIC JC Thermal Resistance (Junction to Case) Standard Board SOIC 4 to 44 C/W T sol Wave Solder Pb Pb Free Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability C/W C/W C m/on/ 2
3 Table 4. LVTTL INPUT C CHARACTERISTICS V CC = 3.3 V, GN = 0 V, T A = 40 C to +5 C Symbol Characteristic Min Typ Max Unit I IH Input HIGH Current (V in = 2.7 V) 20 A I IHH Input HIGH Current MAX (V in = 6.0 V) 00 A I IL Input LOW Current (V in = 0.5 V) 0.6 ma V IK Input Clamp Voltage (I in = ma).2 V V IH Input HIGH Voltage 2.0 V V IL Input LOW Voltage 0. V NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit values are applied individually under normal operating conditions and not valid simultaneously. Table 5. 00LVELT PECL OUTPUT C CHARACTERISTICS V CC = 3.3 V, GN = 0 V (Note 2) Symbol Characteristic 40 C 25 C 5 C Min Typ Max Min Typ Max Min Typ Max I CC Negative Power Supply Current ma V OH Output HIGH Voltage (Note 3) mv V OL Output LOW Voltage (Note 3) mv NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Output parameters vary : with V CC. 3. All loading with 50 to V CC 2.0 V. Table 6. AC CHARACTERISTICS V CC = 3.0 V to 3.6 V, GN = 0 V (Note 4) 40 C 25 C 5 C Symbol f max Characteristic Maximum Input Clock Frequency (Figure 2) Min Typ Max Min Typ Max Min Typ Max Unit Unit MHz t PLH, t PHL Propagation elay to Output ifferential ps t SKEW evice to evice Skew (Note 5) ps t JITTER Random Clock Jitter (RMS) (Figure 2) < < 2 < < 2 < < 2 ps t r Output Rise/Fall Times, t f (20% 0%) ps NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. Measured using a LVTTL source, 50% duty cycle clock source. All loading with 50 to V CC 2.0 V. 5. Skew is measured between outputs under identical transitions. m/on/ 3
4 OUTPUT VOLTAGE AMPLITUE (mv) Jitter Amplitude RANOM CLOCK JITTER (ps RMS) INPUT CLOCK FREUEY (MHz) Figure 2. Output Voltage Amplitude (V OUTpp )/RMS Jitter vs. Input Clock Frequency at Ambient Temperature Z o = 50 river Receiver evice evice Z o = V TT V TT = V CC 2.0 V Figure 3. Typical Termination for Output river and evice Evaluation (See Application Note AN020/ Termination of ECL Logic evices.) ORERING INFORMATION evice Package Shipping SOIC 9 Units / Rail G SOIC (Pb Free) 9 Units / Rail R2 SOIC 2500 / Tape & Reel R2G SOIC (Pb Free) 2500 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BR0/. m/on/ 4
5 Resource Reference of Application Notes AN405/ ECL Clock istribution Techniques AN406/ esigning with PECL (ECL at +5.0 V) AN503/ ECLinPS I/O SPiCE Modeling Kit AN504/ Metastability and the ECLinPS Family AN56/ Interfacing Between LVS and ECL AN672/ The ECL Translator Guide AN00/ Odd Number Counters esign AN002/ Marking and ate Codes AN020/ Termination of ECL Logic evices AN066/ Interfacing with ECLinPS AN090/ AC Characteristics of ECL evices m/on/ 5
6 PACKAGE IMENSIONS SOIC NB CASE ISSUE AH Y B X A 5 4 S 0.25 (0.00) M Y M K NOTES:. IMENSIONING AN TOLERAING PER ANSI Y4.5M, CONTROLLING IMENSION: MILLIMETER. 3. IMENSION A AN B O NOT ILUE MOL PROTRUSION. 4. MAXIMUM MOL PROTRUSION 0.5 (0.006) PER SIE. 5. IMENSION OES NOT ILUE AMBAR PROTRUSION. ALLOWABLE AMBAR PROTRUSION SHALL BE 0.27 (0.005) TOTAL IN EXCESS OF THE IMENSION AT MAXIMUM MATERIAL CONITION THRU ARE OBSOLETE. NEW STANAR IS Z H G C 0.25 (0.00) M Z Y S X S SEATING PLANE 0.0 (0.004) N X 45 M J MILLIMETERS IHES IM MIN MAX MIN MAX A B C G.27 BSC BSC H J K M 0 0 N S SOLERING FOOTPRINT* SCALE 6: mm inches *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLERRM/. m/on/ 6
7 ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORERING INFORMATION LITERATURE FULFILLMENT: Literature istribution Center for ON Semiconductor P.O. Box 563, enver, Colorado 027 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: m/on/ / 7 For additional information, please contact your local Sales Representative
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3.3VНVTT/VCMOS to VPEC Translator The is a 10 Bit VTT/VCMOS to VPEC translator. Because VPEC (Positive EC) levels are used only +3.3 V and ground are required. The device has an OR ed enable input which
Distributed by: www.jameco.com 1-800-831-44 The content and copyrights of the attached material are the property of its owner. Transient Voltage Suppressors Micro Packaged Diodes for ESD Protection The
MUN5311DW1T1G Series.
MUNDWTG Series Preferred Devices Dual Bias Resistor Transistors NPN and PNP Silicon Surface Mount Transistors with Monolithic Bias Resistor Network The Bias Resistor Transistor (BRT) contains a single
MMSZ5221BT1 Series. Zener Voltage Regulators. 500 mw SOD 123 Surface Mount
MMSZ5BT Series Preferred Device Zener Voltage Regulators 5 mw SOD 3 Surface Mount Three complete series of Zener diodes are offered in the convenient, surface mount plastic SOD 3 package. These devices
NTMS4801NR2G. Power MOSFET 30 V, 12 A, N Channel, SO 8
NTMSN Power MOSFET 3 V, A, N Channel, SO Features Low R DS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses This is a Pb Free
NBSG16M. 2.5 V/3.3 V Multilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer
2.5 V/3.3 V Multilevel Input to CML Clock/ata Receiver/river/Translator Buffer escription The NBSG6M is a differential current mode logic (CML) receiver/driver/translator buffer. The device is functionally
BD809 (NPN), BD810 (PNP) Plastic High Power Silicon Transistor 10 AMPERE POWER TRANSISTORS 80 VOLTS 90 WATTS
BD89 (NPN), BD8 (PNP) Plastic High Power Silicon Transistor These devices are designed for use in high power audio amplifiers utilizing complementary or quasi complementary circuits. Features DC Current
NSBC114EDP6T5G Series. Dual Digital Transistors (BRT) NPN Silicon Surface Mount Transistors with Monolithic Bias Resistor Network
Preferred Devices Dual Digital Transistors (BRT) NPN Silicon Surface Mount Transistors with Monolithic Bias Resistor Network This new series of digital transistors is designed to replace a single device
NB4N840M. 3.3V 3.2Gb/s Dual Differential Clock/Data 2 x 2 Crosspoint Switch with CML Output and Internal Termination
3.3V 3.2Gb/s Dual Differential Clock/Data 2 x 2 Crosspoint Switch with Output and Internal Termination Description The NB4N84M is a high bandwidth fully differential dual 2 x 2 crosspoint switch with inputs/outputs
MMUN2111LT1 Series. Bias Resistor Transistors. PNP Silicon Surface Mount Transistors with Monolithic Bias Resistor Network
MMUNLT Series Preferred Devices Bias Resistor Transistors PNP Silicon Surface Mount Transistors with Monolithic Bias Resistor Network This new series of digital transistors is designed to replace a single
MC100EL14. 5V ECL 1:5 Clock Distribution Chip
MC100E14 5V EC 1:5 Clock Distribution Chip The MC100E14 is a low skew 1:5 clock distribution chip designed explicitly for low skew clock distribution applications. The V BB pin, an internally generated
NSVEMD4DXV6T5G. Dual Bias Resistor Transistors. NPN and PNP Silicon Surface Mount Transistors with Monolithic Bias Resistor Network
Dual Bias Resistor Transistors NPN and PNP Silicon Surface Mount Transistors with Monolithic Bias Resistor Network The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias
MC10H603, MC100H Bit Latch ECL to TTL Translator
9 Bit atch EC to TT Tralator escription The MC10/100603 is a 9 bit, dual supply EC to TT tralator. evices in the ON Semiconductor 9 bit tralator series utilize the 28 lead PCC for optimal power pinning,
PZTA92T1. High Voltage Transistor. PNP Silicon SOT 223 PACKAGE PNP SILICON HIGH VOLTAGE TRANSISTOR SURFACE MOUNT
High Voltage Transistor PNP Silicon Features These Devices are Pb Free, Halogen Free/BFR Free and are RoHS Compliant MAXIMUM RATINGS (T C = 25 C unless otherwise noted) Rating Symbol Value Unit Collector-Emitter
NBSG53ABAR2. 2.5V/3.3VНSiGe Selectable Differential Clock and Data D Flip Flop/Clock Divider with Reset and OLS*
NBSG3A.V/3.3VНSiGe Selectable Differential Clock and Data D Flip Flop/Clock Divider with Reset and OLS* The NBSG3A is a multi-function differential D flip-flop (DFF) or fixed divide by two (DIV/) clock
NTTFS5116PLTWG. Power MOSFET 60 V, 20 A, 52 m. Low R DS(on) Fast Switching These Devices are Pb Free and are RoHS Compliant
Power MOSFET 6 V, 2 A, 52 m Features Low R DS(on) Fast Switching These Devices are Pb Free and are RoHS Compliant Applications Load Switches DC Motor Control DC DC Conversion MAXIMUM RATINGS ( unless otherwise
MMUN2211LT1 Series. NPN Silicon Surface Mount Transistor with Monolithic Bias Resistor Network
MMUNLT Series Preferred Devices Bias Resistor Transistor NPN Silicon Surface Mount Transistor with Monolithic Bias Resistor Network This new series of digital transistors is designed to replace a single
NB4L V / 3.3V Differential LVPECL 2x2 Clock Switch and Low Skew Fanout Buffer
2.5V / 3.3V Differential LVPECL 2x2 Clock Switch and Low Skew Fanout Buffer Description The NB4L6254 is a differential 2x2 clock switch and drives precisely aligned clock signals through its LVPECL fanout
SN74LS122, SN74LS123. Retriggerable Monostable Multivibrators LOW POWER SCHOTTKY
Retriggerable Monostable Multivibrators These dc triggered multivibrators feature pulse width control by three methods. The basic pulse width is programmed by selection of external resistance and capacitance
NSQA6V8AW5T2 Series Transient Voltage Suppressor
Transient Voltage Suppressor ESD Protection Diode with Low Clamping Voltage This integrated transient voltage suppressor device (TVS) is designed for applications requiring transient overvoltage protection.
MMBZ15VDLT3G MMBZ27VCLT1G. 40 Watt Peak Power Zener Transient Voltage Suppressors. SOT-23 Dual Common Cathode Zeners for ESD Protection
MMBZ5VDLT, MMBZ7VCLT Preferred s 40 Watt Peak Power Zener Transient Voltage Suppressors SOT- Dual Common Cathode Zeners for ESD Protection These dual monolithic silicon zener diodes are designed for applications
NGB8207AN, NGB8207ABN. Ignition IGBT 20 A, 365 V, N Channel D 2 PAK. 20 AMPS, 365 VOLTS V CE(on) = 1.75 V I C = 10 A, V GE 4.
NGB827AN, NGB827ABN Ignition IGBT 2 A, 365 V, N Channel D 2 PAK This Logic Level Insulated Gate Bipolar Transistor (IGBT) features monolithic circuitry integrating ESD and Overvoltage clamped protection
NTMD4840NR2G. Power MOSFET 30 V, 7.5 A, Dual N Channel, SOIC 8
NTMDN Power MOSFET 3 V, 7. A, Dual N Channel, SOIC Features Low R DS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses Dual
UMC2NT1, UMC3NT1, UMC5NT1
UMCNT, UMC3NT, UMC5NT Preferred Devices Dual Common BaseCollector Bias Resistor Transistors NPN and PNP Silicon Surface Mount Transistors with Monolithic Bias Resistor Network The Bias Resistor Transistor
MMBFU310LT1G. JFET Transistor. N Channel. These Devices are Pb Free, Halogen Free/BFR Free and are RoHS Compliant. Features.
MMBFULT1G JFET Transistor N Channel Features These Devices are Pb Free, Halogen Free/BFR Free and are RoHS Compliant 2 SOURCE MAXIMUM RATINGS Rating Symbol Value Unit Drain Source Voltage V DS 25 Vdc Gate
NGB18N40CLB, NGB18N40ACLB. Ignition IGBT 18 Amps, 400 Volts. N Channel D 2 PAK. 18 AMPS, 400 VOLTS V CE(on) 2.0 I C = 10 A, V GE 4.
NGB8N4CLB, NGB8N4ACLB Ignition IGBT 8 Amps, 4 Volts N Channel D PAK This Logic Level Insulated Gate Bipolar Transistor (IGBT) features monolithic circuitry integrating ESD and Over Voltage clamped protection
MMBTA06W, SMMBTA06W, Driver Transistor. NPN Silicon. Moisture Sensitivity Level: 1 ESD Rating: Human Body Model 4 kv ESD Rating: Machine Model 400 V
Driver Transistor NPN Silicon Moisture Sensitivity Level: 1 ESD Rating: Human Body Model 4 kv ESD Rating: Machine Model 400 V Features S Prefix for Automotive and Other Applications Requiring Unique Site
NDF10N60Z. N-Channel Power MOSFET 600 V, 0.75
NDFNZ N-Channel Power MOSFET V,.7 Features Low ON Resistance Low Gate Charge ESD Diode Protected Gate % Avalanche Tested % R g Tested These Devices are Pb Free, Halogen Free/BFR Free and are RoHS Compliant
NTMD4184PFR2G. Power MOSFET and Schottky Diode -30 V, -4.0 A, Single P-Channel with 20 V, 2.2 A, Schottky Barrier Diode Features
NTMDPF Power MOSFET and Schottky Diode -3 V, -. A, Single P-Channel with V,. A, Schottky Barrier Diode Features FETKY Surface Mount Package Saves Board Space Independent Pin-Out for MOSFET and Schottky
NTTFS5820NLTWG. Power MOSFET. 60 V, 37 A, 11.5 m. Low R DS(on) Low Capacitance Optimized Gate Charge These Devices are Pb Free and are RoHS Compliant
NTTFS582NL Power MOSFET 6 V, 37 A,.5 m Features Low R DS(on) Low Capacitance Optimized Gate Charge These Devices are Pb Free and are RoHS Compliant MAXIMUM RATINGS ( unless otherwise stated) Parameter
NTS4172NT1G. Power MOSFET. 30 V, 1.7 A, Single N Channel, SC 70. Low On Resistance Low Gate Threshold Voltage Halide Free This is a Pb Free Device
Power MOSFET V,.7 A, Single N Channel, SC 7 Features Low On Resistance Low Gate Threshold Voltage Halide Free This is a Pb Free Device V (BR)DSS R DS(on) MAX I D MAX Applications Low Side Load Switch DC
NTNS3164NZT5G. Small Signal MOSFET. 20 V, 361 ma, Single N Channel, SOT 883 (XDFN3) 1.0 x 0.6 x 0.4 mm Package
NTNS36NZ Small Signal MOSFET V, 36 ma, Single N Channel, SOT 883 (XDFN3). x.6 x. mm Package Features Single N Channel MOSFET Ultra Low Profile SOT 883 (XDFN3). x.6 x. mm for Extremely Thin Environments
NTJS4405N, NVJS4405N. Small Signal MOSFET. 25 V, 1.2 A, Single, N Channel, SC 88
NTJSN, NVJSN Small Signal MOSFET V,. A, Single, N Channel, SC 88 Features Advance Planar Technology for Fast Switching, Low R DS(on) Higher Efficiency Extending Battery Life AEC Q Qualified and PPAP Capable
NGD18N40CLBT4G. Ignition IGBT 18 Amps, 400 Volts N Channel DPAK. 18 AMPS 400 VOLTS V CE(on) 2.0 I C = 10 A, V GE 4.5 V
NGD8NCLB Ignition IGBT 8 Amps, Volts N Channel DPAK This Logic Level Insulated Gate Bipolar Transistor (IGBT) features monolithic circuitry integrating ESD and Over Voltage clamped protection for use in