MARKING DIAGRAMS* ORDERING INFORMATION 8 1 SO 8 D SUFFIX CASE 751 KEP51 ALYW HEP51 ALYW 8 1 TSSOP 8 DT SUFFIX CASE 948R KP51 ALYW

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1 The MC0/EP5 is a differential clock flip flop with reset. The device is functionally equivalent to the E5 and VE5 devices. The reset input is an asynchronous, level triggered signal. ata enters the master portion of the flip flop when the clock is OW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EP5 allow the device to be used as a negative edge triggered flip-flop. The differential input employs clamp circuitry to maintain stability under open input conditions. When left open, the CK input will be pulled down to V EE and the CK input will be biased at V CC /2. The Series contains temperature compensation. 350 ps Typical Propagation elay Maximum Frequency > 3 GHz Typical PEC Mode Operating Range: V CC = 3.0 V to 5.5 V with V EE = 0 V NEC Mode Operating Range: V CC = 0 V with V EE = 3.0 V to 5.5 V Open Input efault State Safety Clamp on Inputs SO SUFFIX CASE 75 TSSOP T SUFFIX CASE 94R H = MC0 K = MC A = Assembly ocation MARKING IAGRAMS* HEP5 AYW HP5 AYW KEP5 AYW KP5 AYW = Wafer ot Y = Year W = Work Week *For additional information, see Application Note AN002/ ORERING INFORMATION evice Package Shipping MC0EP5 SO 9 Units/Rail MC0EP5R2 SO 2500 Tape & Reel MCEP5 SO 9 Units/Rail MCEP5R2 SO 2500 Tape & Reel MC0EP5T TSSOP Units/Rail MC0EP5TR2 TSSOP 2500 Tape & Reel MCEP5T TSSOP Units/Rail MCEP5TR2 TSSOP 2500 Tape & Reel Semiconductor Components Industries, C, 200 April, 200 Rev. 3 Publication Order Number: MC0EP5/

2 MC0EP5, MCEP5 PIN ESCRIPTION RESET 2 R 7 V CC Q PIN CK*, CK* FUNCTION EC Clock Inputs Reset* EC Asynchronous Reset * EC ata Input Q, Q EC ata Outputs Flip-Flop V CC V EE Positive Supply Negative Supply CK 3 6 Q * Pins will default OW when left open. TRUTH TABE CK 4 5 V EE H X R H CK Z Z X Q H Figure. ead Pinout (Top View) and ogic iagram Z = OW to HIGH Transition ATTRIBUTES Internal Input Pulldown Resistor Internal Input Pullup Resistor ES Protection Characteristics Human Body Model Machine Model Charged evice Model Value 75 k N/A > 2 kv > 200 V > 2 kv Moisture Sensitivity, Indefinite Time Out of rypack (Note.) evel Flammability Rating Oxygen Index U 94 code V 0 A / 2 to 34 Transistor Count Meets or exceeds JEEC Spec EIA/JES7 IC atchup Test. For additional information, see Application Note AN003/. 65 evices MAXIMUM RATINGS (Note 2.) Symbol Parameter Condition Condition 2 Rating Units V CC PEC Mode Power Supply V EE = 0 V 6 V V EE NEC Mode Power Supply V CC = 0 V 6 V V I PEC Mode Input Voltage V EE = 0 V V I V CC 6 V NEC Mode Input Voltage V CC = 0 V V I V EE 6 V I out Output Current Continuous Surge TA Operating Temperature Range 40 to +5 C T stg Storage Temperature Range 65 to +50 C θ JA Thermal Resistance (Junction to Ambient) 0 FPM 500 FPM SOIC SOIC θ JC Thermal Resistance (Junction to Case) std bd SOIC 4 to 44 C/W θ JA Thermal Resistance (Junction to Ambient) 0 FPM 500 FPM TSSOP TSSOP θ JC Thermal Resistance (Junction to Case) std bd TSSOP 4 to 44 C/W T sol Wave Solder <2 to 3 24 C 265 C 2. Maximum Ratings are those values beyond which device damage may occur ma ma C/W C/W C/W C/W 2

3 MC0EP5, MCEP5 0EP C CHARACTERISTICS, PEC V CC = 3.3 V, V EE = 0 V (Note 3.) 40 C 25 C 5 C I EE Power Supply Current ma V OH Output HIGH Voltage (Note 4.) mv V O Output OW Voltage (Note 4.) mv V IH Input HIGH Voltage (Single Ended) mv V I Input OW Voltage (Single Ended) mv Range (ifferential) (Note 5.) V I IH Input HIGH Current µa I I Input OW Current µa 3. Input and output parameters vary : with V CC. V EE can vary +0.3 V to 2.2 V. 4. All loading with 50 ohms to V CC 2.0 volts. 5. min varies : with V EE, max varies : with V CC. The range is referenced to the most positive side of the differential 0EP C CHARACTERISTICS, PEC V CC = 5.0 V, V EE = 0 V (Note 6.) 40 C 25 C 5 C I EE Power Supply Current ma V OH Output HIGH Voltage (Note 7.) mv V O Output OW Voltage (Note 7.) mv V IH Input HIGH Voltage (Single Ended) mv V I Input OW Voltage (Single Ended) mv Range (ifferential) (Note.) V I IH Input HIGH Current µa I I Input OW Current µa 6. Input and output parameters vary : with V CC. V EE can vary +2.0 V to 0.5 V. 7. All loading with 50 ohms to V CC 2.0 volts.. min varies : with V EE, max varies : with V CC. The range is referenced to the most positive side of the differential 0EP C CHARACTERISTICS, NEC V CC = 0 V, V EE = 5.5 V to 3.0 V (Note 9.) 40 C 25 C 5 C I EE Power Supply Current ma V OH Output HIGH Voltage (Note 0.) mv V O Output OW Voltage (Note 0.) mv V IH Input HIGH Voltage (Single Ended) mv V I Input OW Voltage (Single Ended) mv Range (ifferential) (Note.) V EE V EE V EE V I IH Input HIGH Current µa I I Input OW Current µa 9. Input and output parameters vary : with V CC. 0.All loading with 50 ohms to V CC 2.0 volts.. min varies : with V EE, max varies : with V CC. The range is referenced to the most positive side of the differential 3

4 MC0EP5, MCEP5 EP C CHARACTERISTICS, PEC V CC = 3.3 V, V EE = 0 V (Note 2.) 40 C 25 C 5 C I EE Power Supply Current ma V OH Output HIGH Voltage (Note 3.) mv V O Output OW Voltage (Note 3.) mv V IH Input HIGH Voltage (Single Ended) mv V I Input OW Voltage (Single Ended) mv Range (ifferential) (Note 4.) V I IH Input HIGH Current µa I I Input OW Current µa 2.Input and output parameters vary : with V CC. V EE can vary +0.3 V to 2.2 V. 3.All loading with 50 ohms to V CC 2.0 volts. 4. min varies : with V EE, max varies : with V CC. The range is referenced to the most positive side of the differential EP C CHARACTERISTICS, PEC V CC = 5.0 V, V EE = 0 V (Note 5.) 40 C 25 C 5 C I EE Power Supply Current ma V OH Output HIGH Voltage (Note 6.) mv V O Output OW Voltage (Note 6.) mv V IH Input HIGH Voltage (Single Ended) mv V I Input OW Voltage (Single Ended) mv Range (ifferential) (Note 7.) V I IH Input HIGH Current µa I I Input OW Current µa 5.Input and output parameters vary : with V CC. V EE can vary +2.0 V to 0.5 V. 6.All loading with 50 ohms to V CC 2.0 volts. 7. min varies : with V EE, max varies : with V CC. The range is referenced to the most positive side of the differential EP C CHARACTERISTICS, NEC V CC = 0 V, V EE = 5.5 V to 3.0 V (Note.) 40 C 25 C 5 C I EE Power Supply Current ma V OH Output HIGH Voltage (Note 9.) mv V O Output OW Voltage (Note 9.) mv V IH Input HIGH Voltage (Single Ended) mv V I Input OW Voltage (Single Ended) mv Range (ifferential) (Note 20.) V EE V EE V EE V I IH Input HIGH Current µa I I Input OW Current µa.input and output parameters vary : with V CC. 9.All loading with 50 ohms to V CC 2.0 volts. 20. min varies : with V EE, max varies : with V CC. The range is referenced to the most positive side of the differential 4

5 MC0EP5, MCEP5 AC CHARACTERISTICS V CC = 0 V; V EE = 3.0 V to 5.5 V or V CC = 3.0 V to 5.5 V; V EE = 0 V (Note 2.) 40 C 25 C 5 C f max Maximum Frequency (See Figure 2. F max /JITTER) > 3 > 3 > 3 GHz t PH, t PH Propagation elay to Output ifferential CK, CK to Q, Q ps RESET to Q, Q t RR Reset Recovery ps t S t H Setup Time Hold Time 0 40 ps t PW Minimum Pulse Width RESET ps t JITTER Cycle to Cycle Jitter (See Figure 2. F max /JITTER).2 <.2 <.2 < ps t r Output Rise/Fall Times Q, Q t f (20% 0%) Measured using a 750 mv source, 50% duty cycle clock source. All loading with 50 ohms to V CC 2.0 V. ps V OUTpp (mv) ÉÉÉÉÉ (JITTER) FREQUENCY (MHz) Figure 2. F max /Jitter Measured Simulated JITTER OUT ps (RMS) ÉÉ 5

6 MC0EP5, MCEP5 river evice Q Qb b Receiver evice V TT V TT = V CC 2.0 V Figure 3. Typical Termination for Output river and evice Evaluation (See Application Note AN020 Termination of EC ogic evices.) Resource Reference of Application Notes AN404 ECinPS Circuit Performance at Non Standard V IH evels AN405 EC Clock istribution Techniques AN406 esigning with PEC (EC at +5.0 V) AN504 Metastability and the ECinPS Family AN56 Interfacing Between VS and EC AN650 Using Wire OR Ties in ECinPS esigns AN672 The EC Translator Guide AN00 Odd Number Counters esign AN002 Marking and ate Codes AN009 ECinPS Plus Spice I/O Model Kit AN020 Termination of EC ogic evices For an updated list of Application Notes, please see our website at. 6

7 MC0EP5, MCEP5 PACKAGE IMENSIONS X B Y Z H G A S C SO SUFFIX PASTIC SOIC PACKAGE CASE ISSUE W N X 45 M K J TSSOP T SUFFIX PASTIC TSSOP PACKAGE CASE 94R 02 ISSUE A 2X /2 PIN IENT 5 x A V K REF 4 B U M F T C G ETAI E ETAI E W 7

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