Watts T. W/ C Operating and Storage Junction. T J, T stg

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1 The BUS98 and BUS98A transistors are designed for high voltage, high speed, power switching in inductive circuits where fall time is critical. They are particularly suited for line operated SWITCHMODE applications such as: Switching Regulators Inverters Solenoid and Relay Drivers Motor Controls Deflection Circuits Fast Turn Off Times 60 ns Inductive Fall Time 25C (Typ) 120 ns Inductive Crossover Time 25C (Typ) Operating Temperature Range 65 to +200C 100C Performance Specified for: Reverse Biased SOA with Inductive Loads Switching Times with Inductive Loads Saturation Voltages Leakage Currents (125C) MAXIMUM RATINGS Rating Symbol BUS98 BUS98A Î Unit Collector Emitter Voltage V CEO(sus) Î Vdc Collector Emitter Voltage V CEV Î Vdc Emitter Base Voltage V EB 7 Î Vdc Collector Current Continuous I C 30 Î Adc Peak (1) I Overload CM 60 I oi 120 Î Base Current Continuous I B 10 Î Adc Peak (1) I BM 30 Î Total Power Dissipation T C = 25C P D 250 Î Watts T C = 100C 142 Derate above 25C ÎÎ 1.42 Î W/C Operating and Storage Junction T J, T stg 65 to +200 Î C Temperature Range THERMAL CHARACTERISTICS Characteristic Symbol Max Î Unit Thermal Resistance, R θjc 0.7 Î C/W Junction to Case Maximum Lead Temperature T L 275 for Soldering Purposes: Î C Î 1/8 from Case for 5 Seconds 30 AMPERES NPN SILICON POWER TRANSISTORS 400 AND 450 VOLTS (BVCEO) 250 WATTS V (BVCES) CASE 1 07 TO 204AA (1) Pulse Test: Pulse Width = 5 ms, Duty Cycle 10%. Designer s and SWITCHMODE are trademarks of ON Semiconductor, Inc. Semiconductor Components Industries, LLC, 2001 March, 2001 Rev. 9 1 Publication Order Number: BUS98/D

2 ELECTRICAL CHARACTERISTICS (T C = 25C unless otherwise noted) Î Characteristic Symbol Î Min Typ Î Max Unit OFF CHARACTERISTICS (1) Î Collector Emitter Sustaining Voltage (Table 1) V CEO(sus) Î (I C = 200 ma, I B = 0) L = 25 mh BUS98 ÎÎ 400 Î Vdc BUS98A 450 Collector Cutoff Current I Î (V CEV = Rated Value, V BE(off) = 1.5 Vdc) CEV madc Î (V CEV = Rated Value, V BE(off) = 1.5 Vdc, T C = 125C) ÎÎ 0.4 Î 4.0 Î Collector Cutoff Current I CER madc (V Î CE = Rated V CEV, R BE = 10 Ω) T C = 25 C T C ÎÎ 1.0 = 125 C 6.0 Î Emitter Cutoff Current I Î (V EB = 7 Vdc, I C = 0) EBO Î 0.2 madc Î Emitter Base Breakdown Voltage 7.0 Vdc Î (I E = 100 ma I C = 0) SECOND BREAKDOWN Î Second Breakdown Collector Current with Base Forward Biased I S/b See Figure 12 Î Clamped Inductive SOA with Base Reverse Biased RBSOA See Figure 13 ON CHARACTERISTICS (1) Î DC Current Gain h FE Î 8 Î (I Î C = 20 Adc, V CE = 5 Vdc) BUS98 (I C = 16 Adc, V CE = 5 V) BUS98A Î Collector Emitter Saturation Voltage V CE(sat) Vdc Î (I C = 20 Adc, I B = 4 Adc) BUS98 ÎÎ Î 1.5 (I Î C = 30 Adc, I B = 8 Adc) 3.5 (I C = 20 Adc, I B = 4 Adc, T C = 100C) ÎÎ Î 2.0 (I Î C = 16 Adc, I B = 3.2 Adc) BUS98A (I C = 24 Adc, I B ÎÎ 1.5 = 5 Adc) 5.0 Î (I C = 16 Adc, I B = 3.2 Adc, T C = 100C) ÎÎ Î 2.0 Î Base Emitter Saturation Voltage V BE(sat) Vdc Î (I C = 20 Adc, I B = 4 Adc) BUS98 ÎÎ Î 1.6 (I Î C = 20 Adc, I B = 4 Adc, T C = 100C) 1.6 (I C = 16 Adc, I B = 3.2 Adc) BUS98A ÎÎ Î 1.6 Î (I C = 16 Adc, I B = 3.2 Adc, T C = 100C) ÎÎ Î 1.6 DYNAMIC CHARACTERISTICS Î Output Capacitance C ob Î Î 700 pf (V CB = 10 Vdc, I E = 0, f test = 100 khz) SWITCHING CHARACTERISTICS Restive Load (Table 1) Delay Time t d Î 0.1 Î 0.2 µs (V Rise Time ÎÎ CC = 250 Vdc, I C = 20 A, t r Î 0.4 Î 0.7 I B1 = 4.0 A, t p = 30 µs, Storage Time ÎÎ Duty Cycle 2%, V BE(off) = 5 V) t s Î 1.55 Î 2.3 (for BUS98A: I =16A =32A) Fall Time ÎÎ C A, Ib t f Î 0.2 Î 0.4 Inductive Load, Clamped (Table 1) Storage Time Î ÎÎ 1.55 Î µs V EBO I C(pk) = 20 A (BUS98) t sv I b1 = 4 A (T =25C) C t V fi BE(off) = 5 V, V CE(c1) = 250 V) t sv I C(pk) = 16 A (BUS98A (T C = 100C) t ) c lb 1 = 3.2 A) tfi Fall Time Î Î 0.06 Î Storage Time Î Î 1.8 Î 2.8 Crossover TimeÎ( C ) Î 0.3 Î 0.6 Fall Time ÎÎ Î 0.17 Î 0.35 (1) Pulse Test: PW = 300 µs, Duty Cycle 2%. 2

3 DC CHARACTERISTICS Figure 1. DC Current Gain Figure 2. Collector Saturation Region β β Figure 3. Collector Emitter Saturation Voltage Figure 4. Base Emitter Voltage µ Figure 5. Collector Cutoff Region Figure 6. Capacitance 3

4 Table 1. Test Conditions for Dynamic Performance V CEO(sus) RBSOA AND INDUCTIVE SWITCHING RESISTIVE SWITCHING INPUT CONDITIONS PW Varied to Attain I C = 100 ma µ µ µ µ TURN ON TIME I B1 adjusted to obtain the forced h FE desired TURN OFF TIME Use inductive switching driver as the input to the resistive test circuit. CIRCUIT VALUES L coil = 25 mh, V CC = 10 V R coil = 0.7 Ω L coil = 180 µh R coil = 0.05 Ω V CC = 20 V V clamp = 250 V V CC = 250 V Pulse Width = 10 µs TEST CIRCUITS INDUCTIVE TEST CIRCUIT OUTPUT WAVEFORMS t 1 Adjusted to Obtain I C t1 L coil (IC(pk)) VCC t2 L coil (IC(pk)) Vclamp Test Equipment Scope Tektronix 475 or Equivalent RESISTIVE TEST CIRCUIT β Figure 7. Inductive Switching Measurements Figure 8. Peak Reverse Current 4

5 SWITCHING TIMES NOTE In resistive switching circuits, rise, fall, and storage times have been defined and apply to both current and voltage waveforms since they are in phase. However, for inductive loads which are common to SWITCHMODE power supplies and hammer drivers, current and voltage waveforms are not in phase. Therefore, separate measurements must be made on each waveform to determine the total switching time. For this reason, the following new terms have been defined. t sv = Voltage Storage Time, 90% I B1 to 10% V clamp t rv = Voltage Rise Time, 10 90% V clamp t fi = Current Fall Time, 90 10% I C t ti = Current Tail, 10 2% I C t c = Crossover Time, 10% V clamp to 10% I C An enlarged portion of the inductive switching waveforms is shown in Figure 7 to aid in the visual identity of these terms. For the designer, there is minimal switching loss during storage time and the predominant switching power losses occur during the crossover interval and can be obtained using the standard equation from AN 222: P SWT = 1/2 V CC I C (t c ) f In general, t rv + t fi t c. However, at lower test currents this relationship may not be valid. As is common with most switching transistors, resistive switching is specified at 25C and has become a benchmark for designers. However, for designers of high frequency converter circuits, the user oriented specifications which make this a SWITCHMODE transistor are the inductive switching speeds (t c and t sv ) which are guaranteed at 100C.INDUCTIVE SWITCHING µ µ β Figure 9. Storage Time, t sv β Figure 10. Crossover and Fall Times β µ µ β Figure 11. Turn Off Times versus Forced Gain Figure 12. Turn Off TM Times versus Ib 2 /Ib 1 5

6 The Safe Operating Area figures shown in Figures 12 and 13 are specified for these devices under the test conditions shown. Figure 13. Forward Bias Safe Operating Area µ Figure 14. Reverse Bias Safe Operating Area SAFE OPERATING AREA INFORMATION FORWARD BIAS There are two limitations on the power handling ability of a transistor: average junction temperature and second breakdown. Safe operating area curves indicate I C V CE limits of the transistor that must be observed for reliable operation, i.e., the transistor must not be subjected to greater dissipation than the curves indicate. The data of Figure 13 is based on T C = 25C; T J(pk) is variable depending on power level. Second breakdown pulse limits are valid for duty cycles to 10% but must be derated when T C 25C. Second breakdown limitations do not derate the same as thermal limitations. Allowable current at the voltages shown on Figure 13 may be found at any case temperature by using the appropriate curve on Figure 15. T J(pk) may be calculated from the data in Figure 11. At high case temperatures, thermal limitations will reduce the power that can be handled to values less than the limitations imposed by second breakdown. REVERSE BIAS For inductive loads, high voltage and high current must be sustained simultaneously during turn off, in most cases, with the base to emitter junction reverse biased. Under these conditions the collector voltage must be held to a safe level at or below a specific value of collector current. This can be accomplished by several means such as active clamping, RC snubbing, load line shaping, etc. The safe level for these devices is specified as Reverse Bias Safe Operating Area and represents the voltage current conditions during reverse biased turn off. This rating is verified under clamped conditions so that the device is never subjected to an avalanche mode. Figure 14 gives RBSOA characteristics. Figure 15. Power Derating 6

7 θ θ θ θ Figure 16. Thermal Response OVERLOAD CHARACTERISTICS µ Figure 17. Rated Overload Safe Operating Area (OLSOA) OLSOA OLSOA applies when maximum collector current is limited and known. A good example Is a circuit where an inductor is inserted between the transistor and the bus, which limits the rate of rise of collector current to a known value. If the transistor is then turned off within a specified amount of time, the magnitude of collector current is also known. Maximum allowable collector emitter voltage versus collector current is plotted for several pulse widths. (Pulse width is defined as the time lag between the fault condition and the removal of base drive.) Storage time of the transistor has been factored into the curve. Therefore, with bus voltage and maximum collector current known, Figure 17 defines the maximum time which can be allowed for fault detection and shutdown of base drive. OLSOA is measured in a common base circuit (Figure 19) which allows precise definition of collector emitter voltage and collector current. This is the same circuit that is used to measure forward bias safe operating area. Ω Ω Ω µ Notes: V CE = V CC + V BE Adjust pulsed current source for desired I C, t p µ Figure 18. Figure 17. I C = f (dv/dt) Figure 19. Overload SOA Test Circuit 7

8 PACKAGE DIMENSIONS TO 204AA (TO 3) CASE 1 07 ISSUE Z V H E 2 1 A N U C D 2 PL K L G Q T Y B SWITCHMODE is a trademark of Semiconductor Components Industries, LLC. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION NORTH AMERICA Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada ONlit@hibbertco.com Fax Response Line: or Toll Free USA/Canada N. American Technical Support: Toll Free USA/Canada EUROPE: LDC for ON Semiconductor European Support German Phone: (+1) (Mon Fri 2:30pm to 7:00pm CET) ONlit german@hibbertco.com French Phone: (+1) (Mon Fri 2:00pm to 7:00pm CET) ONlit french@hibbertco.com English Phone: (+1) (Mon Fri 12:00pm to 5:00pm GMT) ONlit@hibbertco.com EUROPEAN TOLL FREE ACCESS*: *Available from Germany, France, Italy, UK, Ireland CENTRAL/SOUTH AMERICA: Spanish Phone: (Mon Fri 8:00am to 5:00pm MST) ONlit spanish@hibbertco.com Toll Free from Mexico: Dial for Access then Dial ASIA/PACIFIC: LDC for ON Semiconductor Asia Support Phone: (Tue Fri 9:00am to 1:00pm, Hong Kong Time) Toll Free from Hong Kong & Singapore: ONlit asia@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center Nishi Gotanda, Shinagawa ku, Tokyo, Japan Phone: r14525@onsemi.com ON Semiconductor Website: For additional information, please contact your local Sales Representative. 8 BUS98/D