MC14066BF. MARKING DIAGRAMS. MAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.) ORDERING INFORMATION PDIP 14 P SUFFIX CASE 646

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1 The MC14066B consists of four independent switches capable of controlling either digital or analog signals. This quad bilateral switch is useful in signal gating, chopper, modulator, demodulator and CMOS logic implementation. The MC14066B is designed to be pin for pin compatible with the MC14016B, but has much lower ON resistance. Input voltage swings as large as the full supply voltage can be controlled via each independent control input. Triple Diode Protection on All Control Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Linearized Transfer Characteristics Low Noise 12 nv/ Cycle, f 1.0 khz typical Pin for Pin Replacement for CD4016, CD4016, MC14016B For Lower R ON, Use The HC4066 High Speed CMOS Device MAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.) Symbol Parameter Value Unit V DD DC Supply Voltage Range 0.5 to V V in, V out Input or Output Voltage Range (DC or Transient) 0.5 to V DD V I in Input Current (DC or Transient) per Control Pin ±10 ma I SW Switch Through Current ±25 ma P D Power Dissipation, per Package (Note 3.) 500 mw T A Ambient Temperature Range 55 to +125 C T stg Storage Temperature Range 65 to +150 C T L Lead Temperature (8 Second Soldering) 260 C 2. Maximum Ratings are those values beyond which damage to the device may occur. 3. Temperature Derating: Plastic P and D/DW Packages: 7.0 mw/c From 65C To 125C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, V in and V out should be constrained to the range V SS (V in or V out ) V DD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V SS or V DD ). Unused outputs must be left open. A WL, L YY, Y WW, W = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device Package Shipping MC14066BCP PDIP /Box MC14066BD SOIC 14 55/Rail MC14066BDR2 SOIC /Tape & Reel MC14066BDT MC14066BF PDIP 14 P SUFFIX CASE 646 SOIC 14 D SUFFIX CASE 751A TSSOP 14 DT SUFFIX CASE 948G SOEIAJ 14 F SUFFIX CASE 965 TSSOP 14 SOEIAJ 14 MARKING DIAGRAMS MC14066BCP AWLYYWW 14066B AWLYWW B ALYW MC14066B ALYW 96/Rail MC14066BDTEL TSSOP /Tape & Reel MC14066BDTR2 TSSOP /Tape & Reel See Note 1. MC14066BFEL SOEIAJ 14 See Note For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative. Semiconductor Components Industries, LLC, 2000 August, 2000 Rev. 4 1 Publication Order Number: MC14066B/D

2 PIN ASSIGNMENT BLOCK DIAGRAM LOGIC DIAGRAM AND TRUTH TABLE (1/4 OF DEVICE SHOWN) Control Switch 0=V SS OFF 1=V DD ON Logic Diagram Restrictions V SS V in V DD V SS V out V DD CIRCUIT SCHEMATIC (1/4 OF CIRCUIT SHOWN) Ω 2

3 Î ELECTRICAL CHARACTERISTICS 55C 25C Î 125C Characteristic Symbol V DD Test Conditions Min Max Min Typ (4.) Max Min Max Unit Î SUPPLY REQUIREMENTS (Voltages Referenced to V EE ) Power Supply Voltage V DD Î V Range Î Quiescent Current Per I Package DD 5.0 Control Inputs: µa 10 V in = V SS or V DD, Switch I/O: V SS V I/O V DD, and V switch 500 mv (5.) Total Supply Current I D(AV) 5.0 T A = 25C only The µa (0.07 µa/khz) f + I (Dynamic Plus Quiescent, Î 10 channel component, DD Typical (0.20 µa/khz) f + I Per Package 15 (V in V out )/R on, is DD not included.) (0.36 µa/khz) f + I DD Î CONTROL INPUTS (Voltages Referenced to V SS ) Low Level Input Voltage V IL 5.0 R on = per spec, 10 I off = per spec V High Level Input Voltage V IH 5.0 R on = per spec, V Î 10 I off = per spec Î Input Leakage Current I in 15 V in = 0 or V DD ± 0.1 ± ± 0.1 ± 1.0 µa Input Capacitance C in Î pf SWITCHES IN AND OUT (Voltages Referenced to V SS ) Recommended Peak to V I/O Channel On or Off 0 V DD 0 V DD 0 V DD V p p Peak Voltage Into or Out of the Switch Recommended Static or V Dynamic Voltage Across the Switch (5.) (Figure 1) switch Channel On mv Output Offset Voltage V OO V in = 0 V, No Load 10 µv ON Resistance R on 5.0 V switch 500 mv 10 (5.), Ω V in = V IL or V IH (Control), and V in = to V DD (Switch) ON Resistance Between R on Any Two Channels Î Ω in the Same Package Off Channel Leakage Current (Figure 6) I off 15 V in = V IL or V IH (Control) Channel to Î ±100 Î ± 0.05 ±100 ±1000 na Channel or Any One Channel Capacitance, Switch I/O C I/O Î Switch Off pf Capacitance, Feedthrough C (Switch Off) I/O 0.47 pf 4. Data labeled Typ is not to be used for design purposes, but is intended as an indication of the IC s potential performance. 5. For voltage drops across the switch ( V switch ) > 600 mv ( > 300 mv at high temperature), excessive V DD current may be drawn; i.e. the current out of the switch may contain both V DD and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. (See first page of this data sheet.) 3

4 Î ELECTRICAL CHARACTERISTICS (6.) (C L = 50 pf, T A = 25C unless otherwise noted.) V DD Characteristic Symbol Vdc Min Typ (7.) Max Unit Î Propagation Delay Times V SS = 0 Vdc t Input to Output (R L = 10 kω) PLH, t PHL ns t PLH, t PHL = (0.17 ns/pf) C L ns t PLH, t PHL = (0.08 ns/pf) C L ns t PLH, t PHL = (0.06 ns/pf) C L ns Control to Output (R L = 1 kω) (Figure 2) t PHZ ns Output 1 to High Impedance Output 0 to High Impedance t PLZ ns Î High Impedance to Output 1 t PZH ns High Impedance to Output 0 t PZL ns Second Harmonic Distortion V SS = 5 Vdc (V in = 1.77 Vdc, RMS 0.0 Vdc, % R L = 10 kω, f = 1.0 khz) Bandwidth (Switch ON) (Figure 3) V SS = 5 Vdc (R L = 1 kω, 20 Log (V out /V in ) = 3 db, C L = 50 pf, MHz V in = 5 V p p ) Feedthrough Attenuation (Switch OFF) V SS = 5 Vdc (V in = 5 V p p, R L = 1 kω, f in db = 1.0 MHz) (Figure 3) Channel Separation (Figure 4) V SS = 5 Vdc (V in = 5 V p p, R L = 1 kω, f in = 8.0 MHz) db (Switch A ON, Switch B OFF) Î Crosstalk, Control Input to Signal Output (Figure 5) V SS = 5 Vdc (R 1 = 1 kω, R L = 10 kω, Control t TLH = t THL = 20 ns) mv p p 6. The formulas given are for the typical characteristics only at 25C. 7. Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance. 4

5 TEST CIRCUITS Figure 1. V Across Switch Figure 2. Turn On Delay Time Test Circuit and Waveforms Figure 3. Bandwidth and Feedthrough Attenuation Figure 4. Channel Separation Figure 5. Crosstalk, Control to Output Figure 6. Off Channel Leakage 5

6 Ω Figure 7. Channel Resistance (R ON ) Test Circuit TYPICAL RESISTANCE CHARACTERISTICS Figure 8. V DD = 7.5 V, V SS = 7.5 V Figure 9. V DD = 5.0 V, V SS = 5.0 V Figure 10. V DD = 2.5 V, V SS = 2.5 V Figure 11. Comparison at 25 C, V DD = V SS 6

7 APPLICATIONS INFORMATION Figure A illustrates use of the Analog Switch. The 0 to 5 volt digital control signal is used to directly control a 5 volt peak to peak analog signal. The digital control logic levels are determined by V DD and V SS. The V DD voltage is the logic high voltage, the V SS voltage is logic low. For the example, V DD = + 5 V = logic high at the control inputs; V SS = GND = 0 V = logic low. The maximum analog signal level is determined by V DD and V SS. The analog voltage must not swing higher than V DD or lower than V SS. The example shows a 5 volt peak to peak signal which allows no margin at either peak. If voltage transients above V DD and/or below V SS are anticipated on the analog channels, external diodes (D x ) are recommended as shown in Figure B. These diodes should be small signal types able to absorb the maximum anticipated current surges during clipping. The absolute maximum potential difference between V DD and V SS is 18.0 volts. Most parameters are specified up to 15 volts which is the recommended maximum difference between V DD and V SS. + Figure A. Application Example Figure B. External Germanium or Schottky Clipping Diodes 7

8 PACKAGE DIMENSIONS P SUFFIX PLASTIC DIP PACKAGE CASE ISSUE M B T N A F L C K J H G D 14 PL M 8

9 PACKAGE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751A 03 ISSUE F A B P 7 PL T G D 14 PL K C R X 45 F M J 9

10 PACKAGE DIMENSIONS DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948G 01 ISSUE O L T 2X L/2 PIN 1 IDENT. D C 14X K REF N M B U A V G H N J J1 F DETAIL E K K1 ÇÇÇ ÉÉ SECTION N N DETAIL E W 10

11 PACKAGE DIMENSIONS Z D e b E A H E A 1 VIEW P F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE ISSUE O M L E Q 1 L DETAIL P c 11

12 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION NORTH AMERICA Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada ONlit@hibbertco.com Fax Response Line: or Toll Free USA/Canada N. American Technical Support: Toll Free USA/Canada EUROPE: LDC for ON Semiconductor European Support German Phone: (+1) (Mon Fri 2:30pm to 7:00pm CET) ONlit german@hibbertco.com French Phone: (+1) (Mon Fri 2:00pm to 7:00pm CET) ONlit french@hibbertco.com English Phone: (+1) (Mon Fri 12:00pm to 5:00pm GMT) ONlit@hibbertco.com EUROPEAN TOLL FREE ACCESS*: *Available from Germany, France, Italy, UK CENTRAL/SOUTH AMERICA: Spanish Phone: (Mon Fri 8:00am to 5:00pm MST) ONlit spanish@hibbertco.com ASIA/PACIFIC: LDC for ON Semiconductor Asia Support Phone: (Tue Fri 9:00am to 1:00pm, Hong Kong Time) Toll Free from Hong Kong & Singapore: ONlit asia@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center Nishi Gotanda, Shinagawa ku, Tokyo, Japan Phone: r14525@onsemi.com ON Semiconductor Website: For additional information, please contact your local Sales Representative. 12 MC14066B/D