NB4N855S 3.3 V, 1.5 Gb/s Dual AnyLevel to LVDS Receiver/Driver/Buffer/ Translator
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1 3.3 V,.5 Gb/s ual AnyLevel to LVS Receiver/river/Buffer/ Translator escription NB4N55S is a clock or data Receiver/river/Buffer/Translator capable of translating AnyLevel input signal (LVPECL, CML, HSTL, LVS, or LVTTL/LVCMOS) to LVS. epending on the distance, noise immunity of the system design, and transmission line media, this device will receive, drive or translate data or clock signals up to.5 Gb/s or.0 GHz, respectively. This device is pin for pin plug in compatible to the SY5555V in a 3.3 V applications. The NB4N55S has a wide input common mode range of GN + 50 mv to V CC 50 mv. This feature is ideal for translating differential or single ended data or clock signals to 350 mv typical LVS output levels. The device is offered in a small 0 lead MSOP package. NB4N55S is targeted for data, wireless and telecom applications as well as high speed logic interface where jitter and package size are main requirements. Application notes, models, and support documentation are available at Features Guaranteed Input Clock Frequency up to.0 GHz Guaranteed Input ata Rate up to.5 Gb/s 490 ps Maximum Propagation elay.0 ps Maximum RMS Jitter 0 ps Maximum Rise/Fall Times Single Power Supply; V CC = 3.3 V ±0% Temperature Compensated TIA/EIA 644 Compliant LVS Outputs GN + 50 mv to V CC 50 mv V CMR Range This is a Pb Free evice Micro 0 M SUFFIX CASE 46B A Y W = Assembly Location = Year = Work Week = Pb Free Package *For additional marking information, refer to Application Note AN002/. 0 0 MARKING IAGRAM* 0 55S AYW (Note: Microdot may be in either location) Q0 Q0 Q Q Functional Block iagram evice J = ps ORERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page of this data sheet. TIME (33 ps/div) Figure. Typical Output Waveform at.5 Gb/s with K2.5 (V INPP = 00 mv, Input Signal J = 24 ps) Semiconductor Components Industries, LLC, June, Rev. 4 Publication Order Number: NB4N55S/
2 0 0 V CC Q0 3 Q0 4 Q GN 5 6 Q Figure 2. Pin Configuration and Block iagram (Top View) Table. PIN ESCRIPTION Pin Name I/O escription 0 LVPECL, CML, LVCMOS, LVTTL, LVS 2 0 LVPECL, CML, LVCMOS, LVTTL, LVS 3 LVPEL, CML, LVS LVCMOS, LVTTL 4 LVPECL, CML, LVS LVCMOS LVTTL Noninverted ifferential Clock/ata 0 Input. Inverted ifferential Clock/ata 0 Input. Noninverted ifferential Clock/ata Input. Inverted ifferential Clock/ata Input. 5 GN Ground. 0 V. 6 Q LVS Output Inverted Q output. Typically loaded with 00 receiver termination resistor across differential pair. Q LVS Output Noninverted Q output. Typically loaded with 00 receiver termination resistor across differential pair. Q0 LVS Output Inverted Q0 output. Typically loaded with 00 receiver termination resistor across differential pair. 9 Q0 LVS Output Noninverted Q0 output. Typically loaded with 00 receiver termination resistor across differential pair. 0 V CC Positive Supply Voltage. 2
3 Table 2. ATTRIBUTES Characteristics Value Moisture Sensitivity (Note ) Pb Pkg Pb Free Pkg Micro 0 Level Level Flammability Rating Oxygen Index: 2 to 34 UL 94 V 0.25 in ES Protection Human Body Model Machine Model Charged evice Model > 2 kv > 0 V > kv Transistor Count 2 Meets or exceeds JEEC Spec EIA/JES IC Latchup Test. For additional information, see Application Note AN003/. Table 3. MAXIMUM RATINGS Symbol Parameter Condition Condition 2 Rating Unit V CC Positive Power Supply GN = 0 V 3. V V I Positive Input GN = 0 V V I = V CC 3. V I OSC Output Short Circuit Current Line to Line (Q to Q) Line to End (Q or Q to GN) Q to Q Q or Q to GN Continuous Continuous 2 24 ma T A Operating Temperature Range Micro 0 40 to +5 C T stg Storage Temperature Range 65 to +50 C JA Thermal Resistance (Junction to Ambient) (Note 2) 0 lfpm 500 lfpm Micro 0 Micro 0 32 C/W C/W JC Thermal Resistance (Junction to Case) S2P (Note 4) Micro 0 40 C/W T sol Wave Solder Pb Pb Free <3 24 C <3 260 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 2. JEEC standard multilayer board S2P ( signal, 2 power) C 3
4 Table 4. C CHARACTERISTICS, CLOCK INPUTS, LVS OUTPUTS V CC = 3.0 V to 3.6 V, GN = 0 V, T A = 40 C to +5 C Symbol Characteristic Min Typ Max Unit I CC Power Supply Current (Note 3) ma IFFERENTIAL INPUTS RIVEN SINGLE ENE (Figures 0 and 2) V th Input Threshold Reference Voltage Range (Note 4) GN +00 V CC 00 mv V IH Single ended Input HIGH Voltage V th + 00 V CC mv V IL Single ended Input LOW Voltage GN V th 00 mv IFFERENTIAL INPUTS RIVEN IFFERENTIALLY (Figures and 3) V IH ifferential Input HIGH Voltage 00 V CC mv V IL ifferential Input LOW Voltage GN V CC 00 mv V CMR Input Common Mode Range (ifferential Configuration) GN + 50 V CC 50 mv V I ifferential Input Voltage (V IH V IL ) 00 V CC mv LVS OUTPUTS (Note 5) V O ifferential Output Voltage mv V O Change in Magnitude of V O for Complementary Output States (Note 6) mv V OS Offset Voltage (Figure 9) mv V OS Change in Magnitude of V OS for Complementary Output States (Note 6) mv V OH Output HIGH Voltage (Note ) mv V OL Output LOW Voltage (Note ) mv NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. x/x at the C level within V CMR and output pins loaded with R L = 00 across differential. 4. V th is applied to the complementary input when operating in single ended mode. 5. LVS outputs require 00 receiver termination resistor between differential pair. See Figure. 6. Parameter guaranteed by design verification not tested in production.. V OH max = V OS max + ½ V O max.. V OL max = V OS min ½ V O max. 4
5 Table 5. AC CHARACTERISTICS V CC = 3.0 V to 3.6 V, GN = 0 V; (Note 9) 40 C 25 C 5 C Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit V OUTPP Output Voltage Amplitude (@ V INPPMIN )f in.0 GHz (Figure 3) f in =.5 GHz mv f ATA Maximum Operating ata Rate Gb/s t PLH, t PHL ifferential Input to ifferential Output Propagation elay ps t SKEW uty Cycle Skew (Note 0) Within evice Skew (Note ) evice to evice Skew (Note 2) ps t JITTER RMS Random Clock Jitter (Note 3) f in =.0 GHz f in =.5 GHz eterministic Jitter (Note 4) f ATA = 622 Mb/s f ATA =.5 Gb/s f ATA = 2.4 Gb/s Crosstalk Induced Jitter (Note 5) ps V INPP Input Voltage Swing/Sensitivity (ifferential Configuration) (Note 6) 00 V CC GN 00 V CC GN 00 V CC GN mv t r Output Rise/Fall 250 MHz Q, Q t f (% 0%) ps NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit values are applied individually under normal operating conditions and not valid simultaneously. 9. Measured by forcing V INPPMIN with 50% duty cycle clock source and V CC 400 mv offset. All loading with an external R L = 00 across and of the receiver. Input edge rates 50 ps (% 0%). 0.See Figure differential measurement of t skew = t PLH t PHL for a nominal 50% differential clock input 250 MHz.. The worst case condition between Q0/Q0 and Q/Q from either 0/0 or /, when both outputs have the same transition. 2. Skew is measured between outputs under identical 250 MHz. 3.RMS jitter with 50% uty Cycle clock signal. 4.eterministic jitter with input NRZ data at PRBS 2 23 and K Crosstalk Induced Jitter is the additive eterministic jitter to channel one with channel two active both running at 622 Gb/s PRBS 2 23 as an asynchronous signals. 6. Input voltage swing is a single ended measurement operating in differential mode. 400 OUTPUT VOLTAGE AMPLITUE (mv) C 40 C 25 C INPUT CLOCK FREQUENCY (GHz) Figure 3. Output Voltage Amplitude (V OUTPP ) versus Input Clock Frequency (f in ) and Temperature (@ V CC = 3.3 V) 5
6 evice J = 6 ps evice J = 6 ps TIME (322 ps/div) TIME (322 ps/div) Figure 4. Typical Output Waveform at.5 Gb/s with 2 23 (V INPP = 00 mv (left) & V INPP = 400 mv (right), Input Signal J = 24 ps) evice J = 0 ps evice J = 0 ps TIME (0 ps/div) TIME (0 ps/div) Figure 5. Typical Output Waveform at 2.4 Gb/s with 2 23 (V INPP = 00 mv (left) & V INPP = 400 mv (right), Input Signal J = 30 ps) R C R C.25 k.25 k x.25 k I.25 k x Figure 6. Input Structure 6
7 Q Q V INPP = V IH () V IL () V OUTPP = V OH (Q) V OL (Q) t PHL t PLH Figure. AC Reference Measurement LVS river evice Q Q Z o = 50 Z o = HI Z Probe HI Z Probe Oscilloscope Figure. Typical LVS Termination for Output river and evice Evaluation Q N V OH V OS V O Q N V OL Figure 9. LVS Output V IH V th V IL V th Figure 0. ifferential Input riven Single Ended Figure. ifferential Inputs riven ifferentially V CC V IH(MAX) V CC V thmax V IHmax V IL V ILmax V IH V th V CMR V INPP = V IH V IL V IL V thmin GN V IHmin V ILmin V EE V IH V IL(MIN) Figure 2. V th iagram Figure 3. V CMR iagram
8 ORERING INFORMATION NB4N55SMR4G evice Package Shipping Micro 0 (Pb Free) 000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BR0/
9 PACKAGE IMENSIONS K PIN I G A B Micro 0 CASE 46B 03 ISSUE PL 0.0 (0.003) M T B S A S NOTES:. IMENSIONING AN TOLERANCING PER ANSI Y4.5M, CONTROLLING IMENSION: MILLIMETER. 3. IMENSION A OES NOT INCLUE MOL FLASH, PROTRUSIONS OR GATE BURRS. MOL FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEE (0.006) PER SIE. 4. IMENSION B OES NOT INCLUE INTERLEA FLASH OR PROTRUSION. INTERLEA FLASH OR PROTRUSION SHALL NOT EXCEE 0.25 (0.00) PER SIE B 0 OBSOLETE. NEW STANAR 46B (0.005) T SEATING PLANE H C J L MILLIMETERS INCHES IM MIN MAX MIN MAX A B C G 0 BSC 0.0 BSC H J K L SOLERING FOOTPRINT* 0X X X SCALE : mm inches *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLERRM/. AnyLevel is a trademark of Semiconductor Components Industries, LLC. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORERING INFORMATION LITERATURE FULFILLMENT: Literature istribution Center for ON Semiconductor P.O. Box 563, enver, Colorado 02 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative NB4N55S/
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2.5V/3.3V Differential 2x10 Crosspoint Clock Driver with SDI Programmable Output Selects The is a Clock input crosspoint fanout distribution device selecting between one of two input clocks on each of
NTHS2101P. Power MOSFET. 8.0 V, 7.5 A P Channel ChipFET
NTHSP Power MOSFET. V,. A P Channel ChipFET Features Offers an Ultra Low R S(on) Solution in the ChipFET Package Miniature ChipFET Package % Smaller Footprint than TSOP making it an Ideal evice for Applications
MMSZ5221BT1 Series. Zener Voltage Regulators. 500 mw SOD 123 Surface Mount
MMSZ5BT Series Preferred Device Zener Voltage Regulators 5 mw SOD 3 Surface Mount Three complete series of Zener diodes are offered in the convenient, surface mount plastic SOD 3 package. These devices
MUN5311DW1T1G Series.
MUNDWTG Series Preferred Devices Dual Bias Resistor Transistors NPN and PNP Silicon Surface Mount Transistors with Monolithic Bias Resistor Network The Bias Resistor Transistor (BRT) contains a single
NSQA6V8AW5T2 Series Transient Voltage Suppressor
Transient Voltage Suppressor ESD Protection Diode with Low Clamping Voltage This integrated transient voltage suppressor device (TVS) is designed for applications requiring transient overvoltage protection.
MJD44H11 (NPN) MJD45H11 (PNP) Complementary Power Transistors. DPAK For Surface Mount Applications
MJDH (NPN) MJD5H (PNP) Complementary Power Transistors For Surface Mount Applications Designed for general purpose power and switching such as output or driver stages in applications such as switching
UMC2NT1, UMC3NT1, UMC5NT1
UMCNT, UMC3NT, UMC5NT Preferred Devices Dual Common BaseCollector Bias Resistor Transistors NPN and PNP Silicon Surface Mount Transistors with Monolithic Bias Resistor Network The Bias Resistor Transistor
NTTFS5116PLTWG. Power MOSFET 60 V, 20 A, 52 m. Low R DS(on) Fast Switching These Devices are Pb Free and are RoHS Compliant
Power MOSFET 6 V, 2 A, 52 m Features Low R DS(on) Fast Switching These Devices are Pb Free and are RoHS Compliant Applications Load Switches DC Motor Control DC DC Conversion MAXIMUM RATINGS ( unless otherwise
NCN Differential Channel 1:2 Mux/Demux Switch for PCI Express Gen3
4-Differential Channel 1:2 Mux/Demux Switch for PCI Express Gen3 The NCN3411 is a 4 Channel differential SPDT switch designed to route PCI Express Gen3 signals. When used in a PCI Express application,
PZTA92T1. High Voltage Transistor. PNP Silicon SOT 223 PACKAGE PNP SILICON HIGH VOLTAGE TRANSISTOR SURFACE MOUNT
High Voltage Transistor PNP Silicon Features These Devices are Pb Free, Halogen Free/BFR Free and are RoHS Compliant MAXIMUM RATINGS (T C = 25 C unless otherwise noted) Rating Symbol Value Unit Collector-Emitter
NB7L1008M. 2.5V / 3.3V 1:8 CML Fanout. Multi Level Inputs w/ Internal Termination
2.5V / 3.3V 1:8 CML Fanout Multi Level Inputs w/ Internal Termination Description The is a high performance differential 1:8 Clock/Data fanout buffer. The produces eight identical output copies of Clock
NTGD4167C. Power MOSFET Complementary, 30 V, +2.9/ 2.2 A, TSOP 6 Dual
Power MOSFET Complementary, 3 V, +.9/. A, TSOP 6 Dual Features Complementary N Channel and P Channel MOSFET Small Size (3 x 3 mm) Dual TSOP 6 Package Leading Edge Trench Technology for Low On Resistance
MC3488A. Dual EIA 423/EIA 232D Line Driver
Dual EIA423/EIA232D Line Driver The MC34A dual is singleended line driver has been designed to satisfy the requirements of EIA standards EIA423 and EIA232D, as well as CCITT X.26, X.2 and Federal Standard
NTA4001N, NVA4001N. Small Signal MOSFET. 20 V, 238 ma, Single, N Channel, Gate ESD Protection, SC 75
Small Signal MOSFET V, 8 ma, Single, N Channel, Gate ESD Protection, SC 75 Features Low Gate Charge for Fast Switching Small.6 x.6 mm Footprint ESD Protected Gate AEC Q Qualified and PPAP Capable NVA4N
MJD44H11 (NPN) MJD45H11 (PNP)
MJDH (NPN) MJD5H (PNP) Preferred Device Complementary Power Transistors For Surface Mount Applications Designed for general purpose power and switching such as output or driver stages in applications such
Distributed by: www.jameco.com 1-800-831-44 The content and copyrights of the attached material are the property of its owner. Transient Voltage Suppressors Micro Packaged Diodes for ESD Protection The
PCS2P2309/D. 3.3V 1:9 Clock Buffer. Functional Description. Features. Block Diagram
3.3V 1:9 Clock Buffer Features One-Input to Nine-Output Buffer/Driver Buffers all frequencies from DC to 133.33MHz Low power consumption for mobile applications Less than 32mA at 66.6MHz with unloaded
BAT54CLT3G SBAT54CLT1G. Dual Common Cathode Schottky Barrier Diodes 30 VOLT DUAL COMMON CATHODE SCHOTTKY BARRIER DIODES
BAT54CLTG, SBAT54CLTG Dual Common Cathode Schottky Barrier Diodes These Schottky barrier diodes are designed for high speed switching applications, circuit protection, and voltage clamping. Extremely low
NB4L V / 3.3V Differential LVPECL 2x2 Clock Switch and Low Skew Fanout Buffer
2.5V / 3.3V Differential LVPECL 2x2 Clock Switch and Low Skew Fanout Buffer Description The NB4L6254 is a differential 2x2 clock switch and drives precisely aligned clock signals through its LVPECL fanout
MC10EP51, MC100EP V / 5VНECL D Flip Flop with Reset and Differential Clock
3.3V / 5VНEC Flip Flop with Reset and ifferential Clock escription The MC0/00EP5 is a differential clock flip flop with reset. The device is functionally equivalent to the E5 and VE5 devices. The reset
NTTFS5820NLTWG. Power MOSFET. 60 V, 37 A, 11.5 m. Low R DS(on) Low Capacitance Optimized Gate Charge These Devices are Pb Free and are RoHS Compliant
NTTFS582NL Power MOSFET 6 V, 37 A,.5 m Features Low R DS(on) Low Capacitance Optimized Gate Charge These Devices are Pb Free and are RoHS Compliant MAXIMUM RATINGS ( unless otherwise stated) Parameter
NUP4302MR6T1G. Schottky Diode Array for Four Data Line ESD Protection
Schottky Diode Array for Four Data Line ESD Protection The NUP432MR6 is designed to protect high speed data line interface from ESD, EFT and lighting. Features Very Low Forward Voltage Drop Fast Switching
MC100EL29. 5VНECL Dual Differential Data and Clock D Flip Flop With Set and Reset
MCE29 5НEC ual ifferential ata and Clock Flip Flop With Set and Reset escription The MCE29 is a dual master slave flip flop. The device features fully differential ata and Clock inputs as well as outputs.
NTNUS3171PZ. Small Signal MOSFET. 20 V, 200 ma, Single P Channel, 1.0 x 0.6 mm SOT 1123 Package
NTNUS7PZ Small Signal MOSFET V, ma, Single P Channel,. x.6 mm SOT Package Features Single P Channel MOSFET Offers a Low R DS(on) Solution in the Ultra Small. x.6 mm Package. V Gate Voltage Rating Ultra
NLAS7222B, NLAS7222C. High-Speed USB 2.0 (480 Mbps) DPDT Switches
High-Speed USB 2.0 (480 Mbps) DPDT Switches ON Semiconductor s NLAS7222B and NLAS7222C are part of a series of analog switch circuits that are produced using the company s advanced sub micron CMOS technology,
MMBFU310LT1G. JFET Transistor. N Channel. These Devices are Pb Free, Halogen Free/BFR Free and are RoHS Compliant. Features.
MMBFULT1G JFET Transistor N Channel Features These Devices are Pb Free, Halogen Free/BFR Free and are RoHS Compliant 2 SOURCE MAXIMUM RATINGS Rating Symbol Value Unit Drain Source Voltage V DS 25 Vdc Gate
NGB18N40CLB, NGB18N40ACLB. Ignition IGBT 18 Amps, 400 Volts. N Channel D 2 PAK. 18 AMPS, 400 VOLTS V CE(on) 2.0 I C = 10 A, V GE 4.
NGB8N4CLB, NGB8N4ACLB Ignition IGBT 8 Amps, 4 Volts N Channel D PAK This Logic Level Insulated Gate Bipolar Transistor (IGBT) features monolithic circuitry integrating ESD and Over Voltage clamped protection
SN74LS122, SN74LS123. Retriggerable Monostable Multivibrators LOW POWER SCHOTTKY
Retriggerable Monostable Multivibrators These dc triggered multivibrators feature pulse width control by three methods. The basic pulse width is programmed by selection of external resistance and capacitance
NSBC114EDP6T5G Series. Dual Digital Transistors (BRT) NPN Silicon Surface Mount Transistors with Monolithic Bias Resistor Network
Preferred Devices Dual Digital Transistors (BRT) NPN Silicon Surface Mount Transistors with Monolithic Bias Resistor Network This new series of digital transistors is designed to replace a single device
NSVEMD4DXV6T5G. Dual Bias Resistor Transistors. NPN and PNP Silicon Surface Mount Transistors with Monolithic Bias Resistor Network
Dual Bias Resistor Transistors NPN and PNP Silicon Surface Mount Transistors with Monolithic Bias Resistor Network The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias
MC100EPT22/D. MARKING DIAGRAMS* ORDERING INFORMATION SO 8 D SUFFIX CASE 751 KPT22 ALYW TSSOP 8 DT SUFFIX CASE 948R KA22 ALYW
The MC00EPT22 is a dual LVTTL/LVCMOS to differential LVPECL translator. Because LVPECL (Positive ECL) levels are used only +3.3 V and ground are required. The small outline lead package and the single
NGD18N40CLBT4G. Ignition IGBT 18 Amps, 400 Volts N Channel DPAK. 18 AMPS 400 VOLTS V CE(on) 2.0 I C = 10 A, V GE 4.5 V
NGD8NCLB Ignition IGBT 8 Amps, Volts N Channel DPAK This Logic Level Insulated Gate Bipolar Transistor (IGBT) features monolithic circuitry integrating ESD and Over Voltage clamped protection for use in
NTGS3441BT1G. Power MOSFET. -20 V, -3.5 A, Single P-Channel, TSOP-6. Low R DS(on) in TSOP-6 Package 2.5 V Gate Rating This is a Pb-Free Device
Power MOSFET - V, -. A, Single P-Channel, TSOP- Features Low R DS(on) in TSOP- Package. V Gate Rating This is a Pb-Free Device Applications Battery Switch and Load Management Applications in Portable Equipment
NTMS5835NL. Power MOSFET 40 V, 12 A, 10 m
Power MOSFET V, 2 A, m Features Low R DS(on) Low Capacitance Optimized Gate Charge These Devices are Pb Free, Halogen Free/BFR Free and are RoHS Compliant MAXIMUM RATINGS ( unless otherwise stated) Parameter
NTJS4405N, NVJS4405N. Small Signal MOSFET. 25 V, 1.2 A, Single, N Channel, SC 88
NTJSN, NVJSN Small Signal MOSFET V,. A, Single, N Channel, SC 88 Features Advance Planar Technology for Fast Switching, Low R DS(on) Higher Efficiency Extending Battery Life AEC Q Qualified and PPAP Capable
NTMS5838NL. Power MOSFET 40 V, 7.5 A, 20 m
Power MOSFET V, 7.5 A, 2 m Features Low R DS(on) Low Capacitance Optimized Gate Charge These Devices are Pb Free, Halogen Free/BFR Free and are RoHS Compliant MAXIMUM RATINGS ( unless otherwise stated)
MMUN2211LT1 Series. NPN Silicon Surface Mount Transistor with Monolithic Bias Resistor Network
MMUNLT Series Preferred Devices Bias Resistor Transistor NPN Silicon Surface Mount Transistor with Monolithic Bias Resistor Network This new series of digital transistors is designed to replace a single
MMBTA06W, SMMBTA06W, Driver Transistor. NPN Silicon. Moisture Sensitivity Level: 1 ESD Rating: Human Body Model 4 kv ESD Rating: Machine Model 400 V
Driver Transistor NPN Silicon Moisture Sensitivity Level: 1 ESD Rating: Human Body Model 4 kv ESD Rating: Machine Model 400 V Features S Prefix for Automotive and Other Applications Requiring Unique Site
MBD301G, MMBD301LT1G, MMBD301LT3G, SMMBD301LT3G. Silicon Hot-Carrier Diodes. Schottky Barrier Diodes
, MMB0LTG, MMB0LTG, Silicon Hot-Carrier iodes Schottky Barrier iodes These devices are designed primarily for high efficiency UHF and VHF detector applications. They are readily adaptable to many other
MUN5211DW1T1 Series. NPN Silicon Surface Mount Transistors with Monolithic Bias Resistor Network
MUNDWT Series Preferred Devices Dual Bias Resistor Transistors NPN Silicon Surface Mount Transistors with Monolithic Bias Resistor Network The BRT (Bias Resistor Transistor) contains a single transistor
NGB8207AN, NGB8207ABN. Ignition IGBT 20 A, 365 V, N Channel D 2 PAK. 20 AMPS, 365 VOLTS V CE(on) = 1.75 V I C = 10 A, V GE 4.
NGB827AN, NGB827ABN Ignition IGBT 2 A, 365 V, N Channel D 2 PAK This Logic Level Insulated Gate Bipolar Transistor (IGBT) features monolithic circuitry integrating ESD and Overvoltage clamped protection
NTR4502P, NVTR4502P. Power MOSFET. 30 V, 1.95 A, Single, P Channel, SOT 23
NTRP, NVTRP Power MOSFET V,.9 A, Single, P Channel, SOT Features Leading Planar Technology for Low Gate Charge / Fast Switching Low R DS(ON) for Low Conduction Losses SOT Surface Mount for Small Footprint
MC100EL30. 5VНECL Triple D Flip Flop with Set and Reset
MCE30 5VНEC Triple Flip Flop with et and Reset The MCE30 is a triple master slave flip flop with differential outputs. ata enters the master latch when the clock input is OW and transfers to the slave
MUN5211T1 Series. NPN Silicon Surface Mount Transistor with Monolithic Bias Resistor Network NPN SILICON BIAS RESISTOR TRANSISTORS
MUNT Series Preferred Devices Bias Resistor Transistor NPN Silicon Surface Mount Transistor with Monolithic Bias Resistor Network This new series of digital transistors is designed to replace a single
EMF5XV6T5G. Power Management, Dual Transistors. NPN Silicon Surface Mount Transistors with Monolithic Bias Resistor Network
Preferred Devices Power Management, Dual Transistors NPN Silicon Surface Mount Transistors with Monolithic Bias Resistor Network Features Simplifies Circuit Design Reduces Board Space Reduces Component
MMUN2111LT1 Series. Bias Resistor Transistors. PNP Silicon Surface Mount Transistors with Monolithic Bias Resistor Network
MMUNLT Series Preferred Devices Bias Resistor Transistors PNP Silicon Surface Mount Transistors with Monolithic Bias Resistor Network This new series of digital transistors is designed to replace a single