NB6L V / 3.3V Differential 2 X 2 Crosspoint Switch with LVPECL Outputs. Multi-Level Inputs w/ Internal Termination

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1 .5V / 3.3V ifferential X Crosspoint Switch with LVPECL Outputs Multi-Level Inputs w/ Internal Termination escription The NB6L7 is a clock or data high-bandwidth fully differential x Crosspoint Switch with internal source termination and LVPECL output structure, optimized for low skew and minimal jitter. The differential inputs incorporate internal termination resistors and will accept LVPECL, CML, LVS, LVCMOS, or LVTTL logic levels. The SELECT inputs are single-ended and can be driven with LVCMOS/LVTTL. The differential LVPECL outputs provide 800 mv output swings when externally terminated with a resistor to.0 V. The device is offered in a small 3 mm x 3 mm 16-pin QFN package. The NB6L7 is a member of the ECLinPS MAX family of high performance clock and data management products. Features Input Clock Frequency > 3.0GHz Input ata Rate > 3 Gb/s 45 ps Typical Propagation elay 100 ps Typical Rise and Fall Times 0.5 ps maximum RMS Clock Jitter LVPECL, CML or LVS Input Compatible ifferential LVPECL Outputs, 800 mv Amplitude, Typical Operating Range: =.375 V to 3.63 V with GN = 0 V Internal Input Termination Provided Functionally Compatible with Existing.5 V/3.3 V LVEL, LVEP, EP, and SG evices -40 C to +85 C Ambient Operating Temperature These are Pb-Free evices 1 QFN-16 MN SUFFIX CASE 485G MARKING IAGRAM* A = Assembly Location L = Wafer Lot Y = Year W = Work Week = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AN800/. ORERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet NB6L 7 ALYW Semiconductor Components Industries, LLC, 008 April, Rev. 4 1 Publication Order Number: NB6L7/

2 VT VT1 SEL0 SEL k + 75 k GN Q0 Q0 + Q1 Q1 Figure 1. Logic/Block iagram

3 GN Q0 Q Exposed Pad (EP) Table 1. INPUT/OUTPUT SELECT TRUTH TABLE SEL0* SEL1* Q0 Q1 SEL0 1 1 L L 0 0 H L VT0 3 4 NB6L Q1 Q1 GN L H 0 1 H H 1 1 *efaults HIGH when left open VT1 1 1 SEL1 Figure. Pin Configuration (Top View) Table. PIN ESCRIPTION Pin Name I/O escription 1 SEL0 LVTTL, LVCMOS Input 0 LVPECL, CML, LVS, LVTTL, LVCMOS, Input 3 0 LVPECL, CML, LVS, LVTTL, LVCMOS, Input Select Logic Input control that selects 0 or 1 to output Q0. See Table 1, Select Input Function Table. Pin defaults HIGH when left open Noninverted ifferential Input. Note 1. Inverted ifferential Input. Note 1. 4 VT0 - Internal Termination Pin. Note 1. 5 VT1 - Internal termination pin. Note LVPECL, CML, LVS, LVTTL, LVCMOS, Input 7 1 LVPECL, CML, LVS, LVTTL, LVCMOS, Input 8 SEL1 LVTTL,LVCMOS Input Noninverted ifferential Input. Note 1. Inverted ifferential Input. Note 1. Select Logic Input control that selects 0 or 1 to output Q1. See Table 1, Select Input Function Table. Pin defaults HIGH when left open 9 GN - Negative Supply Voltage 10 Q1 LVPECL Output Inverted ifferential Output. Typically Terminated with Resistor to -.0 V. 11 Q1 LVPECL Output Noninverted ifferential Output. Typically Terminated with Resistor to -.0 V. 1 - Positive Supply Voltage 13 - Positive Supply Voltage 14 Q0 LVPECL Output Inverted ifferential Reset Input. Typically Terminated with Resistor to -.0 V. 15 Q0 LVPECL Output Noninverted ifferential Reset Input. Typically Terminated with Resistor to -.0 V. 16 GN - Negative Supply Voltage - EP - The Exposed Pad (EP) on the QFN-16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat-sinking conduit. The pad is not electrically connected to the die, but is recommended to be electrically and thermally connected to GN on the PC board. 1. In the differential configuration when the input termination pin (VTn, VTn) are connected to a common termination voltage or left open, and if no signal is applied on n/n input, then the device will be susceptible to self-oscillation.. All and GN pins must be externally connected to a power supply for proper operation. 3

4 Table 3. ATTRIBUTES ES Protection Characteristics Human Body Model Machine Model Value > kv > 00 V Moisture Sensitivity 16-QFN Level 1 Flammability Rating Oxygen Index: 8 to 34 UL in Transistor Count Meets or exceeds JEEC Spec EIA/JES78 IC Latchup Test For additional information, see Application Note AN8003/. Table 4. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition Rating Unit Positive Power Supply GN = 0 V 4.0 V V IO Positive Input/Output Voltage GN = 0 V -0.5 V IO V V INPP ifferential Input Voltage - - GN V I IN Input Current Through R T ( Resistor) Static Surge ma ma I OUT Output Current (LVPECL Output) Continuous Surge T A Operating Temperature Range QFN to +85 C T stg Storage Temperature Range -65 to +150 C JA Thermal Resistance (Junction-to-Ambient) (Note 3) 0 lfpm 500 lfpm QFN-16 QFN-16 JC Thermal Resistance (Junction-to-Case) (Note 3) QFN-16 4 C/W T sol Wave Solder Pb-Free 65 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 3. JEEC standard multilayer board - SP ( signal, power) with 8 filled thermal vias under exposed pad ma ma C/W C/W 4

5 Table 5. C CHARACTERISTICS, Multi-Level Inputs =.375 V to 3.63 V, GN = 0 V, TA = -40 C to +85 C Symbol Characteristic Min Typ Max Unit POWER SUPPLY CURRENT I CC Power Supply Current (Inputs and Outputs Open) ma LVPECL OUTPUTS (Notes 4 and 5) V OH Output HIGH Voltage mv = 3.3 V =.5 V V OL Output LOW Voltage = 3.3 V =.5 V IFFERENTIAL INPUT RIVEN SINGLE-ENE (see Figures 4 and 5) (Note 6) V th Input Threshold Reference Voltage Range (Note 7) mv V IH Single-ended Input HIGH Voltage V th mv V IL Single-ended Input LOW Voltage GN V th mv V ISE Single-ended Input Voltage Amplitude (V IH - V IL ) GN mv IFFERENTIAL INPUTS RIVEN IFFERENTIALLY (see Figures 7 and 9) V IH ifferential Input HIGH Voltage 1050 mv V IL ifferential Input LOW Voltage GN mv V I ifferential Input Voltage (n, n) (V IH - V IL ) GN mv V CMR Input Common Mode Range (ifferential Configuration) (Note 9) mv I IH Input HIGH Current n/n, (VTn/VTn Open) A I IL Input LOW Current n/n, (VTn/VTn Open) A SINGLE-ENE LVCMOS/LVTTL CONTROL INPUTS V IH Single-ended Input HIGH Voltage 000 mv V IL Single-ended Input LOW Voltage GN 800 mv I IH Input HIGH Current A I IL Input LOW Current A TERMINATION RESISTORS R TIN Internal Input Termination Resistor NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. LVPECL outputs loaded with to -.0 V for proper operation. 5. Input and output parameters vary 1:1 with. 6. V th, V IH, V IL,, and V ISE parameters must be complied with simultaneously. 7. V th is applied to the complementary input when operating in single-ended mode. 8. V IH, V IL, V I and V CMR parameters must be complied with simultaneously. 9. V CMR minimum varies 1:1 with GN, V CMR max varies 1:1 with. The V CMR range is referenced to the most positive side of the differential input signal. mv 5

6 Table 6. AC CHARACTERISTICS =.375 V to 3.63 V, V EE = 0 V, or = 0 V, V EE = V to V, T A = -40 C to +85 C; (Note 10) Symbol Characteristic Min Typ Max Unit V OUTPP Output Voltage Amplitude (@ V INPPmin ) f in 1.5 GHz (Note 14) (See Figure 16) f in.5 GHz f in 3.0 GHz t PLH, Propagation elay (@0.5GHz) n to Qn t PHL SELn to Qn t SKEW uty Cycle Skew (Note 11) Within evice Skew evice to evice Skew (Note 1) t C Output Clock uty Cycle f in 3.0 GHz (Reference uty Cycle = 50%) t JITTER RMS Random Clock Jitter (Note 13) f in =.5 GHz f in = 3.0 GHz ata ependent Jitter f ATA =.5 Gb/s f ATA = 3.0 Gb/s V INPP Input Voltage Swing/Sensitivity (ifferential Configuration) (Note 14) mv ps % GN mv ps ps t r,t f Output Rise/Fall 0.5 GHz (0% - 80%) Q, Q ps NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10.Measured by forcing V INPP (minimum) from a 50% duty cycle clock source. All loading with an external R L = to.0 V. Input edge rates 40 ps (0% - 80%). 11. uty cycle skew is measured between differential outputs using the deviations of the sum of T pw - and T pw 0.5 GHz. 1. evice to device skew is measured between outputs under identical 0.5 GHz. 13. Additive RMS jitter with 50% duty cycle clock signal. 14. Input and output voltage swing is a single-ended measurement operating in differential mode. 6

7 VT R C R C I VT Figure 3. Input Structure V IH V th V IL V thmax V th V IHmax V ILmax V IH V th V IL V thmin V IHmin V th Figure 4. ifferential Input riven Single-Ended GN Figure 5. V th iagram V ILmin V I = V IH() - V IL() V IH V IL Figure 6. ifferential Inputs riven ifferentially Figure 7. ifferential Inputs riven ifferentially V IH(MAX) V IL V INPP = V IH () - V IL () V CMR V IH V I = V IH - V IL Q V IL Q V OUTPP = V OH (Q) - V OL (Q) V IH(MIN) t P GN V IL(MIN) t P Figure 8. V CMR iagram Figure 9. AC Reference Measurement 7

8 Z O = NB6L7 Z O = NB6L7 LVPECL river VT = - V Z O = LVS river V T = Open Z O = GN GN GN GN Figure 10. LVPECL Interface Figure 11. LVS Interface Z O = NB6L7 CML river V T = Z O = GN GN Figure 1. Standard Load CML Interface Z O = NB6L7 Z O = NB6L7 ifferential river VT = V REFAC * Z O = Single-Ended river VT = V REFAC * (Open) GN Figure 13. Capacitor-Coupled ifferential Interface (VT Connected to V REFAC ) GN GN Figure 14. Capacitor-Coupled Single-Ended Interface (VT Connected to V REFAC ) GN *V REFAC bypassed to ground with a 0.01 F capacitor 8

9 river evice Q Q Z o = Z o = Receiver evice V TT V TT = -.0 V Figure 15. Typical Termination for Output river and evice Evaluation (See Application Note AN800/ - Termination of ECL Logic evices.) OUTPUT VOLTAGE AMPLITUE (mv) OUTPUT FREQUENCY (GHz) Figure 16. Output Voltage Amplitude (V OUTPP ) versus Output Frequency at Ambient Temperature (Typical) Total Jitter = 5 ps evice Jitter = 1 ps Input Jitter = 13 ps Figure 17. Typical Output Wave Form - ata Signal PRBS 3-1 Room Temperature, 400 mv Input Amplitude, =.5 V,.488 Gb/s (X-scale = 80 ps/iv; y-scale = 100 mv/iv) 9

10 Total Jitter = 8 ps evice Jitter = 15 ps Input Jitter = 13 ps Figure 18. Typical Output Wave Form - ata Signal PRBS 3-1 Room Temperature, 75 mv Input Amplitude, 3 Gb/s (X-scale = 80 ps/iv; y-scale = 100 mv/iv) ORERING INFORMATION NB6L7MNG NB6L7MNRG evice Package Shipping QFN-16 (Pb-free) QFN-16 (Pb-free) 13 Units / Rail 3000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BR8011/. 10

11 PACKAGE IMENSIONS 16 X PIN 1 LOCATION 16X L NOTE C 0.10 C 0.08 C 16X K 0.15 C 4 ÇÇ 1 TOP VIEW SIE VIEW e 5 8 (A3) 9 A B E A1 e 1 E A C EXPOSE PA 16 PIN QFN MN SUFFIX CASE 485G-01 ISSUE C SEATING PLANE NOTES: 1. IMENSIONING AN TOLERANCING PER ASME Y14.5M, CONTROLLING IMENSION: MILLIMETERS. 3. IMENSION b APPLIES TO PLATE TERMINAL AN IS MEASURE BETWEEN 0.5 AN 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSE PA AS WELL AS THE TERMINALS. 5. L max CONITION CAN NOT VIOLATE 0. MM MINIMUM SPACING BETWEEN LEA TIP AN FLAG MILLIMETERS IM MIN MAX A A A3 0.0 REF b BSC E 3.00 BSC E e 0.50 BSC K 0.18 TYP L SOLERING FOOTPRINT* EXPOSE PA 0.10 C 0.05 C 16X b A B NOTE BOTTOM VIEW SCALE 10: mm inches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLERRM/. ECLinPS MAX is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORERING INFORMATION LITERATURE FULFILLMENT: Literature istribution Center for ON Semiconductor P.O. Box 5163, enver, Colorado 8017 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center -9-1 Kamimeguro, Meguro-ku, Tokyo, Japan Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative. NB6L7/