NB3V8312C. Ultra-Low Jitter, Low Skew 1:12 LVCMOS/LVTTL Fanout Buffer

Size: px

Start display at page:

Download "NB3V8312C. Ultra-Low Jitter, Low Skew 1:12 LVCMOS/LVTTL Fanout Buffer"

Angel Anderson
5 years ago
Views:

Ultra-Low Jitter, Low Skew : LCMOS/LTTL Fanout Buffer The is a high performance, low skew LCMOS fanout buffer which can distribute ultra low jitter clocks from an LCMOS/LTTL input up to 50 MHz.

1 Ultra-Low Jitter, Low Skew : LCMOS/LTTL Fanout Buffer The is a high performance, low skew LCMOS fanout buffer which can distribute ultra low jitter clocks from an LCMOS/LTTL input up to 50 MHz. The LCMOS output pins drive 50 series or parallel terminated transmission lines. The outputs can also be disabled to a high impedance (tri stated) via the OE input, or enabled when High. The provides an enable input, _EN pin, which synchronously enables or disables the clock outputs while in the LOW state. Since this input is internally synchronized to the input clock, changing only when the input is LOW, potential output glitching or runt pulse generation is eliminated. Separate core and output supplies allow the output buffers to operate at the same supply as the ( = ) or from a lower supply voltage. Compared to single supply operation, dual supply operation enables lower power consumption and output level compatibility. The core supply voltage can be set to 3.3,.5 or.8, while the output supply voltage can be set to 3.3,.5, or.8, with the constraint that. This buffer is ideally suited for various networking, telecom, server and storage area networking, RRU LO reference distribution, medical and test equipment applications. Features Power Supply Modes: (Core) / (Outputs) 3.3 / / /.8.5 /.5.5 /.8.8 /.8 50 MHz Maximum Clock Frequency Accepts LCMOS, LTTL Clock Inputs LCMOS Compatible Control Inputs LCMOS Clock Outputs Synchronous Clock Enable Output Enable to High Z State Control 50 ps Max. Skew Between Outputs Temp. Range 40 C to +85 C 3 pin LQFP and QFN Packages These are Pb Free Devices Applications Networking Telecom Storage Area Network End Products Servers Routers Switches FA SUFFIX CASE 873A _EN OE R PU R PD R PU D Q Figure. Simplified Logic Diagram ORDERING AND MARKING INFORMATION See detailed ordering and shipping information on page 9 of this data sheet. 3 QFN3 MN SUFFIX CASE 488AM Q0 Q Q Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q0 Q Semiconductor Components Industries, LLC, 03 August, 03 Rev. 0 Publication Order Number: /D

2 Q Q0 Q9 Q8 Q0 Q Q Q Q4 Q0 3 Q Q 8 7 Q3 6 5 Exposed Pad (EP) _EN OE Q5 Q6 Q7 _EN OE Q4 3 Q5 0 Q6 9 8 Q Q Q0 Q9 Q8 Figure. Pinout Configuration (Top iew) Figure 3. QFN3 Pinout Configuration (Top iew) Table. PIN DESCRIPTION Pin Name I/O, 5, 8,, 6, 7,, 5, 9 Open Default Description Power Ground, Negative Power Supply, 7 DD Power Positive Supply for Core and Inputs 3 _EN Input High Synchronous Clock Enable Input. When High, outputs are enabled. When Low, outputs are disabled Low. Internal Pullup Resistor. 4 Input Low Single ended Clock input; LCMOS/LTTL. Internal Pull down Resistor. 6 OE Input High Output Enable. Internal Pullup Resistor. 9,, 3, 5, 8, 0,, 4, 6, 8, 30, 3 Q, Q0, Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q, Q, Q0 Output Single ended LCMOS/LTTL outputs 0, 4, 9, 3, 7, 3 DDO Power Positive Supply for Outputs EP The Exposed Pad (EP) on the package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat sinking conduit. The pad is connected to the die and must only be connected electrically to on the PC board.. All DD, DDO and pins must be externally connected to a power supply to guarantee proper operation. Bypass each supply pin with 0.0 F to.

3 _EN Q Figure 4. _EN Control Timing Diagram Table. OE, _EN FUNCTION TABLES Inputs Outputs OE _EN (Note ) Q[0:] 0 X X Hi Z 0 X Low 0 Low High. The _EN control input synchronously enables or disables the outputs as shown in Figure 4. This control latches on the falling edge of the selected input. When _EN is LOW, the outputs are disabled in a LOW state. When _EN is HIGH, the outputs are enabled as shown. _EN to Set up and Hold times must be satisfied. 3

4 Table 3. ATTRIBUTES (Note 3) Characteristics Internal Input Pullup (R PU ) and Pulldown (R PD ) Resistor Input Capacitance, C IN Power Dissipation Capacitance, C PD (per Output) R OUT ESD Protection Human Body Model Machine Model alue 50 k 4 pf 0 pf 8 >.5 k > 00 Moisture Sensitivity, Indefinite Time Out of Drypack (Note 3) Level Flammability Rating Oxygen Index Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, see Application Note AND8003/D. UL 94 code 0 A /8 8 to Devices Table 4. MAXIMUM RATINGS (Note 4) Symbol Parameter Condition Rating Unit / Positive Power Supply = I Input oltage 0.5 I T stg Storage Temperature Range 65 to +50 C JA Thermal Resistance (Junction to Ambient) (Note 5) 0 lfpm 500 lfpm 80 C/W C/W JC Thermal Resistance (Junction to Case) (Note 5) Standard Board 7 C/W JA Thermal Resistance (Junction to Ambient) (Note 5) 0 lfpm 500 lfpm QFN 3 QFN C/W JC Thermal Resistance (Junction to Case) (Note 5) Standard Board QFN 3 C/W Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 4. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously. If stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected. 5. JEDEC standard multilayer board SP ( signal, power). 4

5 Table 5. LCMOS/LTTL DC CHARACTERISTICS (T A = 40 C to +85 C) Symbol Characteristics Conditions Min Typ Max Unit = IH Input High oltage = = x IL Input Low oltage = = = x I IH I IL Input High Current Input Low Current 50 OE, _EN = IN = or.65 or.0 5 OE, _EN OH Output High oltage (Note 6) = or.65 or.0, IN = = 3.3 ±5%.6 =.5 ±5%.8 =.5 ±5%; I OH = ma.0 =.8 ± A A =.8 ±0. ; I OH = 00 A 0. OL Output Low oltage (Note 6) = 3. 3 ±5% 0.5 =.5 ±5% 0. =.5 ±5%; I OL = ma 0.4 =.8 ± =.8 ±0. ; I OL = 00 A 0. NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 6. Outputs terminated 50 to / unless otherwise specified. See Figure 7. Table 6. POWER SUPPLY DC CHARACTERISTICS, (T A = 40 C to +85 C) (Core) (Outputs) Min Typ Max Unit 3.3 ±5% 3.3 ±5% 0 ma 3.3 ±5%.5 ±5% 0 ma 3.3 ±5%.8 ± 0. 0 ma.5 ±5%.5 ±5% 0 ma.5 ±5%.8 ± 0. 0 ma.8 ± 0..8 ± 0. 0 ma 5

6 Table 7. AC CHARACTERISTICS (T A = 40 C to +85 C) (Note 7) Symbol Characteristic Min Typ Max Unit f MAX Maximum Operating Frequency / 3.3 ±5% / 3.3 ±5% 3.3 ±5% /.5 ±5% 3.3 ±5% /.8 ± 0..5 ±5% /.5 ±5%.5 ±5% /.8 ± 0..8 ± 0. /.8 ± MHz t plh Propagation Delay, Low to High; (Note 8) / 3.3 ±5% / 3.3 ±5% 3.3 ±5% /.5 ±5% 3.3 ±5% /.8 ± 0..5 ±5% /.5 ±5%.5 ±5% /.8 ± 0..8 ± 0. /.8 ± ns t jit Additive Phase Jitter, RMS; / f C = 00 MHz 3.3 ±5% / 3.3 ±5% Integration Range: khz 0 MHz 3.3 ±5% /.5 ±5% See Figure ±5% /.8 ± 0..5 ±5% /.5 ±5%.5 ±5% /.8 ± 0..8 ± 0. /.8 ± fs t sk(o) Output to output skew; (Note 9); Figure 6 / 3.3 ±5% / 3.3 ±5% 3.3 ±5% /.5 ±5% 3.3 ±5% /.8 ± 0..5 ±5% /.5 ±5%.5 ±5% /.8 ± 0..8 ± 0. /.8 ± ps t sk(pp) Part to Part Skew; (Note 0) / 3.3 ±5% / 3.3 ±5% 3.3 ±5% /.5 ±5% 3.3 ±5% /.8 ± 0..5 ±5% /.5 ±5%.5 ±5% /.8 ± 0..8 ± 0. /.8 ± ps t r /t f Output rise and fall times / 3.3 ±5% / 3.3 ±5% 3.3 ±5% /.5 ±5% 3.3 ±5% /.8 ± 0..5 ±5% /.5 ±5%.5 ±5% /.8 ± 0..8 ± 0. /.8 ± ps ODC Output Duty Cycle (Note ) / f 00 MHz, 3.3 ±5% / 3.3 ±5% f 50 MHz, 3.3 ±5% /.5 ±5% f 00 MHz, 3.3 ±5% /.8 ± 0. f 50 MHz,.5 ±5% /.5 ±5% f 00 MHz,.5 ±5% /.8 ± 0. f 00 MHz,.8 ± 0. /.8 ± 0. % All parameters measured at f MAX unless noted otherwise. 7. Outputs loaded with 50 to /; see Figure 7. CLOCK input with 50% duty cycle; minimum input amplitude =. at = 3.3,.0 at =.5, / at = Measured from the / of the input to / of the output. 9. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at /. 0. Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using the same type of input on each device, the output is measured at /.. Clock input with 50% duty cycles, rail to rail amplitude and t r /t f = 500 ps. 6

Additive Phase Jitter @ 00 MHz DD = DDO = 3.3 khz to 0 MHz = 9.8 fs (typical) Filter = khz 0 MHz Source RMS Jitter = 00.53 fs Output RMS Jitter = 0.

7 Additive Phase 00 MHz DD = DDO = 3.3 khz to 0 MHz = 9.8 fs (typical) Filter = khz 0 MHz Source RMS Jitter = fs Output RMS Jitter = 0.73 fs RMS addititive jitter RMS phase jitter of output RMS phase jitter of input fs fs Output (DUT + Source) Input Source Figure 5. Typical Phase Noise Plot at f carrier = 00 MHz at an Operating oltage of 3.3, Room Temperature The above phase noise data was captured using Agilent E505A/B. The data displays the input phase noise and output phase noise used to calculate the additive phase jitter at a specified integration range. The RMS Phase Jitter contributed by the device (integrated between khz and 0 MHz) is 9.8 fs. The additive phase jitter performance of the fanout buffer is highly dependent on the phase noise of the input source. To obtain the most accurate additive phase noise measurement, it is vital that the source phase noise be notably lower than that of the DUT. If the phase noise of the source is greater than the device under test output, the source noise will dominate the additive phase jitter calculation and lead to an artificially low result for the additive phase noise measurement within the integration range. The Figure above is a good example of the source generator phase noise having a significantly higher floor such that the DUT output results in an additive phase jitter of 9.8 fs. RMS addititive jitter RMS phase jitter of output RMS phase jitter of input fs fs 7

8 PP = IH IL IHCMR LCMOS_ Qx t LH t PHL Qx t PW Figure 6. AC Reference Measurement t P t SKEWDC % tpw t P 00 Q x Z O = 50 IN Scope 50 = 0 = Ground Figure 7. Typical Device Evaluation and Termination Setup See Table 8 Table 8. TEST SUPPLY SETUP. SUPPLY MAY BE CENTERED ON 0.0 (SCOPE ) TO PERMIT DIRECT CONNECTION INTO 50 TO SCOPE MODULE. SUPPLY TRACKS DUT PIN Spec Condition: Test Setup DDO Test Setup Pin Test Setup = 3.3 ±5%, = 3.3 ±5% +.65 ±5% +.65 ±5%.65 ±5% = 3.3 ±5%, =.5 ±5% +.05 ±5% +.5 ±5%.5 ±5% = 3.3 ±5%, =.8 ±5% +.4 ±5% +0.9 ± ±0. =.5 ±5%, O =.5 ±5% +.5 ±5% +.5 ±5%.5 ±5% =.5 ±5%, =.8 ± ±5% +0.9 ± ±0. =.8 ±0., =.8 ± ± ± ±0. 8

9 MARKING DIAGRAMS* NB3 83C AWLYYWWG 3 NB3 83C AWLYYWWG QFN3 A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb Free Package (*Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND800/D. ORDERING INFORMATION FAG Device Package Shipping (Pb Free) 50 Units / Tray FARG MNG (Pb Free) QFN3 (Pb Free) 000 / Tape & Reel 74 Units / Rail MNR4G QFN3 (Pb Free) 000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD80/D. 9

10 PACKAGE DIMENSIONS 3 LEAD LQFP CASE 873A 0 ISSUE C T B B 9 8 A 3 9 S A 5 DETAIL Y Z S 4X 0.0 (0.008) AB T-U Z 7 4X U P 0.0 (0.008) AC T-U Z DETAIL Y 8X M AE AE T, U, Z R BASE METAL N ÉÉ ÉÉ F J D 0.0 (0.008) M AC T-U Z SECTION AE AE AB G DETAIL AD C E SEATING PLANE AC 0.0 (0.004) AC NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, 98.. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE AB IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS T, U, AND Z TO BE DETERMINED AT DATUM PLANE AB. 5. DIMENSIONS S AND TO BE DETERMINED AT SEATING PLANE AC. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.50 (0.00) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE AB. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.50 (0.00). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY ARY FROM DEPICTION. MILLIMETERS INCHES DIM MIN MAX MIN MAX A BSC 0.76 BSC A BSC 0.38 BSC B BSC 0.76 BSC B BSC 0.38 BSC C D E F G BSC 0.03 BSC H J K M REF REF N P BSC 0.06 BSC Q 5 5 R S BSC BSC S BSC 0.77 BSC BSC BSC BSC 0.77 BSC W 0.00 REF REF X.000 REF REF H W DETAIL AD X K Q GAUGE PLANE 0.50 (0.00) 0

11 PACKAGE DIMENSIONS QFN3 5x5, 0.5P CASE 488AM ISSUE O PIN ONE LOCATION ÉÉ D E A B NOTES:. DIMENSIONS AND TOLERANCING PER ASME Y4.5M, CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.5 AND 0.30 MM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. X 3 X X 0.5 C 0.0 C 0.08 C 0.5 C TOP IEW SIDE IEW (A3) A A C SEATING PLANE MILLIMETERS DIM MIN NOM MAX A A A REF b D 5.00 BSC D E 5.00 BSC E e BSC K 0.00 L SOLDERING FOOTPRINT* L 3 X 8 D EXPOSED PAD K 3 X E 3 X X b 0.0 C A B 0.05 C 5 BOTTOM IEW 4 e 3 X X 0.50 PITCH *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 563, Denver, Colorado 807 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative /D

MC100EP V 2:1:9 Differential HSTL/PECL/LVDS to HSTL Clock Driver with LVTTL Clock Select and Enable

MC100EP V 2:1:9 Differential HSTL/PECL/LVDS to HSTL Clock Driver with LVTTL Clock Select and Enable 3.3 2:: Differential HSTL/PECL/LDS to HSTL Clock Driver with LTTL Clock Select and Enable Description The MC00EP80 is a low skew 2:: differential clock driver, designed with clock distribution in mind,