MC100EPT V LVTTL/LVCMOS to LVPECL Translator Description The MC100EPT622 is a 10- Bit LVTTL/LVCMOS to LVPECL translator. Because LVPECL (Positiv
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1 3.3V VTT/VCMOS to VPEC Translator Description The is a 0- Bit VTT/VCMOS to VPEC translator. Because VPEC (Positive EC) levels are used only +3.3 V and ground are required. The device has an OR- ed enable input which can accept either VPEC (ENPEC) or TT/VCMOS inputs (ENTT). If the inputs are left open, they will default to the enable state. The device design has been optimized for low channel- to- channel skew MARKING DIAGRAMS* Features 450 ps Typical Propagation Delay Maximum Frequency >.5 Gz Typical PEC Mode Operating Range: V CC = 3.0 V to 3.8 V with V EE = 0 V PNP VTT Inputs for Minimal oading Q Output Will Default IG with Inputs Open The 00 Series Contains Temperature Compensation. Pb-Free Packages are Available* QFP-32 FA SUFFI CASE 873A 32 MC00 EPT622 AWYYWWG 32 MC00 EPT622 AWYYWW QFN32 MN SUFFI CASE 488AM A = Assembly ocation W = Wafer ot YY = Year WW = Work Week G or = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND2/D. Table. TRUT TABE ENPEC ENTT D Q ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SODERRM/D. m/on/ Semiconductor Components Industries, C, 7 Publication Order Number: August, 7 - Rev. 5 /D
2 D4 D3 D2 V EE D D0 ENPEC ENTT D0 Q D5 D6 D7 D8 D9 ENTT ENPEC V EE Q0 Q Q2 Q3 Q4 VCMOS/TT D D2 D3 D4 Q Q2 Q3 Q4 VPEC D5 Q5 Q9 Q8 Q7 V CC Q6 Q5 Warning: All V CC,, and V EE pins must be externally connected to Power Supply to guarantee proper operation. Figure. 32-ead QFP Pinout (Top View) Exposed Pad D4 D3 D2 V EE D D0 (EP) D6 D7 Q6 Q7 D5 D6 D7 D D8 Q Q0 D9 Q9 22 Q 2 Q2 Figure 2. ogic Symbol D ENTT 6 9 Q3 ENPEC 7 8 Q4 V EE Q9 Q8 Q7 V CC Q6 Q5 Figure ead QFN Pinout (Top View) Table. PIN DESCRIPTION Pin Function D0:9 Data Input (TT) Q0:9 Data Outputs (PEC) ENTT Enable Control (TT) ENPEC Enable Control (PEC) V CC, Positive Supply V EE Ground EP The exposed pad (EP) on the QFN-32 package bottom is thermally connected to the die for improved heat transfer out of the package. Te exposed pad must be attached to a heat-sinking conduit. The pad is electrically connected to V EE. m/on/ 2
3 Table 2. ATTRIBUTES Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection uman Body Model Machine Model Charged Device Model Value N/A N/A > 2 kv > 50 V > 2 kv Moisture Sensitivity, Indefinite Time Out of Drypack Pb Pkg Pb-Free Pkg QFP-32 QFN-32 evel 2 N/A evel 2 evel Flammability Rating Oxygen Index: 28 to 34 U in Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC atchup Test 596 Devices Table 3. MAIMUM RATINGS Symbol Parameter Condition Condition 2 Rating Unit V CC Power Supply V EE = 0 V 5 V V I Input Voltage V EE = 0 V V I V CC 5 to 0 V I out Output Current Continuous Surge T A Operating Temperature Range -40 to +85 C T stg Storage Temperature Range -65 to +50 C JA Thermal Resistance (Junction-to-Ambient) 0 lfpm 32 QFP 80 C/W lfpm 32 QFP 55 C/W JC Thermal Resistance (Junction-to-Case) Standard Board 32 QFP 2 to 7 C/W JA Thermal Resistance (Junction-to-Ambient) 0 lfpm QFN-32 3 C/W lfpm QFN C/W JC Thermal Resistance (Junction-to-Case) 2S2P QFN-32 2 C/W T sol Wave Solder Pb Pb-Free Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability ma ma C Table 4. TT INPUT DC CARACTERISTICS V CC = 3.3 V, GND= 0.0 V, T A = -40 C to 85 C Symbol Characteristic Condition Min Typ Max Unit I I Input IG Current V IN = 2.7 V 25 A I I Input IG Current MA V IN = V CC 00 A I I Input OW Current V IN = 0.5 V -0.6 ma V IK Input Clamp Voltage I IN = -8 ma V V I Input IG Voltage 2.0 V V I Input OW Voltage 0.8 V NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. m/on/ 3
4 Table 5. PEC INPUT DC CARACTERISTICS V CC = 3.3 V, GND= 0.0 V, T A = -40 C to 85 C Symbol Characteristic Condition Min Typ Max Unit I I Input IG Current V IN = 2420 mv 50 A I I Input OW Current V IN = 490 mv A V I Input IG Voltage mv V I Input OW Voltage mv NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. Table 6. PEC OUTPUT DC CARACTERISTICS V CC = 3.3 V, GND = 0.0 V (Note ) Symbol Characteristic -40 C 25 C 85 C Min Typ Max Min Typ Max Min Typ Max I EE Power Supply Current ma V O Input igh Voltage (Note 2) mv Unit V O Input ow Current (Note 2) mv NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.. Input and output parameters vary : with V CC. 2. All loading with 50 to V CC -2.0 V. Table 7. AC CARACTERISTICS V CC = 3.0 V to 3.8 V (Note 3) -40 C 25 C 85 C Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit f max Maximum Frequency (See Figure 4) Gz t P, Propagation Delay to Output (Figure 5, Note 4) t P D to Q ENPEC to Q ENTT to Q t JITTER Random Clock Jitter (RMS) (See Figure 4) ps ps t r / t f Output Rise/Fall Times (20% - 80%) ps T SKEW Duty Cycle Skew (Note 5) D to Q Channel 0-7 Channel 8-9 ENPEC to Q ENTT to Q ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. Measured using a 2.4 V source, 50% duty cycle clock source. All loading with 50 to V CC -2.0 V V to 50% point of the output. 5. Duty cycle skew t P - t P on the specific path. m/on/ 4
5 OUTPUT AMPITUDE (mv) V CC = 3.3 V T A = 25 C V O (mv) V O (mv) RMS Jitter (ps) t P, t P (ps) FREQUENCY (Gz) Figure 4. Average Output Amplitude/Jitter (3.3 V, 25 C) t P t P ÉÉ RMS JITTER (ps) CANNE Figure 5. Average Propagation Delay (3.3 V, 25 C) Driver Device Q Q Z o = 50 Z o = 50 D D Receiver Device V TT V TT = V CC V Figure 6. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of EC ogic Devices.) m/on/ 5
6 ORDERING INFORMATION Device Package Shipping FA QFP Units / Tray FAG QFP-32 (Pb-Free) 250 Units / Tray FAR2 QFP-32 0 / Tape & Reel FAR2G MNG QFP-32 (Pb-Free) QFN32 (Pb-Free) 0 / Tape & Reel 74 Units / Rail MNR4G QFN32 (Pb-Free) 000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD80/D. Resource Reference of Application Notes AN405/D - EC Clock Distribution Techniques AN406/D - Designing with PEC (EC at +5.0 V) AN503/D - ECinPS I/O SPiCE Modeling Kit AN504/D - Metastability and the ECinPS Family AN568/D - Interfacing Between VDS and EC AN672/D - The EC Translator Guide AND/D - Odd Number Counters Design AND2/D - Marking and Date Codes AND8020/D - Termination of EC ogic Devices AND8066/D - Interfacing with ECinPS AND8090/D - AC Characteristics of EC Devices m/on/ 6
7 PACKAGE DIMENSIONS 32 EAD QFP CASE 873A-02 ISSUE C A 32 A (0.008) AB T-U Z -U-, -Z- -T-, -T- -U- P AE B 9 SEATING PANE B -AC- -AB- 8 9 S S DETAI Y -Z- 7 4 V V 0.20 (0.008) AC T-U Z 8 M DETAI Y AE R BASE META N ÉÉ ÉÉ F ÉÉ DETAI AD G SECTION AE-AE C E 0.0 (0.004) AC W K Q DETAI AD GAUGE PANE (0.00) J D 0.20 (0.008) M AC T-U Z m/on/ 7
8 PACKAGE DIMENSIONS QFN32 5*5* 0.5 P CASE 488AM-0 ISSUE O PIN ONE OCATION 0.5 C 0.0 C 0.08 C 0.5 C ÉÉ D TOP VIEW SIDE VIEW (A3) A E A B A C SEATING PANE NOTES:. DIMENSIONS AND TOERANCING PER ASME Y4.5M, CONTROING DIMENSION: MIIMETERS. 3. DIMENSION b APPIES TO PATED TERMINA AND IS MEASURED BETWEEN 0.25 AND 0.30 MM TERMINA 4. COPANARITY APPIES TO TE EPOSED PAD AS WE AS TE TERMINAS. MIIMETERS DIM MIN NOM MA A A A3 0. REF b D 5.00 BSC D E 5.00 BSC E e 0. BSC K EPOSED PAD 32 D2 K SODERING FOOTPRINT* E b e 0.0 C A B 0.05 C BOTTOM VIEW PITC *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SODERRM/D. ECinPS is a trademark of Semiconductor Components INdustries, C (SCIC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, C (SCIC). SCIC reserves the right to make changes without further notice to any products herein. SCIC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCIC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCIC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer's technical experts. SCIC does not convey any license under its patent rights nor the rights of others. SCIC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCIC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCIC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCIC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCIC was negligent regarding the design or manufacture of the part. SCIC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBICATION ORDERING INFORMATION ITERATURE FUFIMENT: iterature Distribution Center for ON Semiconductor P.O. Box 563, Denver, Colorado 8027 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order iterature: m/on/ /D 8 For additional information, please contact your local Sales Representative
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