NB3N508S. 3.3V, 216 MHz PureEdge VCXO Clock Generator with M LVDS Output
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1 3.3V, 216 MHz PureEdge VCXO Clock Generator with M LVDS Output Description The NB3N508S is a high precision, low phase noise Voltage Controlled Crystal Oscillator (VCXO) and phase lock loop (PLL) that generates 216 MHz M LVDS output from a 27 MHz crystal. The ±100 ppm output pullable range is obtained using the V IN pin of the VCXO with usable range from 0 V to 3.3 V. The VCXO input pin V IN is a high impedance input that can be driven directly from a pulse width modulated RC integrator circuit. The NB3N508S is designed primarily for data and clock recovery applications within end products such as ADSL modems, set top box receivers, and telecom systems. This device is housed in 5.0 mm x 4.4 mm narrow body TSSOP 16 pin package. Features PureEdge Clock Family Provides Accuracy and Precision Performs Precision Clock Multiplication from 27 MHz Crystal Uses 27 MHz Fundamental Mode Crystal External Loop Filter is Not Required 216 MHz M LVDS Output VCXO with Pull Range 100 ppm 0 V to 3.3 V VCXO Tuning Voltage Range Capabilities Phase Noise: Offset Noise Power 100 Hz 80 dbc 1 khz 88 dbc 10 khz 105 dbc 100 khz 106 dbc 1 MHz 120 dbc 10 MHz 145 dbc Operating Range 3.3 V 5% These are Pb Free Devices* 16 1 TSSOP 16 DT SUFFIX CASE 948F MARKING DIAGRAM NB3N 508S ALYW A = Assembly Location L = Wafer Lot Y = Year W = Work Week = Pb Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet Semiconductor Components Industries, LLC, 2006 October, 2006 Rev. 0 1 Publication Order Number: NB3N508S/D
2 27 MHz Crystal X1 X2 VCXO Phase Detector Charge Pump VCO M LVDS Output V IN N Figure 1. NB3N508S Simplified Logic Diagram *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 2
3 X X NC 3 14 V IN 4 5 NB3N508S NC NC Figure 2. Pin Configuration (Top View) Table 1. PIN DESCRIPTION Pin Name I/O Description 1 X1 Crystal Input Crystal input(in). Connect to a 27 MHz crystal. 2, 3, 4, 10 Power Supply Positive power supply voltage. 5 V IN Input Analog voltage input pin that controls output oscillation frequencies. V IN pin range is from 0 V to 3.3 V. V IN voltage should not exceed. 6, 7, 8, 12 Power Supply Ground 0 V. These pins provide return path for the devices. 9, 11, 15 NC No Connect. 13 M LVDS Output Inverted clock output. Typically loaded with 50 receiver termination resistor across diff. pair. 14 M LVDS Output Noninverted clock output. Typically loaded with 50 receiver termination resistor across diff. pair. 16 X2 Crystal Input Crystal input(out). Connect to a 27 MHz crystal. Recommended Crystal Parameters Crystal Fundamental AT Cut Frequency Load Capacitance Shunt Capacitance, C0 Max Equivalent Series Resistance Max Initial Accuracy at 25 C Temperature Stability Aging C0/C1 Ration 27 MHz 14 pf 7 pf 35 ±20 ppm ±30 ppm ±20 ppm 250 Max 3
4 Table 2. ATTRIBUTES Characteristics Value ESD Protection Human Body Model Machine Model > 4 kv > 400 V Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) TSSOP 16 Level 3 Flammability Rating Oxygen Index: 28 to 34 UL 94 V in Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D Devices Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit Positive Power Supply = 0 V 4.6 V V I Input Voltage (V IN ) = 0 V V I V I OUT M LVDS Output Current Continuous Surge ma ma T A Operating Temperature Range 0 to +70 C T STG Storage Temperature Range 65 to +150 C JA Thermal Resistance (Junction to Ambient) 0 lfpm 500 lfpm TSSOP 16 TSSOP C/W C/W JA Thermal Resistance (Junction to Case) (Note 2) TSSOP to 36 C/W T SOL Wave Solder Pb Free 265 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 2. JEDEC standard multilayer board 2S2P (2 Signal, 2 Power). Table 4. DC CHARACTERISTICS ( = V to V, = 0 V, T A = 0 C to +70 C) Symbol Characteristic Min Typ Max Unit I DD Power Supply Current (outputs loaded with R L = 50 ) ma V IA VCXO Control Voltage, V IN V V OD Differential Output Voltage (Note 3) mv V OD Change in Magnitude of V OD for Complementary Output States (Notes 3, 6) mv V OS Offset Voltage (See Figure 4) mv V OS Change in Magnitude of V OS for Complementary Output States (Note 6) mv V OH Output HIGH Voltage (Note 4) mv V OL Output LOW Voltage (Note 5) mv I SC Output Short Circuit Current or to 43 ma NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. M LVDS outputs require 50 receiver termination resistor between differential. pair. See Figure 3 4. V OHmax = V OSmax + ½ V ODmax. 5. V OLmax = V OSmin ½ V ODmax. 6. Parameters guaranteed by design but not tested in production. 4
5 Table 5. AC CHARACTERISTICS ( = V to V, = 0 V, T A = 0 C to +70 C, Note 7) Symbol Characteristic Min Typ Max Unit f IN Crystal Input Frequency 27 MHz f OUT Output Clock Frequency 216 MHz NOISE Phase Noise Performance f OUT = Hz Offset from 1 khz Offset from 10 khz Offset from 100 khz Offset from 1 MHz Offset from 10 MHz Offset from Carrier dbc/hz Spurious Noise Components 60 dbc/hz F P Crystal Pullability 0 V V IN 3.3 V 100 ppm t DUTY_CYCLE Output Clock Duty Cycle (Measured at Crosspoint) % t R Output Rise Time (/) (Note 8) ps t F Output Fall Time (/) (Note 8) ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. / loaded with 50 receiver termination resistor between diff. pair. 8. Measured differentially ( ) at 10% to 90%; R L = 50. Phase Noise 10.00dB/Ref 20.00dBc/Hz NOISE POWER (dbc) OFFSET FREQUENCY (Hz) Figure 3. Typical Phase Noise Plot ( = 3.3 V, V IN = 0 V; Room Temperature) 5
6 FREQUENCY ERROR (ppm) Maximum Minimum FREQUENCY (MHz) V IN, CONTROL VOLTAGE (V) Figure 4. VCXO Pulling Range V IN, CONTROL VOLTAGE (V) Figure 5. Output Clock Frequency vs. V IN and Temperature Figure 6. Typical Crystal Startup Time with V IN = 0 V at Ambient Temperature (1.99 ms) Figure 7. Typical Crystal Startup Time with V IN = 3.3 V at Ambient Temperature (694 s) M LVDS Driver Device Z o = 50 Z o = D D M LVDS Receiver Device Figure 8. Typical Termination for Output Driver and Device Evaluation V OH V OS V OD V OL Figure 9. H LVDS Output 6
7 ORDERING INFORMATION NB3N508SDTG NB3N508SDTR2G Device Package Shipping TSSOP 16 (Pb Free) TSSOP 16 (Pb Free) 96 Units / Rail 2500 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 7
8 PACKAGE DIMENSIONS TSSOP 16 CASE 948F 01 ISSUE A 0.15 (0.006) T 0.15 (0.006) T 0.10 (0.004) T SEATING PLANE L U PIN 1 IDENT. U D S S 2X L/2 C 16X K REF 0.10 (0.004) M T U S V S A V G B U H N J N J1 F DETAIL E DETAIL E K K1 ÇÇÇ ÉÉÉ SECTION N N 0.25 (0.010) M W NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE W. MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G 0.65 BSC BSC H J J K K L 6.40 BSC BSC M ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative NB3N508S/D
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MUN526DW, NSBC43TDXV6 Dual NPN Bias Resistor Transistors R = 4.7 k, R2 = k NPN Transistors with Monolithic Bias Resistor Network This series of digital transistors is designed to replace a single device
NBXSBA /3.3 V, MHz LVPECL Clock Oscillator
2.5/. V, 5. MHz LVPECL Clock Oscillator The NBXSBA051, single frequency, crystal oscillator (XO) is designed to meet today s requirements for 2.5/. V LVPECL clock generation applications. The device uses
MBRM110LT3G NRVBM110LT1G NRVBM110LT3G. Surface Mount Schottky Power Rectifier. POWERMITE Power Surface Mount Package
MBRM11LT1G, NRVBM11LT1G, NRVBM11LT3G Surface Mount Schottky Power Rectifier Power Surface Mount Package The Schottky employs the Schottky Barrier principle with a barrier metal and epitaxial construction
NSVEMD4DXV6T5G. Dual Bias Resistor Transistors. NPN and PNP Silicon Surface Mount Transistors with Monolithic Bias Resistor Network
Dual Bias Resistor Transistors NPN and PNP Silicon Surface Mount Transistors with Monolithic Bias Resistor Network The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias
MUN5211T1 Series. NPN Silicon Surface Mount Transistor with Monolithic Bias Resistor Network NPN SILICON BIAS RESISTOR TRANSISTORS
MUNT Series Preferred Devices Bias Resistor Transistor NPN Silicon Surface Mount Transistor with Monolithic Bias Resistor Network This new series of digital transistors is designed to replace a single
NTMD4840NR2G. Power MOSFET 30 V, 7.5 A, Dual N Channel, SOIC 8
NTMDN Power MOSFET 3 V, 7. A, Dual N Channel, SOIC Features Low R DS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses Dual
MMUN2211LT1 Series. NPN Silicon Surface Mount Transistor with Monolithic Bias Resistor Network
MMUNLT Series Preferred Devices Bias Resistor Transistor NPN Silicon Surface Mount Transistor with Monolithic Bias Resistor Network This new series of digital transistors is designed to replace a single
NTD5865NL. N-Channel Power MOSFET 60 V, 46 A, 16 m
N-Channel Power MOSFET 6 V, 6 A, 6 m Features Low Gate Charge Fast Switching High Current Capability % Avalanche Tested These Devices are Pb Free, Halogen Free and are RoHS Compliant MAXIMUM RATINGS (
PIN CONNECTIONS MAXIMUM RATINGS (T J = 25 C unless otherwise noted) SC 75 (3 Leads) Parameter Symbol Value Unit Drain to Source Voltage V DSS 30 V
NTA7N, NVTA7N Small Signal MOSFET V, 4 ma, Single, N Channel, Gate ESD Protection, SC 7 Features Low Gate Charge for Fast Switching Small.6 x.6 mm Footprint ESD Protected Gate NV Prefix for Automotive
NBXDPA V / 3.3 V, 125 MHz / 250 MHz LVDS Clock Oscillator
2.5 V / 3.3 V, 125 MHz / 250 MHz LVS Clock Oscillator The NBXPA019 dual frequency crystal oscillator (XO) is designed to meet today s requirements for 2.5 V and 3.3 V LVS clock generation applications.
NBXHGA /3.3 V, MHz LVPECL Clock Oscillator
2.5/. V, 125.00 MHz LVPECL Clock Oscillator The NBXHGA019, single frequency, crystal oscillator (XO) is designed to meet today s requirements for 2.5/. V LVPECL clock generation applications. The device
NTS2101P. Power MOSFET. 8.0 V, 1.4 A, Single P Channel, SC 70
NTS11P Power MOSFET 8. V, 1.4 A, Single P Channel, SC 7 Features Leading Trench Technology for Low R DS(on) Extending Battery Life 1.8 V Rated for Low Voltage Gate Drive SC 7 Surface Mount for Small Footprint
MMBZxxxALT1G Series, SZMMBZxxxALT1G Series. 24 and 40 Watt Peak Power Zener Transient Voltage Suppressors
MMBZxxxALTG Series, SZMMBZxxxALTG Series 24 and 4 Watt Peak Power Zener Transient Voltage Suppressors Dual Common Anode Zeners for ESD Protection These dual monolithic silicon Zener diodes are designed
NBXDBA V, 62.5 MHz / 125 MHz LVPECL Clock Oscillator
. V, 62.5 MHz / 125 MHz LVPECL Clock Oscillator The NBXBA014 dual frequency crystal oscillator (XO) is designed to meet today s requirements for. V LVPECL clock generation applications. The device uses
NTR4101P, NTRV4101P. Trench Power MOSFET 20 V, Single P Channel, SOT 23
NTRP, NTRVP Trench Power MOSFET V, Single P Channel, SOT Features Leading V Trench for Low R DS(on). V Rated for Low Voltage Gate Drive SOT Surface Mount for Small Footprint NTRV Prefix for Automotive
MMBZxxVAWT1G Series, SZMMBZxxVAWT1G Series. 40 Watt Peak Power Zener Transient Voltage Suppressors. SC 70 Dual Common Anode Zeners for ESD Protection
MMBZxxVAWTG Series, SZMMBZxxVAWTG Series 4 Watt Peak Power Zener Transient Voltage Suppressors SC 7 Dual Common Anode Zeners for ESD Protection These dual monolithic silicon Zener diodes are designed for
NTHD4502NT1G. Power MOSFET. 30 V, 3.9 A, Dual N Channel ChipFET
NTHDN Power MOSFET V,.9 A, Dual N Channel ChipFET Features Planar Technology Device Offers Low R DS(on) and Fast Switching Speed Leadless ChipFET Package has % Smaller Footprint than TSOP. Ideal Device
MMBZ15VDLT3G MMBZ27VCLT1G SZMMBZ15VDLT3G. SZMMBZ27VCLT1G 40 Watt Peak Power Zener Transient Voltage Suppressors
MMBZ15VDLT1G, MMBZ27VCLT1G, SZMMBZ15VDLT1G, SZMMBZ27VCLT1G 40 Watt Peak Power Zener Transient Voltage Suppressors Dual Common Cathode Zeners for ESD Protection These dual monolithic silicon zener diodes
MBD110DWT1G MBD330DWT1G. Dual Schottky Barrier Diodes
, Dual Schottky Barrier Diodes Application circuit designs are moving toward the consolidation of device count and into smaller packages. The new SOT363 package is a solution which simplifies circuit design,
NTNS3164NZT5G. Small Signal MOSFET. 20 V, 361 ma, Single N Channel, SOT 883 (XDFN3) 1.0 x 0.6 x 0.4 mm Package
NTNS36NZ Small Signal MOSFET V, 36 ma, Single N Channel, SOT 883 (XDFN3). x.6 x. mm Package Features Single N Channel MOSFET Ultra Low Profile SOT 883 (XDFN3). x.6 x. mm for Extremely Thin Environments
NSS40301MDR2G. 40 VOLTS 6.0 AMPS NPN LOW V CE(sat) TRANSISTOR EQUIVALENT R DS(on) 44 m
NSS3MDR2G Dual Matched V, 6. A, Low V CE(sat) NPN Transistor These transistors are part of the ON Semiconductor e 2 PowerEdge family of Low V CE(sat) transistors. They are assembled to create a pair of
MC3488A. Dual EIA 423/EIA 232D Line Driver
Dual EIA423/EIA232D Line Driver The MC34A dual is singleended line driver has been designed to satisfy the requirements of EIA standards EIA423 and EIA232D, as well as CCITT X.26, X.2 and Federal Standard
NTLUD3A260PZ. Power MOSFET 20 V, 2.1 A, Cool Dual P Channel, ESD, 1.6x1.6x0.55 mm UDFN Package
NTLUDAPZ Power MOSFET V,. A, Cool Dual P Channel, ESD,.x.x. mm UDFN Package Features UDFN Package with Exposed Drain Pads for Excellent Thermal Conduction Low Profile UDFN.x.x. mm for Board Space Saving
MMSZxxxET1 Series, SZMMSZxxxET1G Series. Zener Voltage Regulators. 500 mw SOD 123 Surface Mount
MMSZxxxET Series, SZMMSZxxxETG Series Zener Voltage Regulators 5 mw SOD 3 Surface Mount Three complete series of Zener diodes are offered in the convenient, surface mount plastic SOD 3 package. These devices
NGB8207AN, NGB8207ABN. Ignition IGBT 20 A, 365 V, N Channel D 2 PAK. 20 AMPS, 365 VOLTS V CE(on) = 1.75 V I C = 10 A, V GE 4.
NGB827AN, NGB827ABN Ignition IGBT 2 A, 365 V, N Channel D 2 PAK This Logic Level Insulated Gate Bipolar Transistor (IGBT) features monolithic circuitry integrating ESD and Overvoltage clamped protection
MRA4003T3G Series, NRVA4003T3G Series. Surface Mount Standard Recovery Power Rectifier. SMA Power Surface Mount Package
MRA43T3G Series, NRVA43T3G Series Surface Mount Standard Recovery Power Rectifier Power Surface Mount Package Features construction with glass passivation. Ideally suited for surface mounted automotive
BD809 (NPN), BD810 (PNP) Plastic High Power Silicon Transistor 10 AMPERE POWER TRANSISTORS 80 VOLTS 90 WATTS
BD89 (NPN), BD8 (PNP) Plastic High Power Silicon Transistor These devices are designed for use in high power audio amplifiers utilizing complementary or quasi complementary circuits. Features DC Current
EMF5XV6T5G. Power Management, Dual Transistors. NPN Silicon Surface Mount Transistors with Monolithic Bias Resistor Network
Preferred Devices Power Management, Dual Transistors NPN Silicon Surface Mount Transistors with Monolithic Bias Resistor Network Features Simplifies Circuit Design Reduces Board Space Reduces Component
P1P Portable Gaming Audio/Video Multimedia. MARKING DIAGRAM. Features
.8V, 4-PLL Low Power Clock Generator with Spread Spectrum Functional Description The PP4067 is a high precision frequency synthesizer designed to operate with a 27 MHz fundamental mode crystal. Device
NTJD1155LT1G. Power MOSFET. 8 V, 1.3 A, High Side Load Switch with Level Shift, P Channel SC 88
NTJDL Power MOSFET V,.3 A, High Side Load Switch with Level Shift, P Channel SC The NTJDL integrates a P and N Channel MOSFET in a single package. This device is particularly suited for portable electronic
NTLUS3A90PZ. Power MOSFET 20 V, 5.0 A, Cool Single P Channel, ESD, 1.6x1.6x0.55 mm UDFN Package
NTLUS3A9PZ Power MOSFET V, 5. A, Cool Single P Channel, ESD,.x.x.55 mm UDFN Package Features UDFN Package with Exposed Drain Pads for Excellent Thermal Conduction Low Profile UDFN.x.x.55 mm for Board Space
NUD4700. LED Shunt. Features. Typical Applications MARKING DIAGRAM PIN FUNCTION DESCRIPTION ORDERING INFORMATION.
LED Shunt The is an electronic shunt which provides a current bypass in the case of a single LED going into open circuit. LEDs are by nature quite fragile when subjected to transients and surge conditions.
MARKING DIAGRAM Mechanical Characteristics. B2E1 Epoxy Meets UL 94 V in
Surface Mount Schottky Power Rectifier Power Surface Mount Package This device employs the Schottky Barrier principle in a metal to silicon power rectifier. Features epitaxial construction with oxide passivation
MMUN2111LT1 Series. Bias Resistor Transistors. PNP Silicon Surface Mount Transistors with Monolithic Bias Resistor Network
MMUNLT Series Preferred Devices Bias Resistor Transistors PNP Silicon Surface Mount Transistors with Monolithic Bias Resistor Network This new series of digital transistors is designed to replace a single
NGD18N40CLBT4G. Ignition IGBT 18 Amps, 400 Volts N Channel DPAK. 18 AMPS 400 VOLTS V CE(on) 2.0 I C = 10 A, V GE 4.5 V
NGD8NCLB Ignition IGBT 8 Amps, Volts N Channel DPAK This Logic Level Insulated Gate Bipolar Transistor (IGBT) features monolithic circuitry integrating ESD and Over Voltage clamped protection for use in
MUN5211DW1T1 Series. NPN Silicon Surface Mount Transistors with Monolithic Bias Resistor Network
MUNDWT Series Preferred Devices Dual Bias Resistor Transistors NPN Silicon Surface Mount Transistors with Monolithic Bias Resistor Network The BRT (Bias Resistor Transistor) contains a single transistor
MBRS360T3, MBRS360BT3G. Surface Mount Schottky Power Rectifier SCHOTTKY BARRIER RECTIFIERS 3.0 AMPERES, 60 VOLTS
Surface Mount Schottky Power Rectifier This device employs the Schottky Barrier principle in a large area metal to silicon power diode. State of the art geometry features epitaxial construction with oxide
NGB18N40CLB, NGB18N40ACLB. Ignition IGBT 18 Amps, 400 Volts. N Channel D 2 PAK. 18 AMPS, 400 VOLTS V CE(on) 2.0 I C = 10 A, V GE 4.
NGB8N4CLB, NGB8N4ACLB Ignition IGBT 8 Amps, 4 Volts N Channel D PAK This Logic Level Insulated Gate Bipolar Transistor (IGBT) features monolithic circuitry integrating ESD and Over Voltage clamped protection