NTHS2101P. Power MOSFET. 8.0 V, 7.5 A P Channel ChipFET

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1 NTHSP Power MOSFET. V,. A P Channel ChipFET Features Offers an Ultra Low R S(on) Solution in the ChipFET Package Miniature ChipFET Package % Smaller Footprint than TSOP making it an Ideal evice for Applications where Board Space is at a Premium Low Profile (<. mm) Allows it to Fit Easily into Extremely Thin Environments such as Portable Electronics esigned to Provide Low R S(on) at Gate Voltage as Low as. V, the Operating Voltage used in many Logic ICs in Portable Electronics Simplifies Circuit esign since Additional Boost Circuits for Gate Voltages are not Required Operated at Standard Logic Level Gate rive, Facilitating Future Migration to Lower Levels using the same Basic Topology Pb Free Package is Available Applications Optimized for Battery and Load Management Applications in Portable Equipment such as MP Players, Cell Phones, igital Cameras, Personal igital Assistant and other Portable Applications Charge Control in Battery Chargers Buck and Boost Converters MAXIMUM RATINGS (T J = C unless otherwise noted) Rating Symbol Value Unit V (BR)SS. V G Ultra Low R S(on) TYP S P Channel MOSFET ChipFET CASE A STYLE I MAX 9 V GS V GS. A V GS rain to Source Voltage V SS. V dc Gate to Source Voltage Continuous V GS. V dc PIN CONNECTIONS MARKING IAGRAM rain Current Continuous seconds I.. A Total Power issipation T A = C ( T A = C C ( C P.... W S G M Continuous Source Current Is. A Thermal Resistance (Note ) Junction to Ambient, sec Junction to Ambient, Continuous Maximum Lead Temperature for Soldering Purposes, / from case for seconds R JA 9 C/W T L C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.. Surface Mounted on FR Board using in sq pad size (Cu area =. in sq [ oz] including traces). = Specific evice Code M = Month Code ORERING INFORMATION evice Package Shipping NTHSPT ChipFET /Tape & Reel NTHSPTG ChipFET /Tape & Reel (Pb Free) For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BR/. Semiconductor Components Industries, LLC, October, Rev. Publication Order Number: NTHSP/

2 NTHSP ELECTRICAL CHARACTERISTICS (T J = C unless otherwise noted) Characteristic Symbol Test Condition Min Typ Max Unit OFF CHARACTERISTICS rain to Source Breakdown Voltage (Note ) Temperature Coefficient (Positive) V (Br)SS V GS = V dc, I = A dc. V dc Gate Body Leakage Current Zero I GSS V S = V dc, V GS =. V dc na dc Zero Gate Voltage rain Current I SS V S =. V dc, V GS = V dc V S =. V dc, V GS = V dc, T J = C ON CHARACTERISTICS (Note ).. A dc Gate Threshold Voltage V GS(th) V S = V GS, I = A dc.. V dc Static rain to Source On Resistance R S(on) V GS =. V dc, I =. A dc V GS =. V dc, I =. A dc V GS =. V dc, I =. A dc Forward Transconductance g FS V S =. V dc, I =. A dc S iode Forward Voltage V S I S =. A dc, V GS = V dc.. V YNAMIC CHARACTERISTIC Input Capacitance C iss V S =. V dc pf V Output Capacitance C GS = V oss f=mhz. Transfer Capacitance C rss SWITCHING CHARACTERISTICS (Note ) Turn On elay Time t d(on) V =. V dc. ns V Rise Time t GS =. V dc r I =. A dc Turn Off elay Time t d(off) R G =. (Note ) Fall Time t f Gate Charge Q G V GS =. V dc nc Q GS I =. Adc. Q G V S =. V dc. Source rain Reverse Recovery Time T rr I F =. A, di/dt = A/ s 9 ns. Pulse Test: Pulse Width = s, uty Cycle = %.. Switching characteristics are independent of operating junction temperatures. 9 m

3 NTHSP TYPICAL ELECTRICAL CHARACTERISTICS I, RAIN CURRENT (AMPS) V GS = thru. V V T J = C. V. V. V V S, RAIN TO SOURCE VOLTAGE (V) Figure. On Region Characteristics I, RAIN CURRENT (AMPS) T J = C T J = C T J = C..... V GS, GATE TO SOURCE VOLTAGE (V) Figure. Transfer Characteristics. R S(on), RAIN TO SOURCE RESISTANCE ( )..... V GS =. V V GS =. V V GS =. V I, RAIN CURRENT (A) Figure. On Resistance versus rain Current and Gate Voltage R S(on), RAIN TO SOURCE RESISTANCE (NORMALIZE)..... V GS =. V. T J, JUNCTION TEMPERATURE ( C) Figure. On Resistance Variation with Temperature I SS, LEAKAGE (na), V GS = V T J = C T J = C V S, RAIN TO SOURCE VOLTAGE (V) Figure. rain to Source Leakage Current vs. Voltage C, CAPACITANCE (pf) C iss C rss C oss C rss V GS V S GATE TO SOURCE OR RAIN TO SOURCE VOLTAGE (V) Figure. Capacitance Variation T J = C C iss

4 NTHSP TYPICAL ELECTRICAL CHARACTERISTICS V GS, GATE TO SOURCE VOLTAGE (VOLTS) Q Q T Q V GS I =. A T J = C 9 Q G, TOTAL GATE CHARGE (nc) Figure. Gate to Source and rain to Source Voltage vs. Total Charge V S, RAIN TO SOURCE VOLTAGE (VOLTS) t, TIME (ns) V =. V I =. A V GS =. V td(off) R G, GATE RESISTANCE ( ) t d(on) Figure. Resistive Switching Time Variation vs. Gate Resistance t f t r I S, SOURCE CURRENT (AMPS) V GS = V T J = C..... V S, SOURCE TO RAIN VOLTAGE (V) Figure 9. iode Forward Voltage vs. Current NORMALIZE EFFECTIVE TRANSIENT THERMAL IMPEANCE. uty Cycle =..... Single Pulse. Notes: P M t t t. uty Cycle, = t. Per Unit Base = R thja = C/W. T JM T A = P M Z (t) thja. Surface Mounted SQUARE WAVE PULSE URATION (sec) Figure. Normalized Thermal Transient Impedance, Junction to Ambient

5 NTHSP PACKAGE IMENSIONS ChipFET CASE A ISSUE E L S A G B M J K NOTES:. IMENSIONING AN TOLERANCING PER ANSI Y.M, 9.. CONTROLLING IMENSION: MILLIMETER.. MOL GATE BURRS SHALL NOT EXCEE. MM PER SIE.. LEAFRAME TO MOLE BOY OFFSET IN HORIZONTAL AN VERTICAL SHALL NOT EXCEE. MM.. IMENSIONS A AN B EXCLUSIVE OF MOL GATE BURRS.. NO MOL FLASH ALLOWE ON THE TOP AN BOTTOM LEA SURFACE.. A AN A OBSOLETE. NEW STANAR IS A. C. (.) STYLE : PIN. RAIN. RAIN. RAIN. GATE. SOURCE. RAIN. RAIN. RAIN MILLIMETERS INCHES IM MIN MAX MIN MAX A.9... B.... C G. BSC. BSC J.... K.... L. BSC. BSC M NOM NOM S.... SOLERING FOOTPRINTS* SCALE : mm inches Basic Style.. mm inches *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLERRM/.

6 NTHSP ChipFET is a trademark of Vishay Siliconix. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORERING INFORMATION LITERATURE FULFILLMENT: Literature istribution Center for ON Semiconductor P.O. Box, Phoenix, Arizona USA Phone: 9 or Toll Free USA/Canada Fax: 9 9 or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: 9 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 9 Kamimeguro, Meguro ku, Tokyo, Japan Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative. NTHSP/

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