NTLJD4116NT1G. Power MOSFET. 30 V, 4.6 A, Cool Dual N Channel, 2x2 mm WDFN Package
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1 NTLJDN Power MOSFET V,. A, Cool Dual N Channel, x mm WDFN Package Features WDFN Package Provides Exposed Drain Pad for Excellent Thermal Conduction x mm Footprint Same as SC 88 Lowest R DS(on) Solution in x mm Package. V R DS(on) Rating for Operation at Low Voltage Gate Drive Logic Level Low Profile (<.8 mm) for Easy Fit in Thin Environments This is a Pb Free Device Applications DC DC Converters (Buck and Boost Circuits) Low Side Load Switch Optimized for Battery and Load Management Applications in Portable Equipment such as, Cell Phones, PDA s, Media Players, etc. Level Shift for High Side Load Switch MAXIMUM RATINGS (T J = C unless otherwise noted) Parameter Symbol Value Unit Drain to Source Voltage V DSS V Gate to Source Voltage V GS ±8. V Continuous Drain Steady T A = C I D.7 A Current (Note ) State T A = 8 C.7 Power Dissipation (Note ) Continuous Drain Current (Note ) Power Dissipation (Note ) t s T A = C. Steady P D. W State T A = C t s. T A = C I D. A Steady T A = 8 C.8 State T A = C P D.7 W Pulsed Drain Current t p = s I DM A Operating Junction and Storage Temperature T J, T STG to C Source Current (Body Diode) (Note ) I S. A Lead Temperature for Soldering Purposes (/8 from case for s) T L C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.. Surface Mounted on FR Board using in sq pad size (Cu area =.7 in sq [ oz] including traces).. Surface Mounted on FR Board using the minimum recommended pad size of mm, oz Cu. V (BR)DSS R DS(on) MAX 7 V V 9 V S G D G V V D S N CHANNEL MOSFET WDFN CASE AN I D MAX (Note ). A MARKING DIAGRAM JFM JF = Specific Device Code M = Date Code = Pb Free Package (Note: Microdot may be in either location) PIN CONNECTIONS D (Top View) D D G S Device Package Shipping NTLJDNTG ORDERING INFORMATION WDFN (Pb Free) /Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8/D. Semiconductor Components Industries, LLC, May, Rev. Publication Order Number: NTLJDN/D
2 NTLJDN THERMAL RESISTANCE RATINGS Parameter Symbol Max Unit SINGLE OPERATION (SELF HEATED) Junction to Ambient Steady State (Note ) R JA 8 Junction to Ambient Steady State Min Pad (Note ) R JA 77 Junction to Ambient t s (Note ) R JA DUAL OPERATION (EQUALLY HEATED) Junction to Ambient Steady State (Note ) R JA 8 Junction to Ambient Steady State Min Pad (Note ) R JA Junction to Ambient t s (Note ) R JA. Surface Mounted on FR Board using in sq pad size (Cu area =.7 in sq [ oz] including traces).. Surface Mounted on FR Board using the minimum recommended pad size ( mm, oz Cu). C/W C/W
3 NTLJDN MOSFET ELECTRICAL CHARACTERISTICS (T J = C unless otherwise noted) Parameter Symbol Test Conditions Min Typ Max Unit OFF CHARACTERISTICS Drain to Source Breakdown Voltage V (BR)DSS V GS = V, I D = A V Drain to Source Breakdown Voltage Temperature Coefficient V (BR)DSS /T J I D = A, Ref to C 8. mv/ C Zero Gate Voltage Drain Current I DSS V DS = V, V GS = V T J = C. A T J = 8 C Gate to Source Leakage Current I GSS V DS = V, V GS = ±8. V na ON CHARACTERISTICS (Note ) Gate Threshold Voltage V GS(TH) V GS = V DS, I D = A..7. V Negative Gate Threshold Temperature Coefficient V GS(TH) /T J.8 mv/ C Drain to Source On Resistance R DS(on) V GS =., I D =. A 7 7 m V GS =., I D =. A 9 V GS =.8, I D =.8 A 88 V GS =., I D =. A Forward Transconductance g FS V DS =. V, I D =. A. S Input Capacitance C CHARGES, CAPACITANCES AND GATE RESISTANCE 7 pf Output Capacitance ISS C OSS V GS = V, f =. MHz, V DS = V Reverse Transfer Capacitance C RSS Threshold Gate Charge Q G(TH) VGS =. V, VDS = V,. Gate to Source Charge Q GS I D =. A.8 Gate to Drain Charge Q GD... nc Gate Resistance R G.7 Turn On Delay Time t d(on) SWITCHING CHARACTERISTICS (Note ).8 ns Rise Time t r VGS =. V, VDD = V,.8 Turn Off Delay Time t d(off) I D =. A, R G =.. Fall Time t f.7 DRAIN SOURCE DIODE CHARACTERISTICS Forward Recovery Voltage V SD V GS = V, IS =. A T J = C.78. T J = C. Charge Time t a VGS = V, disd/dt = A/ s, 7. Discharge Time t b I S =. A.9 Reverse Recovery Time Q RR. nc. Pulse Test: Pulse Width s, Duty Cycle %.. Switching characteristics are independent of operating junction temperatures.. V ns
4 NTLJDN TYPICAL PERFORMANCE CURVES (T J = C unless otherwise noted) V GS =.7 V to 8 V T J = C. V. V. V. V. V V DS V T J = C T J = C. T J = C.. V DS, DRAIN TO SOURCE VOLTAGE (VOLTS) V GS, GATE TO SOURCE VOLTAGE (VOLTS) Figure. On Region Characteristics Figure. Transfer Characteristics R DS(on), DRAIN TO SOURCE RESISTANCE ( ) V GS =. V. T J = C T J = C T J = C.. R DS(on), DRAIN TO SOURCE RESISTANCE ( ) T J = C V GS =.8 V V GS =. V V GS =. V Figure. On Resistance versus Drain Current Figure. On Resistance versus Drain Current and Gate Voltage R DS(on), DRAIN TO SOURCE RESISTANCE (NORMALIZED) I D = A V GS =. V. 7 T J, JUNCTION TEMPERATURE ( C) Figure. On Resistance Variation with Temperature I DSS, LEAKAGE (na),, V GS = V T J = C T J = C V DS, DRAIN TO SOURCE VOLTAGE (VOLTS) Figure. Drain to Source Leakage Current versus Voltage
5 NTLJDN TYPICAL PERFORMANCE CURVES (T J = C unless otherwise noted) C, CAPACITANCE (pf) V DS = V V GS = V T J = C 8 C iss C rss C oss V GS V DS V GS, GATE TO SOURCE VOLTAGE (VOLTS) Q GS V DS V GS Q GD QT I D =. A T J = C Q G, TOTAL GATE CHARGE (nc) 8 9 V DS, DRAIN TO SOURCE VOLTAGE (VOLTS) GATE TO SOURCE OR DRAIN TO SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation Figure 8. Gate To Source and Drain To Source Voltage versus Total Charge t, TIME (ns) V DD = V I D =. A V GS =. V t d(off) t f t r t d(on), SOURCE CURRENT (AMPS) V GS = V T J = C IS T J = C T J = C R G, GATE RESISTANCE (OHMS).. V SD, SOURCE TO DRAIN VOLTAGE (VOLTS).9 Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure. Diode Forward Voltage versus Current T C = C T J = C SINGLE PULSE s s ms ms *See Note on Page. R DS(on) LIMIT THERMAL LIMIT dc PACKAGE LIMIT.. V DS, DRAIN TO SOURCE VOLTAGE (VOLTS) Figure. Maximum Rated Forward Biased Safe Operating Area
6 NTLJDN TYPICAL PERFORMANCE CURVES (T J = C unless otherwise noted) EFFECTIVE TRANSIENT THERMAL RESISTANCE D = SINGLE PULSE..... P (pk). t, TIME (s) Figure. Thermal Response t t DUTY CYCLE, D = t /t. D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t T J(pk) T A = P (pk) R JA (t) *See Note on Page
7 NTLJDN PACKAGE DIMENSIONS WDFN, x CASE AN ISSUE B X PIN ONE REFERENCE. C X. C. C D ÍÍÍ ÍÍÍ A A B E NOTES:. DIMENSIONING AND TOLERANCING PER ASME Y.M, 99.. CONTROLLING DIMENSION: MILLIMETERS.. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN. AND.mm FROM TERMINAL.. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS DIM MIN MAX A.7.8 A.. A. REF b.. D. BSC D.7.77 E. BSC E.9. e. BSC K. REF L.. J. REF A X.8 C X L D A D e X C SEATING PLANE X. SOLDERMASK DEFINED MOUNTING FOOTPRINT*. X. XE. PITCH X K X J BOTTOM VIEW b X. C. C A B NOTE. X.7. DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Cool is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box, Phoenix, Arizona 88 USA Phone: or 8 8 Toll Free USA/Canada Fax: or 8 87 Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 9 Kamimeguro, Meguro ku, Tokyo, Japan Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative. NTLJDN/D
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