NB6L V/3.3 V Multilevel Input to Differential LVPECL/LVNECL 1:2 Clock or Data Fanout Buffer/Translator
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1 .5 V/3.3 V Multilevel Input to ifferential LVPECL/LVNECL : Clock or ata Fanout Buffer/Translator The NB6L is an enhanced differential : clock or data fanout buffer/translator. The device has the same pinout and is functionally equivalent to the LVEL, EP, LVEP devices. Moreover, the device is optimized for the systems that require LOW skew, LOW jitter and LOW power consumption. ifferential input can be configured to accept single ended signal by applying an external reference voltage to unused complementary input pin. Input accept LVNECL, LVPECL, LVTTL, LVCMOS, CML, or LVS. The outputs are 00 ECL signals. Features Input Clock Frequency 6 GHz Input ata Rate 6 Gb/s Low 4 ma Typical Power Supply Current ps Typical Propagation elay 5 ps Typical Within evice Skew 75 ps Typical Rise/Fall Times PECL Mode Operating Range: =.375 V to V with = 0 V NECL Mode Op rating Range: = 0 V with =.375 V to V Open Input efault State Q Outputs Will efault LOW with Inputs Open or at LVS, LVPECL, LVNECL, LCMOS, LVTTL and CML Input Compatible These evices are Pb Free and are RoHS Compliant SO SUFFIX CASE 75 TSSOP T SUFFIX CASE 94R MARKING IAGRAMS* 6L ALYW 6L ALYW A = Assembly Location L = Wafer Lot Y = Year W = Work Week = Pb Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AN00/. ORERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page of this data sheet. Semiconductor Components Industries, LLC, 03 June, 03 Rev. 9 Publication Order Number: NB6L/
2 Q0 Q0 R 7 R Q 3 R 6 R Q 4 5 Figure. Pinout (Top View) and Logic iagram Table. PIN ESCRIPTION Pin Name I/O efault State escription ÁÁÁÁÁÁ ÁÁÁ Q0 ÁÁÁÁÁÁÁÁÁ ECL Output ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Non inverted differential clock/data output 0. Typically terminated with Resistor to V TT = ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ V. Q0 ECL Output Inverted differential clock/data output 0. Typically terminated with resistor to V TT = V. 3 Q ECL Output Non inverted differential clock/data output. Typically terminated with resistor to V TT = V. 4 Q ECL Output Inverted differential clock/data output. Typically terminated with resistor to V TT = V. 5 Negative power supply voltage 6 LVS, CML, LVPECL, LVNECL, LVCMOS, LVTTL Input 7 LVS, CML, LVPECL, LVNECL, LVCMOS, LVTTL Input HIGH LOW Inverted differential clock/data input. Internal 37.5 k to and 75 k to. Non inverted differential clock/data input. Internal 75 k to and 37.5 k to. Positive power supply voltage Table. ATTRIBUTES Internal Input Resistor R Internal Input Resistor R ES Protection Characteristics Human Body Model Machine Model Charged evice Model Value 37.5 k 75 k > kv > 0 V > kv Moisture Sensitivity, Indefinite Time Out of rypack (Note ) Pb Pkg Pb Free Pkg SOIC TSSOP Level Level Level Level 3 Flammability Rating Oxygen Index: to 34 UL 94 V 0.5 in Transistor Count Meets or exceeds JEEC Spec EIA/JES7 IC Latchup Test. For additional information, see Application Note AN003/. 67 evices
3 Table 3. MAXIMUM RATINGS Symbol Parameter Condition Condition Rating Unit Positive Power Supply = 0 V 3.6 V Negative Power Supply = 0 V 3.6 V V I Positive Input Voltage Negative Input Voltage = 0 V = 0 V V INPP ifferential Input Voltage. V. V V I 3.6 V I 3.6. V V V I out Output Current Continuous Surge T A Operating Temperature Range 40 to +5 C T stg Storage Temperature Range 65 to + C JA Thermal Resistance (Junction to Ambient) 0 lfpm 0 lfpm SOIC SOIC JC Thermal Resistance (Junction to Case) Standard Board SOIC 4 to 44 C/W JA Thermal Resistance (Junction to Ambient) 0 lfpm 0 lfpm TSSOP TSSOP JC Thermal Resistance (Junction to Case) Standard Board TSSOP 4 to 44 C/W T sol Wave Solder Standard Pb Free 3 4 C 3 60 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability ma ma C/W C/W C/W C/W C 3
4 Table 4. C CHARACTERISTICS, PECL =.5 V, = 0 V (Note 4) Symbol Characteristic 40 C 5 C 5 C Min Typ Max Min Typ Max Min Typ Max I EE Negative Power Supply Current (Note 5) ma V OH Output HIGH Voltage (Note 6) V OL Output LOW Voltage (Note 6) IFFERENTIAL INPUT RIVEN SINGLE ENE (Figures 4, 6) (Note 7) Input Threshold Reference Voltage Range (Note ) Unit V IH Single Ended Input HIGH Voltage V IL Single Ended Input LOW Voltage IFFERENTIAL INPUTS RIVEN IFFERENTIALLY (Figures 5, 7) (Note ) V IH ifferential Input HIGH Voltage V IL ifferential Input LOW Voltage V CMR Input Common Mode Range (ifferential Cross Point Voltage) (Note 3) V I ifferential Input Voltage (V IH V IL ) I IH Input HIGH Current A I IL Input LOW Current A NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 0 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit values are applied individually under normal operating conditions and not valid simultaneously.. is applied to the complementary input when operating in single ended mode. 3. V CMR minimum varies : with, V CMR maximum varies : with. 4. Input and output parameters vary : with. can vary +0.5 V to.3 V. 5. All input and output pins left open. 6. All loading with to.0 V. 7., V IH, and V IL parameters must be complied with simultaneously.. V IH, V IL, V I and V CMR parameters must be complied with simultaneously. 4
5 Table 5. C CHARACTERISTICS, PECL = 3.3 V, = 0 V (Note ) Symbol Characteristic 40 C 5 C 5 C Min Typ Max Min Typ Max Min Typ Max I EE Negative Power Supply Current (Note ) ma V OH Output HIGH Voltage (Note 3) V OL Output LOW Voltage (Note 3) IFFERENTIAL INPUT RIVEN SINGLE ENE (Figures 4, 6) (Note 4) Input Threshold Reference Voltage Range (Note 9) Unit V IH Single Ended Input HIGH Voltage V IL Single Ended Input LOW Voltage IFFERENTIAL INPUTS RIVEN IFFERENTIALLY (Figures 5, 7) (Note 5) V IH ifferential Input HIGH Voltage V IL ifferential Input LOW Voltage V CMR Input Common Mode Range (ifferential Cross Point Voltage) (Note ) V I ifferential Input Voltage (V IH V IL ) I IH Input HIGH Current A I IL Input LOW Current A NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 0 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit values are applied individually under normal operating conditions and not valid simultaneously. 9. is applied to the complementary input when operating in single ended mode..v CMR minimum varies : with, V CMR maximum varies : with.. Input and output parameters vary : with. can vary +0.3 V to. V..All input and output pins left open. 3.All loading with to.0 V. 4., V IH, and V IL parameters must be complied with simultaneously. 5.V IH, V IL, V I and V CMR parameters must be complied with simultaneously. 5
6 Table 6. C CHARACTERISTICS, NECL = 0 V; = V to.375 V (Note ) 40 C 5 C 5 C Symbol I EE Characteristic Negative Power Supply Current (Note 9) Min Typ Max Min Typ Max Min Typ Max ma Unit V OH Output HIGH Voltage (Note 0) V OL Output LOW Voltage (Note 0) IFFERENTIAL INPUT RIVEN SINGLE ENE (Figures 4, 6) (Note ) Input Threshold Reference Voltage Range (Note 6) V IH Single Ended Input HIGH Voltage V IL Single Ended Input LOW Voltage IFFERENTIAL INPUTS RIVEN IFFERENTIALLY (Figures 5, 7) (Note ) V IH ifferential Input HIGH Voltage V IL ifferential Input LOW Voltage V CMR Input Common Mode Range (ifferential Cross Point Voltage) (Note 7) V I ifferential Input Voltage (V IH V IL ) I IH Input HIGH Current A I IL Input LOW Current A NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 0 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit values are applied individually under normal operating conditions and not valid simultaneously. 6. is applied to the complementary input when operating in single ended mode. 7.V CMR minimum varies : with, V CMR maximum varies : with.input and output parameters vary : with. 9.Input and output pins left open. 0.All loading with to.0 V.., V IH, and V IL parameters must be complied with simultaneously..v IH, V IL, V I and V CMR parameters must be complied with simultaneously. 6
7 Table 7. AC CHARACTERISTICS = 0 V; = V to.375 V or =.375 V to V; = 0 V (Note 3) 40 C 5 C 5 C Symbol Characteristic V OUTPP Output Voltage Amplitude f in 3 GHz (See Figures & 3) f in 6 GHz Min Typ Max Min Typ Max Min Typ Max Unit f ATA Maximum Operating ata Rate 6 Gb/s t PLH, t PHL Propagation elay to Output GHz to Q, Q ps t SKEW uty Cycle Skew Within evice Skew (Note 4) evice to evice Skew ps t JITTER V INPP RMS Random Clock Jitter (Note 5) f in 6 GHz Peak to Peak ata ependent Jitter (Note 6) f in 6 Gb/s Input Voltage Swing / Sensitivity (ifferential Configuration) (Note 7) ps t r Output Rise/Fall GHz Q, Q t f (0% 0%) ps NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 0 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3.Measured using a 00 source, % duty cycle clock source. All loading with to.0 V. Input edge rates 40 ps (0% 0%). 4.See Figure 3 t skew = t PLH t PHL for a nominal % differential clock input waveform. Skew is measured between outputs under identical transitions and GHz. 5.Additive RMS jitter with % duty cycle clock signal at 6 GHz. 6.Additive Peak to Peak data dependent jitter with NRZ PRBS 3 data rate at 6 Gb/s. 7.V INPP(max) cannot exceed (applicable only when < 0 ). Input voltage swing is a single ended measurement operating in differential mode OUTPUT VOLTAGE AMPLITUE (V) C 5 C 40 C OUTPUT VOLTAGE AMPLITUE (V) C 40 C 5 C INPUT CLOCK FREQUENCY (GHz) INPUT CLOCK FREQUENCY (GHz) Figure. Output Voltage Amplitude (V OUTPP ) versus Input Clock Frequency (f IN ) and Temperature at = 3.3 V Figure 3. Output Voltage Amplitude (V OUTPP ) versus Input Clock Frequency (f IN ) and Temperature at =.5 V 7
8 Figure 4. Typical Phase Noise Plot at f carrier = 56.5 MHz Figure 5. Typical Phase Noise Plot at f carrier = 6.0 MHz Figure 6. Typical Phase Noise Plot at f carrier =.5 GHz The above phase noise plots captured using Agilent E5A show additive phase noise of the NB6L device at frequencies 56.5 MHz, 6.0 MHz,.5 GHz and GHz respectively at an operating voltage of 3.3 V in room temperature. The RMS Phase Jitter contributed by the Figure 7. Typical Phase Noise Plot at f carrier = GHz device (integrated between khz and 0 MHz; as shown in the shaded region of the plot) at each of the frequencies is 75 fs, fs, 6 fs and 4 fs respectively. The input source used for the phase noise measurements is Agilent E663B.
9 OUTPUT VOLTAGE AMPLITUE (0 /div) OUTPUT VOLTAGE AMPLITUE (0 /div) TIME (64 ps/div) Figure. Typical Output Waveform at.4 Gb/s with PRBS 3 (Total System Pk Pk Jitter is 7 ps. evice Pk Pk Jitter Contribution is 4 ps) TIME (3 ps/div) Figure 9. Typical Output Waveform at 6.5 Gb/s with PRBS 3 (Total System Pk Pk Jitter is 0 ps. evice Pk Pk Jitter Contribution is 5 ps) NOTE: = 3.3 V; V IN = 700 ; T A = 5 C. 0 PROPAGATION ELAY (ps) C 40 C 5 C RISE/FALL TIME (ps) C 5 C 40 C POWER SUPPLY VOLTAGE (V) Figure. Propagation elay versus Power Supply Voltage and Temperature POWER SUPPLY VOLTAGE (V) Figure. Rise/Fall Time versus Power Supply Voltage and Temperature 0 I EE CURRENT (ma) 7 4 = V =.375 V TEMPERATURE ( C) Figure. I EE Current versus Temperature and Power Supply Voltage 9
10 Q Q V INPP () = V IH () V IL () V INPP () = V IH () V IL () V OUTPP (Q) = V OH (Q) V OL (Q) V OUTPP (Q) = V OH (Q) V OL (Q) t PHL t PLH Figure 3. AC Reference Measurement Figure 4. ifferential Input riven Single Ended Figure 5. ifferential Inputs riven ifferentially max V IHmax V CMmax V IHmax V ILmax V IH V IL V CMR V ILmax V I = V IH V IL V IHtyp V ILtyp min GN V IHmin V ILmin V CMmin GN V IHmin V ILmin Figure 6. iagram Figure 7. V CMR iagram river evice Q Q Z o = Z o = Receiver evice V TT V TT =.0 V Figure. Typical Termination for Output river and evice Evaluation (See Application Note AN00/ Termination of ECL Logic evices.)
11 ORERING INFORMATION NB6LG evice Package Shipping SOIC (Pb Free) 9 Units / Rail NB6LRG NB6LTG SOIC (Pb Free) TSSOP (Pb Free) 0 / Tape & Reel 0 Units / Rail NB6LTRG TSSOP (Pb Free) 0 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BR0/. Resource Reference of Application Notes AN405/ ECL Clock istribution Techniques AN406/ esigning with PECL (ECL at +5.0 V) AN3/ ECLinPS I/O SPiCE Modeling Kit AN4/ Metastability and the ECLinPS Family AN56/ Interfacing Between LVS and ECL AN67/ The ECL Translator Guide AN00/ Odd Number Counters esign AN00/ Marking and ate Codes AN00/ Termination of ECL Logic evices AN066/ Interfacing with ECLinPS AN090/ AC Characteristics of ECL evices
12 PACKAGE IMENSIONS X B Y A 5 4 S 0.5 (0.0) M Y SOIC NB SUFFIX CASE ISSUE AK M K NOTES:. IMENSIONING AN TOLERANCING PER ANSI Y4.5M, 9.. CONTROLLING IMENSION: MILLIMETER. 3. IMENSION A AN B O NOT INCLUE MOL PROTRUSION. 4. MAXIMUM MOL PROTRUSION 0.5 (0.006) PER SIE. 5. IMENSION OES NOT INCLUE AMBAR PROTRUSION. ALLOWABLE AMBAR PROTRUSION SHALL BE 0.7 (0.005) TOTAL IN EXCESS OF THE IMENSION AT MAXIMUM MATERIAL CONITION THRU ARE OBSOLETE. NEW STANAR IS Z H G C 0.5 (0.0) M Z Y S X S SEATING PLANE 0. (0.004) N X 45 M J MILLIMETERS INCHES IM MIN MAX MIN MAX A B C G.7 BSC 0.0 BSC H J K M 0 0 N S SOLERING FOOTPRINT* SCALE 6: mm inches *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLERRM/.
13 PACKAGE IMENSIONS TSSOP T SUFFIX CASE 94R 0 ISSUE A 0.5 (0.006) T 0.5 (0.006) T L U U 0. (0.004) T SEATING PLANE S X L/ PIN IENT S C 5 x A V K REF 4 0. (0.004) M T U S V S G B U ETAIL E F ETAIL E 0.5 (0.0) M W NOTES:. IMENSIONING AN TOLERANCING PER ANSI Y4.5M, 9.. CONTROLLING IMENSION: MILLIMETER. 3. IMENSION A OES NOT INCLUE MOL FLASH. PROTRUSIONS OR GATE BURRS. MOL FLASH OR GATE BURRS SHALL NOT EXCEE 0.5 (0.006) PER SIE. 4. IMENSION B OES NOT INCLUE INTERLEA FLASH OR PROTRUSION. INTERLEA FLASH OR PROTRUSION SHALL NOT EXCEE 0.5 (0.0) PER SIE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. IMENSION A AN B ARE TO BE ETERMINE AT ATUM PLANE -W-. MILLIMETERS INCHES IM MIN MAX MIN MAX A B C F G 0.65 BSC 0.06 BSC K L 4.90 BSC 0.93 BSC M ECLinPS is a trademark of Semiconductor Components Industries, LLC. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORERING INFORMATION LITERATURE FULFILLMENT: Literature istribution Center for ON Semiconductor P.O. Box 563, enver, Colorado 07 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: 37 3 ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative NB6L/
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