MC10E155, MC100E155. 5VНECL 6 Bit 2:1 Mux Latch
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1 5VНECL 6 Bit 2:1 Mux Latch escription The MC10E/100E155 contains six 2:1 multiplexers followed by transparent latches with single ended outputs. When both Latch Enables (L1, L2) are LOW, the latch is transparent, and output data is controlled by the multiplexer select control,. A logic HIGH on either L1 or L2 (or both) latches the outputs. The Master eset (M) overrides all other controls to set the outputs LOW. The 100 Series contains temperature compensation. Features 850 Max. L to Output 825 Max. to Output Single Ended Outputs Asynchronous Master eset ual Latch Enables PECL Mode Operating ange: V CC = 4.2 V to 5.7 V with V EE = 0 V NECL Mode Operating ange: V CC = 0 V with V EE = 4.2 V to 5.7 V Internal Input 50 k Pulldown esistors ES Protection: Human Body Model; > 2 kv, Machine Model; > 200 V Meets or Exceeds JEEC Standard EIA/JES78 IC Latchup Test Moisture Sensitivity Level: Pb = 1 Pb Free = 3 For Additional Information, see Application Note AN8003/ Flammability ating: UL 94 V in, Oxygen Index: 28 to 34 Transistor Count = 239 evices Pb Free Packages are Available* FN SUFFIX CASE 776 MAKING IAGAM* MCxxxE155FNG AWLYYWW xxx = 10 or 100 A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb Free Package *For additional marking information, refer to Application Note AN8002/. OEING INFOMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. 1 *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques eference Manual, SOLEM/. Semiconductor Components Industries, LLC, 2006 November, 2006 ev. 8 1 Publication Order Number: MC10E155/
2 0 a 0 5 a 4 b 4 a 3 b 3 a NC V CCO 0 b 5 b L1 L2 V EE M 0 a Pinout: 28 Lead PLCC (Top View) b 1 a 1 b 2 a 2 b V CCO 0 * All V CC and V CCO pins are tied together on the die V CC 3 2 V CCO Warning: All V CC, V CCO, and V EE pins must be externally connected to Power Supply to guarantee proper operation. Figure Lead Pinout 1 L1 L2 M 1 a 1 b 2 a 2 b 3 a 3 b 4 a 4 b 5 a 5 b Figure 1. Logic iagram Table 1. PIN ESCIPTION 0 a 04 0 b 4 b L1, L2 0 4 M V CC, V CCO V EE NC PIN Table 2. TUTH TABLE H L FUNCTION ECL Input ata a ECL Input ata b ECL ata Select Input ECL Latch Enables ECL Outputs Master eset Positive Supply Negative Supply No Connect ata a b 2
3 Table 3. MAXIMUM ATINGS Parameter Condition 1 Condition 2 ating V CC PECL Mode Power Supply V EE = 0 V 8 V V I PECL Mode Input Voltage NECL Mode Input Voltage V EE = 0 V V CC = 0 V I out Output Current Continuous Surge V I V CC 6 V I V EE 6 T A Operating Temperature ange 0 to +85 C T stg Storage Temperature ange 65 to +150 C JA Thermal esistance (Junction to Ambient) 0 lfpm lfpm JC Thermal esistance (Junction to Case) Standard Board 22 to 26 C/W T sol Wave Solder Pb Pb Free Stresses exceeding Maximum atings may damage the device. Maximum atings are stress ratings only. Functional operation above the ecommended Operating Conditions is not implied. Extended exposure to stresses above the ecommended Operating Conditions may affect device reliability. Table 4. 10E SEIES PECL C CHAACTEISTICS V CCx = 5.0 V, V EE = 0.0 V (Note 1) I EE Power Supply Current ma V OH Output HIGH Voltage (Note 2) mv V OL Output LOW Voltage (Note 2) mv V IH Input HIGH Voltage mv V IL Input LOW Voltage mv I IH Input HIGH Current A I IL Input LOW Current A NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit 1. Input and output parameters vary 1:1 with V CC. V EE can vary 0.46 V / V. 2. Outputs are terminated through a 50 resistor to V CC 2.0 V. Table 5. 10E SEIES NECL C CHAACTEISTICS V CCx = 0.0 V; V EE = 5.0 V (Note 3) I EE Power Supply Current ma V OH Output HIGH Voltage (Note 4) mv V OL Output LOW Voltage (Note 4) mv V IH Input HIGH Voltage mv V IL Input LOW Voltage mv I IH Input HIGH Current A I IL Input LOW Current A NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit 3. Input and output parameters vary 1:1 with V CC. V EE can vary 0.46 V / V. 4. Outputs are terminated through a 50 resistor to V CC 2.0 V. V V ma ma C/W C/W C 3
4 Table E SEIES PECL C CHAACTEISTICS V CCx = 5.0 V; V EE = 0.0 V (Note 5) I EE Power Supply Current ma V OH Output HIGH Voltage (Note 6) mv V OL Output LOW Voltage (Note 6) mv V IH Input HIGH Voltage mv V IL Input LOW Voltage mv I IH Input HIGH Current A I IL Input LOW Current A NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit 5. Input and output parameters vary 1:1 with V CC. V EE can vary 0.46 V / +0.8 V. 6. Outputs are terminated through a 50 resistor to V CC 2.0 V. Table E SEIES NECL C CHAACTEISTICS V CCx = 0 V; V EE = 5.0 V (Note 7) I EE Power Supply Current ma V OH Output HIGH Voltage (Note 8) mv V OL Output LOW Voltage (Note 8) mv V IH Input HIGH Voltage mv V IL Input LOW Voltage mv I IH Input HIGH Current A I IL Input LOW Current A NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit 7. Input and output parameters vary 1:1 with V CC. V EE can vary 0.46 V / +0.8 V. 8. Outputs are terminated through a 50 resistor to V CC 2.0 V. 4
5 Table 8. AC CHAACTEISTICS V CCx = 5.0 V; V EE = 0.0 V or V CCx = 0.0 V; V EE = 5.0 V (Note 9) f MAX Maximum Toggle Frequency MHz t PLH t PHL t s t h Propagation elay to Output Setup Time Hold Time L M t eset ecovery Time t PW Minimum Pulse Width M t SKEW Within-evice Skew (Note 10) t JITTE andom Clock Jitter (MS) < 1 < 1 < 1 t r t f ise/fall Time (20-80%) NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit Series: V EE can vary 0.46 V / V. 100 Series: V EE can vary 0.46 V / +0.8 V. 10. Within-device skew is defined as identical transitions on similar paths through a device river evice Z o = 50 Z o = 50 eceiver evice V TT V TT = V CC 2.0 V Figure 3. Typical Termination for Output river and evice Evaluation (See Application Note AN8020/ Termination of ECL Logic evices.) 5
6 OEING INFOMATION evice Package Shipping MC10E155FN 37 s / ail MC10E155FNG (Pb Free) 37 s / ail MC10E155FN2 / Tape & eel MC10E155FN2G (Pb Free) / Tape & eel MC100E155FN 37 s / ail MC100E155FN2 / Tape & eel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and eel Packaging Specifications Brochure, B8011/. esource eference of Application Notes AN1405/ ECL Clock istribution Techniques AN1406/ esigning with PECL (ECL at +5.0 V) AN1503/ ECLinPS I/O SPiCE Modeling Kit AN1504/ Metastability and the ECLinPS Family AN1568/ Interfacing Between LVS and ECL AN1672/ The ECL Translator Guide AN8001/ Odd Number Counters esign AN8002/ Marking and ate Codes AN8020/ Termination of ECL Logic evices AN8066/ Interfacing with ECLinPS AN8090/ AC s of ECL evices 6
7 PACKAGE IMSIONS FN SUFFIX PLASTIC PLCC PACKAGE CASE ISSUE E N Y BK B U L M Z 28 1 V W X VIEW G (0.250) S T L M S N S Z A H C E K1 G G1 J VIEW S (0.100) T SEATING PLANE K F (0.250) S T L M S N S VIEW S NOTES: 1. ATUMS L, M, AN N ETEMINE WHEE TOP OF LEA SHOULE EXITS PLASTIC BOY AT MOL PATING LINE. 2. IMSION G1, TUE POSITION TO BE MEASUE AT ATUM T, SEATING PLANE. 3. IMSIONS AN U O NOT INCLUE MOL FLASH. ALLOWABLE MOL FLASH IS (0.250) PE SIE. 4. IMSIONING AN TOLEANCING PE ANSI Y14.5M, CONTOLLING IMSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLE THAN THE PACKAGE BOTTOM BY UP TO (0.). IMSIONS AN U AE ETEMINE AT THE OUTEMOST EXTEMES OF THE PLASTIC BOY EXCLUSIVE OF MOL FLASH, TIE BA BUS, GATE BUS AN INTELEA FLASH, BUT INCLUING ANY MISMATCH BETWE THE TOP AN BOTTOM OF THE PLASTIC BOY. 7. IMSION H OES NOT INCLUE AMBA POTUSION O INTUSION. THE AMBA POTUSION(S) SHALL NOT CAUSE THE H IMSION TO BE GEATE THAN (0.940). THE AMBA INTUSION(S) SHALL NOT CAUSE THE H IMSION TO BE SMALLE THAN (0.635). INCHES MILLIMETES IM MIN MAX MIN MAX A B C E F G BSC 1.27 BSC H J K U V W X Y Z G K
8 ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION OEING INFOMATION LITEATUE FULFILLMT: Literature istribution Center for ON Semiconductor P.O. Box 5163, enver, Colorado USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales epresentative MC10E155/
9 Mouser Electronics Authorized istributor Click to View Pricing, Inventory, elivery & Lifecycle Information: ON Semiconductor: MC10E155FN MC10E155FN2
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