ORDERING INFORMATION Figure 1. Pinout: 20 Lead Packages Conductors (Top View) PIN ASSIGNMENT

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Richard Caldwell
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1 The MC74AC574/74ACT574 is a high speed, low power octal flip flop with a buffered common Clock (CP) and a buffered common Output Enable (OE). The information presented to the D inputs is stored in the flip flops on the LOW to HIGH Clock (CP) transition. The MC74AC574/74ACT574 is functionally identical to the MC74AC374/74ACT374 except for the pinouts. Inputs and Outputs on Opposite Sides of Package Allowing Easy Interface with Microprocessors Useful as Input or Output Port for Microprocessors Functionally Identical to MC74AC374/74ACT374 3-State Outputs for Bus-Oriented Applications Outputs Source/Sink 24 ma ACT574 Has TTL Compatible Inputs PDIP 20 N SUFFIX CASE 738 SO 20 DW SUFFIX CASE 751 TSSOP 20 DT SUFFIX CASE 948E EIAJ 20 M SUFFIX CASE ORDERING INFORMATION Figure 1. Pinout: 20 Lead Packages Conductors (Top iew) Device Package Shipping MC74AC574N PDIP s/rail MC74ACT574N PDIP s/rail MC74AC574DW SOIC s/rail MC74AC574DWR2 SOIC Tape & Reel PIN ASSIGNMENT PIN FUNCTION D0 D7 Data Inputs CP Clock Pulse Input OE 3 State Output Enable Input O0 O7 3 State Outputs MC74ACT574DW SOIC s/rail MC74ACT574DWR2 SOIC Tape & Reel MC74AC574DT TSSOP s/rail MC74AC574DTR2 TSSOP Tape & Reel MC74ACT574DT TSSOP s/rail MC74ACT574DTR2 TSSOP Tape & Reel MC74AC574M EIAJ s/rail MC74AC574MEL EIAJ Tape & Reel MC74ACT574M EIAJ s/rail MC74ACT574MEL EIAJ Tape & Reel DEICE MARKING INFORMATION See general marking information in the device marking section on page 8 of this data sheet. Semiconductor Components Industries, LLC, 2001 May, 2001 Rev. 6 1 Publication Order Number: MC74AC574/D

2 Figure 2. Logic Symbol FUNCTIONAL DESCRIPTION The MC74AC574/74ACT574 consists of eight edgetriggered flip flops with individual D type inputs and 3 state true outputs. The buffered clock and buffered Output Enable are common to all flip flops. The eight flip flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW to HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip flops. FUNCTION TABLE Inputs Internal Outputs OE CP D Q On Function H H L NC Z Hold H H H NC Z Hold H L L Z Load H H H Z Load L L L L Data Available L H H H Data Available L H L NC NC No Change in Data L H H NC NC No Change in Data H = HIGH oltage Level L = LOW oltage Level X = Immaterial Z = High Impedance = LOW-to-HIGH Clock Transition NC = No Change NOTE: This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Figure 3. Logic Diagram MAXIMUM RATINGS* Symbol Parameter alue CC DC Supply oltage (Referenced to GND) 0.5 to +7.0 IN DC Input oltage (Referenced to GND) 0.5 to CC +0.5 OUT DC Output oltage (Referenced to GND) 0.5 to CC +0.5 IIN DC Input Current, per Pin ±20 ma IOUT DC Output Sink/Source Current, per Pin ±50 ma ICC DC CC or GND Current per Output Pin ±50 ma Tstg Storage Temperature 65 to +150 C * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. 2

3 RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Typ Max CC Supply oltage AC ACT IN, OUT DC Input oltage, Output oltage (Ref. to GND) 0 CC Input Rise and Fall Time (Note 1) tr, tf AC Devices except Schmitt Inputs tr, tf ns/ Input Rise and Fall Time (Note 2) ACT Devices except Schmitt Inputs TJ Junction Temperature (PDIP) 140 C TA Operating Ambient Temperature Range C IOH Output Current High 24 ma IOL Output Current Low 24 ma 1. IN from 30% to 70% CC; see individual Data Sheets for devices that differ from the typical input rise and fall times. 2. IN from 0.8 to 2.0 ; see individual Data Sheets for devices that differ from the typical input rise and fall times. ns/ 3

4 DC CHARACTERISTICS Symbol Parameter CC () 74AC TA = +25 C Typ 74AC TA = 40 C to +85 C Guaranteed Limits Conditions IH Minimum High Level OUT = 0.1 Input oltage or CC IL Maximum Low Level OUT = 0.1 Input oltage or CC OH Minimum High Level IOUT = 50 µa Output oltage *IN = IL or IH ma IOH 24 ma ma OL Maximum Low Level IOUT = 50 µa Output oltage IININ Maximum Input Leakage Current *IN = IL or IH ma IOL 24 ma ma 5.55 ±0.1 1 ±1.0 0 µa I = CC, GND IOLD Minimum Dynamic ma OLD = 1.65 Max IOHD Output Current ma OHD = 3.85 Min ICC Maximum Quiescent Supply Current µa IN = CC or GND * All outputs loaded; thresholds on input associated with output under test. Maximum test duration 2.0 ms, one output loaded at a time. NOTE: Note: IIN and 3.0 are guaranteed to be less than or equal to the respective 5.5 CC. 4

5 AC CHARACTERISTICS (For Figures and Waveforms See Section 3) Symbol Parameter CC* () 74AC TA = +25 C 74AC TA = 40 C to +85 C Min Typ Max Min Max fmax Maximum Clock Frequency tplh Propagation Delay CP to On Propagation Delay tphl CP to On Fig. No. MHz 3 3 ns 3 6 ns 3 6 tpzh tpzl tphz tplz Output Enable Time Output Enable Time Output Disable Time Output Disable Time * oltage Range 3.3 is 3.3 ±0.3. oltage Range 5.0 is 5.0 ± ns 3 7 ns 3 8 ns 3 7 ns 3 8 AC OPERATING REQUIREMENTS Symbol Parameter CC* () Typ 74AC TA = +25 C 74AC TA = 40 C to +85 C Guaranteed Minimum Setup Time, HIGH or LOW ts Dn to CP Hold Time, HIGH or LOW th Dn to CP CP Pulse Width tw HIGH or LOW Fig. No. ns 3 9 ns 3 9 ns 3 6 *oltage Range 3.3 is 3.3 ±0.3. oltage Range 5.0 is 5.0 ±0.5. 5

6 DC CHARACTERISTICS Symbol Parameter CC () 74ACT TA = +25 C Typ 74ACT TA = 40 C to +85 C Guaranteed Limits IH Minimum High Level e Input oltage IL Maximum Low Level e Input oltage OH Minimum High Level e Output oltage Conditions OUT = 0.1 or CC 0.1 OUT = 0.1 or CC 0.1 IOUT = 50 µa OL Maximum Low Level e Output oltage *IN = IL or IH 24 ma IOH 24 ma IOUT = 50 µa IIN Maximum Input Leakage Current *IN = IL or IH 24 ma IOL 24 ma 5.55 ±0.1 1 ±1.0 0 µa I = CC, GND ICCT Additional Max. ICC/Input ma I = CC 2.1 IOZ Maximum I (OE) = IL, IH 3-State 5.5 ±0.5 ±5.0 µa I = CC, GND Current O = CC, GND IOLD IOHD ICC Minimum Dynamic Output t Current Maximum Quiescent Supply Current *All outputs loaded; thresholds on input associated with output under test. Maximum test duration 2.0 ms, one output loaded at a time ma OLD = 1.65 Max ma OHD = 3.85 Min µa IN = CC or GND AC CHARACTERISTICS (For Figures and Waveforms See Section 3) Symbol fmax tplh tphl Maximum Clock Frequency Propagation Delay CP to On Propagation Delay CP to On Parameter CC* () 74ACT TA = +25 C 74ACT TA = 40 C to +85 C Min Typ Max Min Max Fig. No ns ns ns 3 6 tpzh Output Enable Time ns 3 7 tpzl Output Enable Time ns 3 8 tphz Output Disable Time ns 3 7 tplz Output Disable Time ns 3 8 *oltage Range 5.0 is 5.0 ±0.5. 6

7 AC OPERATING REQUIREMENTS ts th tw Symbol Parameter Setup Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP CP Pulse Width HIGH or LOW *oltage Range 3.3 is 3.3 ±0.3. oltage Range 5.0 is 5.0 ±0.5. CC* () Typ 74ACT TA = +25 C 74ACT TA = 40 C to +85 C Guaranteed Minimum Fig. No ns ns ns 3 6 CAPACITANCE Symbol Parameter alue Typ Test Conditions CIN Input Capacitance 4.5 pf CC = 5.0 CPD Power Dissipation Capacitance 40 pf CC = 5.0 7

8 MARKING DIAGRAMS PDIP 20 SO 20 TSSOP 20 EIAJ 20 MC74AC574N AWLYYWW AC574 AWLYYWW AC 574 ALYW 74AC574 AWLYWW MC74ACT574N AWLYYWW ACT574 AWLYYWW ACT 574 ALYW 74ACT574 AWLYWW A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week 8

9 PACKAGE DIMENSIONS PDIP 20 N SUFFIX 20 PIN PLASTIC DIP PACKAGE CASE ISSUE E T G E A F B K N D 20 PL C L M J 20 PL SO 20 DW SUFFIX 20 PIN PLASTIC SOIC PACKAGE CASE 751D 05 ISSUE F D A H 10X E h X 45 20X B 18X e B A A1 T C L 9

10 PACKAGE DIMENSIONS TSSOP 20 DT SUFFIX 20 PIN PLASTIC TSSOP PACKAGE CASE 948E 02 ISSUE A L 2X L/2 PIN 1 IDENT C T 20X K REF A D G H B U J J1 N N K K1 ÍÍÍ ÍÍÍ SECTION N N F DETAIL E DETAIL E M W e Z b D E A HE A1 EIAJ 20 M SUFFIX 20 PIN PLASTIC EIAJ PACKAGE CASE ISSUE O IEW P M LE L DETAIL P Q1 c 10

11 Notes 11

12 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada ONlit@hibbertco.com N. American Technical Support: Toll Free USA/Canada JAPAN: ON Semiconductor, Japan Customer Focus Center Nishi Gotanda, Shinagawa ku, Tokyo, Japan Phone: r14525@onsemi.com ON Semiconductor Website: For additional information, please contact your local Sales Representative. 12 MC74AC574/D

ORDERING INFORMATION Figure 1. Pinout: 20 Lead Packages Conductors (Top View) PIN ASSIGNMENT

ORDERING INFORMATION Figure 1. Pinout: 20 Lead Packages Conductors (Top View) PIN ASSIGNMENT The MC74AC273/74ACT273 has eight edge-triggered D type flip flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip flops