Octal 3-State Noninverting Transparent Latch High-Performance Silicon-Gate CMOS

Transcription

1 TECHNICAL DATA IN74HCT573A Octal 3-State Noninverting Transparent Latch High-Performance Silicon-Gate CMOS The IN74HCT573A is identical in pinout to the LS/ALS573. This device may be used as a level converter for interfacing TTL or NMOS outputs to High-Speed CMOS inputs. These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes low, data meeting the setup and hold time becomes latched. The Output Enable input does not affect the state of the latches, but when Output Enable is high, all device outputs are forced to the high-impedance state. Thus, data may be latched even when the outputs are not enabled. TTL/NMOS-Compatible Input Levels Outputs Directly Interface to CMOS, NMOS, and TTL Operating oltage Range: to Low Input Current: 1.0 μa ORDERING INFORMATION IN74HCT573AN Plastic IN74HCT573ADW SOIC TA = -55 to 125 C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE PIN 20=CC PIN 10 = GND Output Enable Inputs Latch Enable D Output Q L H H H L H L L L L X no change H X X Z X = don t care Z = high impedance 1

2 MAXIMUM RATINGS * Symbol Parameter alue Unit CC DC Supply oltage (Referenced to GND) -0.5 to +7.0 IN DC Input oltage (Referenced to GND) -1.5 to CC +1.5 OUT DC Output oltage (Referenced to GND) -0.5 to CC +0.5 IIN DC Input Current, per Pin ±20 ma IOUT DC Output Current, per Pin ±35 ma ICC DC Supply Current, CC and GND Pins ±75 ma PD Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Tstg Storage Temperature -65 to +150 C TL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mw/ C from 65 to 125 C SOIC Package: : - 7 mw/ C from 65 to 125 C mw 260 C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit CC DC Supply oltage (Referenced to GND) IN, OUT DC Input oltage, Output oltage (Referenced to GND) 0 CC TA Operating Temperature, All Package Types C tr, tf Input Rise and Fall Time (Figure 1) ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, IN and OUT should be constrained to the range GND (IN or OUT) CC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or CC). Unused outputs must be left open. 2

3 DC ELECTRICAL CHARACTERISTICS(oltages Referenced to GND) Symbol Parameter Test Conditions 25 C to IH Minimum High- Level Input oltage IL Maximum Low - Level Input oltage OH Minimum High- Level Output oltage OUT= or CC- IOUT 20 μa OUT= or CC- IN=IH or IL CC 85 C 125 C Unit IN=IH or IL IOUT 6.0 ma OL Maximum Low- Level Output oltage IN= IL or IH IIN IOZ ICC ΔICC Maximum Input Leakage Current Maximum Three State Leakage Current Maximum Quiescent Supply Current (per Package) Additional Quiescent Supply Current IN= IL or IH IOUT 6.0 ma IN=CC or GND ± ±1.0 ±1.0 μa Output in High-Impedance State IN =IH or IL OUT=CC or GND IN=CC or GND IOUT=0μA IN=2.4, Any One Input IN=CC or GND, Other Inputs ±0.5 ±5.0 ±10 μa μa 25 C to 125 C IOUT=0μA ma 3

4 AC ELECTRICAL CHARACTERISTICS(CC =5.0 ± 10%, CL=50pF,Input tr=tf=6.0 ns) Symbol Parameter 25 C to tplh, tphl tplh, tphl tplz, tphz tpzh, tpzl ttlh, tthl Maximum Propagation Delay, Input D to Q (Figures 1 and 5) Maximum Propagation Delay,Latch Enable to Q (Figures 2 and 5) Maximum Propagation Delay, Output Enable to Q (Figures 3 and 6) Maximum Propagation Delay, Output Enable to Q (Figures 3 and 6) Maximum Output Transition Time, Any Output (Figures 1 and 5) 85 C 125 C Unit ns ns ns ns ns CIN Maximum Input Capacitance pf Maximum Three-State Output Capacitance pf (Output in High-Impedance State) COUT CPD Power Dissipation Capacitance (Per Enabled Output) Used to determine the no-load dynamic power consumption: PD=CPDCC 2 f+icccc C,CC= pf TIMING REQUIREMENTS (CC =5.0 ± 10%, CL=50pF,Input tr=tf=6.0 ns) Symbol Parameter 25 C to 85 C 125 C Unit tsu Minimum Setup Time, Input ns D to Latch Enable (Figure 4) th Minimum Hold Time, Latch ns Enable to Input D (Figure 4) tw Minimum Pulse Width, Latch ns Enable (Figure 2) tr, tf Maximum Input Rise and Fall Times (Figure 1) ns 4

5 Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms Figure 4. Switching Waveforms EXPANDED LOGIC DIAGRAM Figure 5. Test Circuit Figure 6. Test Circuit 5