3.3V CMOS 16-BIT TRANS- PARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND BUS-HOLD
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1 3.3V CMOS 16-BIT TRANS- PARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND BUS-HOLD IDT74ALVCH FEATURES: 0.5 MICRON CMOS Technology Typical tsk(o) (Output Skew) < 250ps ESD > 200 per MIL-STD-883, Method 3015; > 20 using machine model (C = 200pF, R = 0) = 3.3V ± 0.3V, Normal Range = 2.7V to 3.6V, Extended Range = 2.5V ± 0.2V CMOS power levels (0.4μ W typ. static) Rail-to-Rail output swing for increased noise margin Available in SSOP and TSSOP packages DRIVE FEATURES: Balanced Output Drivers: ±12mA Low switching noise APPLICATIONS: 3.3V high speed systems 3.3V and lower voltage computing systems DESCRIPTION: This 16-bit transparent D-type latch is built using advanced dual metal CMOS technology. The ALVCH is particularly suitable for imple-menting buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit latches or one16-bit latch. When the latch enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs. A buffered output-enable (OE) can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be enetered while the outputs are in the high-impedance state. The ALVCH has series resistors in the device output structure which will significantly reduce line noise when used with light loads. This driver has been designed to drive ±12mA at the designated threshold levels. The ALVCH has bus-hold which retains the inputs last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistor. FUNCTIONAL BLOCK DIAGRAM 1OE 1 2OE 24 1LE 48 2LE 25 1D1 47 C1 1D 2 1Q1 2D1 36 C1 1D 13 2Q1 TO 7 OTHER CHANNELS TO 7 OTHER CHANNELS IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 1 JUNE Integrated Device Technology, Inc. DSC-4575/7
2 PIN CONFIGURATION 1OE 1 1Q1 2 1Q2 1Q Q4 6 1Q Q Q LE 1D1 1D2 1D3 1D4 1D5 1D6 1D7 ABSOLUTE MAXIMUM RATINGS (1) Symbol Description Max Unit ERM (2) Terminal Voltage with Respect to 0.5 to +4.6 V ERM (3) Terminal Voltage with Respect to 0.5 to +0.5 V TSTG Storage Temperature 65 to +150 C IOUT DC Output Current 50 to +50 ma IIK Continuous Clamp Current, ±50 ma VI < 0 or VI > IOK Continuous Clamp Current, VO < 0 50 ma ICC Continuous Current through each ±100 ma ISS or 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. terminals. 3. All terminals except. 1Q D8 CAPACITANCE (TA = +25 C, F = 1.0MHz) 2Q1 2Q2 2Q3 2Q D1 2D2 2D3 2D4 Symbol Parameter (1) Conditions Typ. Max. Unit CIN Input Capacitance VIN = 5 7 pf COUT Output Capacitance VOUT = 7 9 pf CI/O I/O Port Capacitance VIN = 7 9 pf 1. As applicable to the device type. 2Q5 2Q6 2Q7 2Q8 2OE D5 2D6 2D7 2D8 2LE PIN DESCRIPTION Pin Names Description xdx Data Inputs (1) xle x Q x xoe Latch Enable Inputs 3-State Outputs 3-State Output Enable Input (Active LOW) 1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os. SSOP/ TSSOP TOP VIEW FUNCTION TABLE (EACH 8-BIT SECTION) (1) Inputs Outputs xoe xle xdx xqx L H H H L H L L H X X Z L L X Q (2) o 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don t Care Z = High Impedance 2. Output level before the indicated steady-state input conditions were established. 2
3 DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 40 C to +85 C Symbol Parameter Test Conditions Min. Typ. (1) Max. Unit Input HIGH Voltage Level = 2.3V to 2.7V 1.7 V = 2.7V to 3.6V 2 VIL Input LOW Voltage Level = 2.3V to 2.7V 0.7 V = 2.7V to 3.6V 0.8 IIH Input HIGH Current = 3.6V VI = ±5 μa IIL Input LOW Current = 3.6V VI = ±5 μa IOZH High Impedance Output Current = 3.6V VO = ±10 μa IOZL (3-State Output pins) VO = ±10 VIK Clamp Diode Voltage = 2.3V, IIN = 18mA V VH Input Hysteresis = 3.3V 100 mv ICCL Quiescent Power Supply Current = 3.6V μa ICCH VIN = or ICCZ ΔICC Quiescent Power Supply Current One input at - 0.6V, other inputs at or 750 μa Variation 1. Typical values are at = 3.3V, +25 C ambient. BUS-HOLD CHARACTERISTICS Symbol Parameter (1) Test Conditions Min. Typ. (2) Max. Unit IBHH Bus-Hold Input Sustain Current = 3V VI = 2V 75 μa IBHL VI = 0.8V 75 IBHH Bus-Hold Input Sustain Current = 2.3V VI = 1.7V 45 μa IBHL VI = 0.7V 45 IBHHO Bus-Hold Input Overdrive Current = 3.6V VI = 0 to 3.6V ±500 μa IBHLO 1. Pins with Bus-Hold are identified in the pin description. 2. Typical values are at = 3.3V, +25 C ambient. 3
4 OUTPUT DRIVE CHARACTERISTICS Symbol Parameter Test Conditions (1) Min. Max. Unit Output HIGH Voltage = 2.3V to 3.6V IOH = 0.1mA 0.2 V = 2.3V IOH = 4mA 1.9 IOH = 6mA 1.7 = 2.7V IOH = 4mA 2.2 IOH = 8mA 2 = 3V IOH = 6mA 2.4 IOH = 12mA 2 Output LOW Voltage = 2.3V to 3.6V IOL = 0.1mA 0.2 V = 2.3V IOL = 4mA 0.4 IOL = 6mA 0.55 = 2.7V IOL = 4mA 0.4 IOL = 8mA 0.6 = 3V IOL = 6mA 0.55 IOL = 12mA and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate range. TA = 40 C to + 85 C. OPERATING CHARACTERISTICS, TA = 25 C = 2.5V ± 0.2V = 3.3V ± 0.3V Symbol Parameter Test Conditions Typical Typical Unit CPD Power Dissipation Capacitance Outputs enabled CL = 0pF, f = 10Mhz pf CPD Power Dissipation Capacitance Outputs disabled 4 5 SWITCHING CHARACTERISTICS (1) = 2.5V ± 0.2V = 2.7V = 3.3V ± 0.3V Symbol Parameter Min. Max. Min. Max. Min. Max. Unit tplh Propagation Delay ns tphl xdx to xqx tplh Propagation Delay ns tphl xle to xqx tpzh Output Enable Time ns tpzl xoe to xqx tphz Output Disable Time ns tplz xoe to xqx tsu Setup Time, data before LE ns th Hold Time, data after LE ns tw Pulse Duration, LE HIGH or LOW ns tsk(o) Output Skew (2) 500 ps 1. See TEST CIRCUITS AND WAVEFORMS. TA = 40 C to + 85 C. 2. Skew between any two outputs of the same package and switching in the same direction. 4
5 TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS Symbol (1) = 3.3V±0.3V (1) = 2.7V (2) = 2.5V±0.2V Unit VLOAD x Vcc V Vcc V Vcc / 2 V VLZ mv VHZ mv CL pf SAME PHASE TRANSITION OUTPUT OPPOSITE PHASE TRANSITION tplh tplh Propagation Delay tphl tphl (1, 2) Pulse Generator VIN OUTPUT 1 OUTPUT 2 RT D.U.T. tplh1 tplh2 VOUT tsk (x) CL Test Circuit for All Outputs tphl1 tphl2 500Ω 500Ω DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. 1. Pulse Generator for All Pulses: Rate 1.0MHz; tf 2.5ns; tr 2.5ns. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tf 2ns; tr 2ns. SWITCH POSITION Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests tsk (x) tsk(x) = tplh2 - tplh1 or tphl2 - tphl1 Output Skew - tsk(x) Switch VLOAD 1. For tsk(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tsk(b) OUTPUT1 and OUTPUT2 are in the same bank. Open VLOAD Open 5 CONTROL OUTPUT SWITCH NORMALLY CLOSED LOW OUTPUT NORMALLY HIGH DATA TIMING ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL ENABLE LOW-HIGH-LOW PULSE HIGH-LOW-HIGH PULSE tpzl tpzh SWITCH OPEN VLOAD/2 tsu tsu tphz trem tw DISABLE th tplz th VLOAD/2 + VLZ - VHZ Enable and Disable Times 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. Set-up, Hold, and Release Times Pulse Width
6 ORDERING INFORMATION XX ALVC X XX XXX XX X Temp. Range Bus-Hold Family Device Type Package Blank 8 Tube Tape and Reel PVG PAG Shrink Small Outline Package - Green Thin Shrink Small Outline Package - Green Bit Transparent D-Type Latch with 3-State Outputs 162 Double-Density with Resistors, ±12mA H Bus-Hold C to +85 C DATASHEET DOCUMENT HISTORY 06/15/2016 Pg. 6 Updated the ordering information by adding Tape and Reel. CORPORATE HEADQUARTERS for SALES: for Tech Support: 6024 Silver Creek Valley Road or logichelp@idt.com San Jose, CA fax:
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