PO74G16240A. Pin Configuration. Logic Block Diagram. Truth Table. 74 Series Noise Cancellation GHz Logic DESCRIPTION: FEATURES:
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1 FEATURES:. Patented technology. Operating frequency up to.25ghz with 2pf load. Operating frequency up to 700MHz with 5pf load. Operating frequency up to 300MHz with 5pf load. Operating frequency up to 00MHz with 50pf load. Operates from.65v to 3.6V. Propagation delay <.5ns max with 5pf load. Low input capacitance: 4pf typical. Available in pin TSSOP package DESCRIPTION: Potato Semiconductor s is designed for world top performance using submicron CMOS technology to achieve.25ghz TTL /CMOS output frequency with less than.5ns propagation delay. This Octal bus buffer gate is designed for.65-v to 3.6-V operation. The features independent line driver swith 3-state outputs. Each output is disabled when the associated output- enable(oe) input is high. s can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in a mixed 3.3V/5V system environment. Pin Configuration Logic Block Diagram OE Y OE A OE A 47 2 Y 25 3OE 3A Y Y2 Y A2 A3 A2 A Y2 Y3 3A2 3A Y2 6 3Y3 Y A4 A Y4 3A Y4 2Y 8 4 2A 2Y2 2Y A2 2A3 2OE 2A 4 8 2Y 24 4OE 4A Y 2Y4 3Y 3Y A4 3A 3A2 2A2 2A Y2 2Y3 4A2 4A Y2 22 4Y3 3Y A3 2A Y4 4A Y4 3Y A4 4Y 4Y A 4A2 Truth Table 4Y3 4Y4 4OE A3 4A4 3OE noe s nax Outpu ts nyx L L H L H L H X Z 0/0/0
2 Maximum Ratings Description Max Unit Storage Temperature -65 to 50 C Operation Temperature -40 to 25 C Operation Voltage -0.5 to +4.6 V Voltage -0.5 to +5.5 V Output Voltage -0.5 to Vcc+0.5 V Note: stresses greater than listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability specification is not implied. DC Electrical Characteristics Symbol Description Test Conditions Min Typ Max Unit VOH Output High voltage Vcc=3V Vin=VIH or VIL, IOH= -2mA V VOL Output Low voltage Vcc=3V Vin=VIH or VIL, IOH=2mA V VIH High voltage Guaranteed Logic HIGH Level ( Pin) V VIL Low voltage Guaranteed Logic LOW Level ( Pin) V IIH High current Vcc = 3.6V and Vin = 5.5V - - ua IIL Low current Vcc = 3.6V and Vin = 0V ua VIK Clamp diode voltage Vcc = Min. And IIN = -8mA V. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 3.3V, 25 C ambient. 3. This parameter is guaranteed but not tested. 4. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 5. VoH = Vcc 0.6V at rated current 2 0/0/0
3 Power Supply Characteristics Symbol Description Test Conditions () Min Typ Max Unit IccQ Quiescent Power Supply Current Vcc=Max, Vin=Vcc or ua Icc Power Supply Current per High Vcc=Max, Vin= Vcc-0.6V ua. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 3.3V, 25 C ambient. 3. This parameter is guaranteed but not tested. 4. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 5. VoH = Vcc 0.6V at rated current Capacitance Parameters () Description Test Conditions Typ Unit Cin Capacitance Vin = 0V 4 pf Cout Output Capacitance Vout = 0V 6 pf This parameter is determined by device characterization but not production tested. Switching Characteristics Symbol Description Test Conditions () Max Unit tplh Propagation Delay A to Y CL = 5pF.5 ns tphl Propagation Delay A to Y CL = 5pF.5 ns tpzh or tpzl Output Enable Time CL = 5pF 2.5 ns tphz or tplz tr/tf Rise/Fall Time 0.8V 2.0V 0.8 ns Output Disable Time CL = 5pF 2.5 ns CL = 50 pf 00 MHz CL =5pF 300 MHz CL = 5pF 750 MHz CL = 2pF 25 MHz. See test circuits and waveforms. 2. tplh, tphl, tsk(p), and tsk(o) are production tested. All other parameters guaranteed but not production tested. 3. Airflow of m/s is recommended for frequencies above 33MHz 3 0/0/0
4 Test Waveforms Test Circuit 500Ohm 50Ohm 50Ohm 500Ohm 4 0/0/0
5 Packaging Mechanical Drawing: pin TSSOP Max X.XX X.XX DENOTES DIMENSIONS IN MILLIMETERS IC Ordering Information Ordering Code Package Top-Marking T A SU for Tube pin TSSOP Pb-free & Green POTATO74G6240AS -40 C to 85 C SR for Tape & Reel pin TSSOP Pb-free & Green POTATO74G6240AS -40 C to 85 C IC Package Information PACKAGE CODE PACKAGE TYPE TAPE WIDTH (mm) TAPE PITCH (mm) PIN LOCATION TAPE TRAILER LENGTH QTY PER REEL TAPE LEADER LENGTH T TSSOP 24 2 Top Left Corner 26 (2 ) (20 ) 39 QTY PER TUBE 5 0/0/0
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ORDERING INFORMATION PACKAGE
Member of Texas Instruments Widebus Family Latch-Up Performance Exceeds 250 ma Per JESD 17 ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) Bus Hold on Data
74ACT11374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
Eight D-Type Flip-Flops in a Single Package -State Bus Driving True s Full Parallel Access for Loading Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and
SN54HC365, SN74HC365 HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
High-Current -State s Drive Bus Lines, Buffer Memory Address Registers, or Drive up to LSTTL Loads True s Package Options Include Plastic Small-Outline (D) and Ceramic Flat (W) Packages, Ceramic Chip Carriers
8-Bit Bidirectional Universal Shift Register with Parallel I/O High-Speed Silicon-Gate CMOS
TECHNICAL ATA IN74AC323 8-Bit Bidirectional Universal Shift Register with Parallel I/O High-Speed Silicon-Gate CMOS The IN74AC323 is identical in pinout to the LS/ALS323, HC/HCT323. The device inputs are
SN5407, SN5417, SN7407, SN7417 HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS SDLS032A DECEMBER 1983 REVISED NOVEMBER 1997
Converts TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays s Fully Compatible With Most TTL Circuits
SN75158 DUAL DIFFERENTIAL LINE DRIVER
SN78 Meets or Exceeds the Requirements of ANSI EIA/TIA--B and ITU Recommendation V. Single -V Supply Balanced-Line Operation TTL Compatible High Output Impedance in Power-Off Condition High-Current Active-Pullup
CD74HCT4514, CD74HCT LINE TO 16-LINE DECODERS/DEMULTIPLEXERS WITH INPUT LATCHES
4.5-V to 5.5-V V CC Operation Fanout (Over Temperature Range) Standard s... 0 LSTTL Loads Bus-Driver s... 5 LSTTL Loads Wide Operating Temperature Range of 55 C to 25 C Balanced Propagation Delays and
SN54ALS00A, SN54AS00, SN74ALS00A, SN74AS00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES
Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description These devices contain four independent 2-input positive-nand
PI3B V, Synchronous 16-Bit to 32-Bit FET Mux/DeMux NanoSwitch. Description. Features. Pin Configuration. Block Diagram.
PI363 3.3, Synchronous 6-it to 3-it FET Mux/DeMux NanoSwitch Features Near-Zero propagation delay. Ω Switches Connect etween Two Ports Packaging: - -pin 40mil Wide Thin Plastic TSSOP (A) - -pin 300mil
SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve
SN54AS825A, SN74AS825A 8-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS020B JUNE 1984 REVISED AUGUST 1995
Functionally Equivalent to AMD s AM2982 Improved I OH Specificatio Multiple Output Enables Allow Multiuser Control of the Interface Outputs Have Undershoot-Protection Circuitry Power-Up High-Impedance
SN5407, SN5417, SN7407, SN7417 HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
Converts TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays s Fully Compatible With Most TTL Circuits
PI5C Bit, 2-Port Bus Switch. Features. Description. Pin Configuration. Block Diagram. Pin Description. Truth Table (1) Pin Name Description
Features ÎÎNear-Zero propagation delay ÎÎ5-ohm switches connect inputs to outputs ÎÎDirect bus connection when switches are on ÎÎUltra Low Quiescent Power (0.2μA typical) Ideally suited for notebook applications
SN54ALS08, SN54AS08, SN74ALS08, SN74AS08 QUADRUPLE 2-INPUT POSITIVE-AND GATES
SNALS0, SNAS0, SN7ALS0, SN7AS0 Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description These devices contain
Description D2+A D2-A D3+A D3-A D0+B D0-B D1+B D1-B D2+B D2-B D3+B D3-B AUX+ A AUX- A HPD A CAB_DETA/LEDA AUX+ B AUX- B HPD B CAB_DETB/LEDB
High Bandwidth 6-differential Channel, 1:2 Demux Features 4 Differential Channel, 1:2 DeMux that will support 2.7Gbps DP rev 1.1a signals 1-channel 1:2 demux for DP_HPD signal 1-differential channel 1:2
1OE 3B V GND ORDERING INFORMATION. TOP-SIDE MARKING QFN RGY Tape and reel SN74CBTLV3126RGYR CL126 PACKAGE
SN74CBTLV326 LOW-VOLTAGE QUADRUPLE FET BUS SWITCH SCDS03H DECEMBER 997 REVISED APRIL 2003 Standard 26-Type Pinout 5-Ω Switch Connection Between Two Ports Isolation Under Power-Off Conditions Latch-up Performance
PI3VeDP212 2-lane DisplayPort Switch/Mux for DP Driven Panels with Triple Control Pins
Features 2 Differential Channel, 2:1 mux/demux that will support 2.7Gbps or 1.62Gbps DP signals 1-differential channel is used for AUX signaling Insertion Loss for high speed channels @ 2.7 Gbps: -1.5dB
SN54ALS873B, SN54AS873A, SN74ALS873B, SN74AS873A DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS036D APRIL 1982 REVISED AUGUST 1995
3-State Buffer-Type Outputs Drive Bus Lines Directly Bus-Structured Pinout Package Optio Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs
PI3C3126. Description. Features. 14-Pin Configuration. Applications. Block Diagram. 16-Pin Configuration. Truth Table (1) Pin Description.
2./3.3, High Bandwidth, Hot Insertion,4-Bit, 2-Port Bus Switch with Individual Enables Features Near-Zero propagation delay -ohm switches connect inputs to outputs High Bandwidth (>400 MHz) 2./3.3 Supply
ORDERING INFORMATION PACKAGE
Member of Texas Instruments Widebus Family State-of-the-Art Advanced Low-Voltage BiCMOS (ALB) Technology Design for.-v Operation Schottky Diodes on All s to Eliminate Overshoot and Undershoot Industry
PI5C3384 PI5C3384C PI5C32384 (25Ω)
PI5C3384 PI5C3384C PI5C32384 (25Ω) 0-Bit, 2-Port Bus Switch Features: Near-Zero propagation delay Low noise, 25Ω version (PI5C32384) 5Ω switches connect inputs to outputs (PI5C3384) Direct bus connection
PI3USB V USB 3.0 SuperSpeed Dual 2:1 Mux/DeMux Switch with Enable. Description. Features. Application Routing USB 3.0 SuperSpeed signals.
Features Dual 2:1 USB 3.0 Switch Bi-directional Operation 5 Gbps Performance Very high -3 db bandwidth: 8.2 GHz Low Insertion Loss: -1dB @ 2.5 GHz Excellent Return Loss: -29 db @ 2.5 GHz Low Crosstalk:
SN54ALS873B, SN54AS873A, SN74ALS873B, SN74AS873A DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS036D APRIL 1982 REVISED AUGUST 1995
3-State Buffer-Type Outputs Drive Bus Lines Directly Bus-Structured Pinout Package Optio Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs
CDC LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS442B FEBRUARY 1994 REVISED NOVEMBER 1995
Low Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation pplications Operates at 3.3-V LVTTL-Compatible Inputs and s Supports Mixed-Mode Signal Operation (-V Input and Voltages With 3.3-V )
SN74ALVCH V 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
Member of the Texas Instruments Widebus Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 200 Per MIL-STD-883, Method 3015; Exceeds 20 Using Machine Model (C =
PI3V514. Low On-Resistance, 3.3V High-Bandwidth 5-port, 4:1 Mux/DeMux VideoSwitch. Description. Features. Pin Configuration.
Features Near-Zero propagation delay 5Ω switches connect inputs to outputs High signal passing bandwidth (400 MHz) Beyond Rail-to-Rail switching 5V I/O tolerant with 3.3V supply 2.5V and 3.3V supply voltage
PI3VDP Lane DisplayPort Rev 1.2 Compliant Switch. Description. Features. Application. Block Diagram
Features ÎÎ2-lane, 1:2 mux/demux that will support RBR, HBR1, or HBR2 ÎÎ1-channel 1:2 mux/demux for DP_HPD signal ÎÎ1-differential channel 1:2 mux/demux for DP_Aux signal with support up to 720Mbps ÎÎInsertion
PI5C3253. Dual 4:1 Mux/DeMux Bus Switch
Features Near-Zero propagation delay 5Ω switches connect inputs to outputs Direct bus connection when switches are ON Ultra Low Quiescent Power (0.2µA typical) Ideally suited for notebook applications
FAST CMOS 1-TO-10 CLOCK DRIVER
Integrated Device Technology, Inc. FAST CMOS 1-TO-10 CLOCK DRIVER IDT54/74FCT807BT/CT FEATURES: 0.5 MICRON CMOS Technology Guaranteed low skew < 250ps (max.) Very low duty cycle distortion < 350ps (max.)