AM26LS31 QUADRUPLE DIFFERENTIAL LINE DRIVER

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1 AM6LS SLLSG JANUARY 979 REVISED FEBRUARY Meets or Exceeds the Requirements of ANSI TIA/EIA--B and ITU Recommendation V. Operates From a Single -V Supply TTL Compatible Complementary Outputs High Output Impedance in Power-Off Conditions Complementary Output-Enable Inputs description D, DB, N, OR NS PACKAGE (TOP VIEW) A Y Z G Z Y A GND V CC A Y Z G Z Y A The AM6LS is a quadruple complementary-output line driver designed to meet the requirements of ANSI TIA/EIA--B and ITU (formerly CCITT) Recommendation V.. The -state outputs have high-current capability for driving balanced lines such as twisted-pair or parallel-wire transmission lines, and they provide a high-impedance state in the power-off condition. The enable function is common to all four drivers and offers the choice of an active-high or active-low enable (G, G) input. Low-power Schottky circuitry reduces power consumption without sacrificing speed. The AM6LS is characterized for operation from C to 7 C. TA C to 7 C PLASTIC SMALL OUTLINE (D, NS) AM6LSCD AM6LSCNS AVAILABLE OPTIONS PACKAGED DEVICES PLASTIC SHRINK SMALL OUTLINE (DB) AM6LSCDB PLASTIC DIP (N) AM6LSCN The DB and NS packages are only available taped and reeled. Add the suffix R to the device type (e.g., AM6LSCDBR). FUNCTION TABLE (each driver) INPUT ENABLES OUTPUTS A G G Y Z H H X H L L H X L H H X L H L L X L L H X L H Z Z H = high level, L = low level, X = irrelevant, Z = high impedance (off) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright, Texas Instruments Incorporated POST OFFICE BOX 6 DALLAS, TEXAS 76

2 AM6LS SLLSG JANUARY 979 REVISED FEBRUARY logic diagram (positive logic) G G A A 7 6 A 9 A Y Z Y Z Y Z Y Z schematic (each driver) Input A V kω 9 Ω Output Y 9 Ω Output Z Common to All Four Drivers VCC V kω kω To Three Other Drivers Enable G Enable G GND All resistor values are nominal. POST OFFICE BOX 6 DALLAS, TEXAS 76

3 AM6LS SLLSG JANUARY 979 REVISED FEBRUARY absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, V CC (see Note ) V Input voltage, V I V Output off-state voltage V Package thermal impedance, θ JA (see Note ): D package C/W DB package C/W N package C/W NS package C/W Lead temperature,6 mm (/6 inch) from case for seconds C Storage temperature range, T stg C to C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES:. All voltage values, except differential output voltage VOD, are with respect to network GND.. The package thermal impedance is calculated in accordance with JESD -7. recommended operating conditions MIN NOM MAX UNIT VCC Supply voltage.7. V VIH High-level input voltage V VIL Low-level input voltage.8 V IOH High-level output current ma IOL Low-level output current ma TA Operating free-air temperature 7 C electrical characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIK Input clamp voltage VCC =.7 V, II = 8 ma. V VOH High-level output voltage VCC =.7 V, IOH = ma. V VOL Low-level output voltage VCC =.7 V, IOL = ma. V IOZ Off-state (high-impedance-state) impedance output current VCC =.7 V VO =. V VO =. V II Input current at maximum input voltage VCC =. V, VI = 7 V. ma IIH High-level input current VCC =. V, VI =.7 V µa IIL Low-level input current VCC =. V, VI =. V.6 ma IOS Short-circuit output current VCC =. V ma ICC Supply current VCC =. V, All outputs disabled 8 ma All typical values are at VCC = V and TA = C. Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second. µa POST OFFICE BOX 6 DALLAS, TEXAS 76

4 AM6LS SLLSG JANUARY 979 REVISED FEBRUARY switching characteristics, V CC = V, T A = C (see Figure ) tplh tphl tpzh tpzl tphz tplz PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Propagation delay time, low-to-high-level output CL =pf pf, S and S open Propagation delay time, high-to-low-level output ns Output enable time to high level RL = 7 Ω CL =pf Output enable time to low level RL = 8 Ω 7 ns Output disable time from high level CL =pf pf, S and S closed Output disable time from low level ns Output-to-output skew CL = pf, S and S open 6 ns PARAMETER MEASUREMENT INFORMATION Test Point VCC Input A (see Notes B and C). V. V tplh tphl V V From Output Under Test CL (see Note A) 7 Ω S S 8 Ω Output Y Output Z tphl Skew. V Skew tplh. V VOH VOL VOH VOL PROPAGATION DELAY TIMES AND SKEW TEST CIRCUIT Enable G (see Note D) Enable G. V See Note D. V V V Waveform (see Note E) tpzl S Closed S Open tpzh. V. V tplz tphz S Closed S Closed. V. V VOL Waveform (see Note E) S Open S Closed. V V ENABLE AND DISABLE TIME WAVEFORMS. V S Closed S Closed VOH. V NOTES: A. B. CL includes probe and jig capacitance. All input pulses are supplied by generators having the following characteristics: PRR MHz, ZO Ω, tr ns, tf 6 ns. C. When measuring propagation delay times and skew, switches S and S are open. D. Each enable is tested separately. E. Waveform is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform is for an output with internal conditions such that the output is high except when disabled by the output control. Figure. Test Circuit and Voltage Waveforms POST OFFICE BOX 6 DALLAS, TEXAS 76

5 AM6LS TYPICAL CHARACTERISTICS SLLSG JANUARY 979 REVISED FEBRUARY OUTPUT VOLTAGE ENABLE G INPUT VOLTAGE ÎÎÎ Load = 7 Ω to GND Î VCC =. V ÎÎÎ TA = C See Note A VCC = V OUTPUT VOLTAGE ENABLE G INPUT VOLTAGE ÎÎÎ VCC = V ÎÎÎ Load = 7 Ω to GND See Note A TA = 7 C Y Output Voltage V Î VCC =.7 V Y Output Voltage V Î TA = C TA = C VI Enable G Input Voltage V VI Enable G Input Voltage V Figure Figure 6 OUTPUT VOLTAGE ENABLE G INPUT VOLTAGE VCC =. V 6 OUTPUT VOLTAGE ENABLE G INPUT VOLTAGE Output Voltage V VCC = V VCC =.7 V ÎÎ Load = 7 Ω to VCC ÎÎ TA = C See Note B Output Voltage V Î TA = 7 C TA = C ÎÎÎ TA = C VCC = V ÎÎÎ Load = 7 Ω to VCC See Note B VI Enable G Input Voltage V VI Enable G Input Voltage V Figure Figure NOTES: A. The A input is connected to VCC during testing of the Y outputs and to ground during testing of the Z outputs. B. The A input is connected to ground during testing of the Y outputs and to VCC during testing of the Z outputs. POST OFFICE BOX 6 DALLAS, TEXAS 76

6 AM6LS SLLSG JANUARY 979 REVISED FEBRUARY TYPICAL CHARACTERISTICS High-Level Output Voltage V H HIGH-LEVEL OUTPUT VOLTAGE FREE-AIR TEMPERATURE VCC = V See Note A Î IOH = ma Î IOH = ma 7 H High-Level Output Voltage V HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT CURRENT VCC =. V Î VCC =.7 V VCC = V TA = C See Note A 6 8 TA Free-Air Temperature C IOH High-Level Output Current ma Figure 6 Figure 7 Low-Level Output Voltage V L Î VCC = V IOL = ma Î..... See Note B LOW-LEVEL OUTPUT VOLTAGE FREE-AIR TEMPERATURE L Low-Level Output Voltage V LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT CURRENT TA = C See Note B VCC =.7 V Î VCC =. V 7 TA Free-Air Temperature C Figure IOL Low-Level Output Current ma Figure 9 NOTES: A. The A input is connected to VCC during testing of the Y outputs and to ground during testing of the Z outputs. B. The A input is connected to ground during testing of the Y outputs and to VCC during testing of the Z inputs. 6 POST OFFICE BOX 6 DALLAS, TEXAS 76

7 AM6LS TYPICAL CHARACTERISTICS SLLSG JANUARY 979 REVISED FEBRUARY Y Output Voltage V No Load TA = C Y OUTPUT VOLTAGE DATA INPUT VOLTAGE Î VCC =. V VCC = V Î VCC =.7 V Y Output Voltage V No Load TA = C Y OUTPUT VOLTAGE DATA INPUT VOLTAGE TA = 7 C TA = C VI Data Input Voltage V Figure VI Data Input Voltage V Figure POST OFFICE BOX 6 DALLAS, TEXAS 76 7

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MC3486 QUADRUPLE DIFFERENTIAL LINE RECEIVER WITH 3-STATE OUTPUTS

MC3486 QUADRUPLE DIFFERENTIAL LINE RECEIVER WITH 3-STATE OUTPUTS Meets or Exceeds the Requirements of ANSI Standards EIA/TIA-422-B and EIA/TIA-423-B and ITU Recommendations V.10 and V.11 3-State, TTL-Compatible s Fast Transition Times Operates From Single 5-V Supply