SN75174 QUADRUPLE DIFFERENTIAL LINE DRIVER
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- Frank O’Brien’
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1 SN Meets or Exceeds the Requirements of ANSI Standards EIA/TIA--B and RS-8 and ITU Recommendation V.. Designed for Multipoint Transmission on Long Bus Lines in Noisy Environments -State s Common-Mode Voltage Range of V to V Active-High Enable Thermal Shutdown Protection Positive- and Negative-Current Limiting Operates From Single -V Supply Low Power Requirements Functionally Interchangeable With MC8 description The SN is a monolithic quadruple differential line driver with -state outputs. It is designed to meet the requirements of ANSI Standards EIA/TIA--B and RS-8 and ITU Recommendation V.. The device is optimized for balanced multipoint bus transmission at rates up to megabaud. Each driver features wide positive and negative common-mode output voltage ranges making it suitable for party-line applications in noisy environments. SLLS9B OCTOBER 98 REVISED MAY 99 The SN provides positive- and negative-current limiting and thermal shutdown for protection from line fault conditions on the transmission bus line. Shutdown occurs at a junction temperature of approximately C. This device offers optimum performance when used with the SN or SN quadruple differential line receivers. The SN is characterized for operation from C to C. FUNCTION TABLE (each driver) INPUT ENABLE OUTPUTS Y Z H H H L L H L H X L Z Z H = TTL high level, X = irrelevant, L = TTL low level, Z = high impedance (off) A Y Z,EN Z Y A GND A Y NC Z,EN Z NC Y A GND N PACKAGE (TOP VIEW) DW PACKAGE (TOP VIEW) V CC A Y Z,EN Z Y A V CC A Y NC Z,EN Z NC Y A NC No internal connection Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 99, Texas Instruments Incorporated POST OFFICE BOX 6 DALLAS, TEXAS 6
2 SN SLLS9B OCTOBER 98 REVISED MAY 99 logic symbol logic diagram, each driver (positive logic),en A A EN 6 Y Z Y Z A EN Y Z,EN EN A A 9 Y Z Y Z This symbol is in accordance with ANSI/IEEE Std 9-98 and IEC Publication 6-. schematics of inputs and outputs EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS VCC R(eq) VCC Input Data Inputs: R(eq) = kω NOM Enable Inputs: R(eq) = 8 kω NOM R(eq) = equivalent resistor GND POST OFFICE BOX 6 DALLAS, TEXAS 6
3 SN SLLS9B OCTOBER 98 REVISED MAY 99 absolute maximum ratings over operating free-air temperature (unless otherwise noted) Supply voltage, V CC (see Note ) V voltage range,v O V to V Input voltage, V I V Continuous total dissipation See Dissipation Rating Table Operating free-air temperature range, T A C to C Storage temperature range, T stg C to C Lead temperature,6 mm (/6 inch) from case for seconds C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE : All voltage values are with respect to the network ground terminal. PACKAGE DISSIPATION RATING TABLE TA C POWER RATING DERATING FACTOR ABOVE TA = C TA = C POWER RATING DW mw 9. mw/ C mw recommended operating conditions N mw 9. mw/ C 6 mw MIN NOM MAX UNIT Supply voltage, VCC.. V High-level input voltage, VIH V Low-level input voltage, VIL.8 V Common-mode output voltage, VOC to V High-level output current, IOH 6 ma Low-level output current, IOL 6 ma Operating free-air temperature, TA C POST OFFICE BOX 6 DALLAS, TEXAS 6
4 SN SLLS9B OCTOBER 98 REVISED MAY 99 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIK Input clamp voltage II = 8 ma. V VIH = V, VIL=.8 V, VOH High-level output voltage IOH = ma VIH = V, VIL=.8 V, VOL Low-level output voltage IOL = ma. V. V VO voltage IO = 6 V VOD Differential output voltage IO =. 6 6 V VOD Differential output voltage RL = Ω, See Figure / VOD or RL = Ω, See Figure.. V VOD Differential output voltage See Note. V VOD Change in magnitude of differential output voltage VOC Common-mode mode output voltage RL = Ω or Ω, See Figure VOC Change in magnitude of common-mode mode output voltage V ±. V + V ±. V IO current with power off VCC =, VO = V to V ± µa IOZ High-impedance-state output current VO = V to V ± µa IIH High-level input current VI =. V µa IIL Low-level input current VI =. V 6 µa VO = V 8 IOS Short-circuit output current VO = VCC 8 ma ICC Supply current (all drivers) No load VO = V s enabled 8 6 s disabled 8 All typical values are at VCC = V and TA = C. The minimum VOD with a -Ω load is either / VOD or V, whichever is greater. VOD and VOC are the changes in magnitude of VOD and VOC, respectively, that occur when the input is changed from a high level to a low level. In ANSI Standard EIA/TIA--B, VOC, which is the average of the two output voltages with respect to ground, is called output offset voltage, VOS. NOTE : See EIA Standard RS-8. switching characteristics, V CC = V, T A = C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT td(od) Differential-output delay time 6 ns RL =Ω Ω, See Figure tt(od) Differential-output transition time 8 ns tpzh enable time to high level RL = Ω, See Figure 8 ns tpzl enable time to low level RL = Ω, See Figure 8 ns tphz disable time from high level RL = Ω, See Figure ns tplz disable time from low level RL = Ω, See Figure 8 ns ma POST OFFICE BOX 6 DALLAS, TEXAS 6
5 SN SYMBOL EQUIVALENTS DATA SHEET PARAMETER EIA/TIA--B RS-8 VO Voa, Vob Voa, Vob VOD Vo Vo VOD Vt (RL = Ω) Vt (RL = Ω) VOD Vt (Test Termination) Measurement ) VOD Vt Vt Vt Vt VOC Vos Vos VOC Vos Vos Vos Vos IOS Isa, Isb IO Ixa, Ixb Iia,Iib SLLS9B OCTOBER 98 REVISED MAY 99 PARAMETER MEASUREMENT INFORMATION VOD RL RL VOC Figure. Differential and Common-Mode Voltages V RL = CL = pf td(od) td(od) Generator Ω (see Note B) ~. V (see Note A) Ω 9% 9% V % % % % ~. V TEST CIRCUIT Input tt(od). V. V VOLTAGE WAVEFORMS NOTES: A. The input pulse is supplied by a generator having the following characteristics: tr ns, tf ns, PRR MHz, duty cycle = %, ZO = Ω. B. CL includes probe and stray capacitance. Figure. Differential- Test Circuit and Voltage Waveforms V tt(od) POST OFFICE BOX 6 DALLAS, TEXAS 6
6 SN SLLS9B OCTOBER 98 REVISED MAY 99 Generator (see Note A) V to V Ω PARAMETER MEASUREMENT INFORMATION TEST CIRCUIT S CL = pf (see Note B) RL = Ω Input. V. V tphz tpzh. V. V VOLTAGE WAVEFORMS NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR MHz, duty cycle = %, tr ns, tf ns, ZO = Ω. B. CL includes probe and stray capacitance. Figure. Test Circuit and Voltage Waveforms V V VOH Voff V V V to V S RL = Ω Input. V. V V V Generator (see Note A) Ω CL = pf (see Note B) tpzl. V tplz. V V VOL TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR MHz, duty cycle = %, tr ns, tf ns, ZO = Ω. B. CL includes probe and stray capacitance. Figure. Test Circuit and Voltage Waveforms 6 POST OFFICE BOX 6 DALLAS, TEXAS 6
7 SN TYPICAL CHARACTERISTICS SLLS9B OCTOBER 98 REVISED MAY 99 High-Level Voltage V V OH..... HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT CURRENT VCC = V TA = C VOL Low-Level Voltage V..... LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT CURRENT VCC = V TA = C IOH High-Level Current ma IOL Low-Level Current ma Figure Figure 6 Differential Voltage V VOD.... DIFFERENTIAL OUTPUT VOLTAGE OUTPUT CURRENT Á VCC = V Á TA = C IIO O Current A µ A Disabled TA = C VCC = V VCC = V OUTPUT CURRENT OUTPUT VOLTAGE 6 8 IO Current ma 9 VO Voltage V Figure Figure 8 POST OFFICE BOX 6 DALLAS, TEXAS 6
8 SN SLLS9B OCTOBER 98 REVISED MAY 99 TYPICAL CHARACTERISTICS ICC Supply Current ma Á Á No Load Á s Enabled TA = C SUPPLY CURRENT SUPPLY VOLTAGE Inputs Open Inputs Grounded ICC Supply Current ma No Load Á Input Open Á s Disabled TA = C SUPPLY CURRENT SUPPLY VOLTAGE 6 VCC Supply Voltage V 8 6 VCC Supply Voltage V 8 Figure 9 Figure APPLICATION INFORMATION / SN / SN RT RT / SN Up to RS-8 Unit Loads / SN / SN / SN / SN / SN NOTE: The line length should be terminated at both ends in its characteristic impedance (RT = ZO). Stub lengths off the main line should be kept as short as possible. Figure. Typical Application Circuit 8 POST OFFICE BOX 6 DALLAS, TEXAS 6
9 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ( CRITICAL APPLICATIONS ). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not constitute TI s approval, warranty or endorsement thereof. Copyright 998, Texas Instruments Incorporated
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Package Optio Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs TYPE TYPICAL MAXIMUM CLOCK FREUEY (CL = 0 pf) (MHz) TYPICAL POWER
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Member of Texas Instruments Widebus Family State-of-the-Art Advanced Low-Voltage BiCMOS (ALB) Technology Design for.-v Operation Schottky Diodes on All s to Eliminate Overshoot and Undershoot Industry
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More informationEN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at ore.hu.
EN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at www.hest ore.hu. Convert TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping
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SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244 3-State s Drive Bus Lines or Buffer Memory Address Registers PNP s Reduce DC Loading Hysteresis at s Improves Noise Margins description These
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Member of the Texas Itruments idebus Family Load Clock and Unload Clock Can Be Asynchronous or Coincident 256 ords by 18 Bits Low-Power Advanced CMOS Technology Full, Empty, and Half-Full Flags Programmable
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