SN75177B, SN75178B DIFFERENTIAL BUS REPEATERS
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1 SN, SN SLLSC D66, JULY 9 REVISED FERURY 99 Meets EI Standards RS-- and RS- and CCI Recommendations V. and X. Designed for Multipoint ransmission on Long us Lines in Noisy Environments -State s us Voltage Range... V to V Positive and Negative Current Limiting Driver Capability... 6 m Max Driver hermal Shutdown Protection Receiver Impedance... kω Min Receiver Sensitivity... ± mv Receiver Hysteresis... mv yp Operates From Single -V Supply Low Power Requirements description SN...D OR P PCKGE (OP VIEW) V CC GND 6 Z Y SN...P PCKGE (OP VIEW) V CC GND 6 Z Y HE SN IS NO RECOMMDED FOR NEW DESIGN he SN and SN differential bus repeaters are monolithic integrated devices each designed for one-way data communication on multipoint bus transmission lines. hese devices are designed for balanced transmission bus line applications and meet EI Standard RS-- and RS- and CCI Recommendations V. and X.. Each device is designed to improve the performance of the data communication over long bus lines. he SN and SN are identical except for the complementary enable inputs, which allow the devices to be used in pairs for bidirectional communication. he SN and SN feature positive- and negative-current limiting -state outputs for the receiver and driver. he receiver features high input impedance, input hysteresis for increased noise immunity, and input sensitivity of ± mv over a common-mode input voltage range of V to V. he driver features thermal shutdown for protection from line fault conditions. hermal shutdown is designed to occur at a junction temperature of approximately C. he driver is designed to drive current loads up to 6 m maximum. he SN and SN are designed for optimum performance when used on transmission buses employing the SN and SN differential line drivers, SN and SN differential line receivers, or SN6 bus transceiver. Function ables SN DIFFERIL INPUS LE OUPUS Y Z VID. V H H H L. V < VID <. V H??? VID. V H L L H X L Z Z Z SN DIFFERIL INPUS LE OUPUS Y Z VID. V L H H L. V < VID <. V L??? VID. V L L L H X H Z Z Z H = high level, L = low level,? = indeterminate, X = irrelevant, Z = impedance (off) PRODUCION D information is current as of publication date. Products conform to specifications per the terms of exas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 99, exas Instruments Incorporated POS OFFICE OX 6 DLLS, EXS 6
2 SN, SN SLLSC D66, JULY 9 REVISED FERURY 99 logic symbols logic diagrams (positive logic) SN 6 Y Z SN Receiver Driver 6 Y Z SN 6 Y Z SN Receiver Driver 6 Y Z hese symbols are in accordance with NSI/IEEE Std 9-9 and IEC Publication 6-. schematics of inputs and outputs EQUIVL OF ECH INPU YPICL OF LL DRIVER OUPUS VCC Req VCC Driver input: Req = kω NOM Enable inputs: Req = kω NOM EQUIVL OF ECH RECEIVER INPU VCC GND YPICL OF RECEIVER OUPU VCC Ω NOM 6. kω NOM 96 Ω NOM 96 Ω NOM POS OFFICE OX 6 DLLS, EXS 6
3 SN, SN SLLSC D66, JULY 9 REVISED FERURY 99 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, V CC (see Note ) V Voltage range at any bus terminal V to V Differential input voltage (see Note ) ± V Enable input voltage V Continuous total dissipation See Dissipation Rating able Operating free-air temperature range C to C Storage temperature range C to C Lead temperature,6 mm (/6 inch) from case for seconds C NOES:. ll voltage values, except differential input voltage, are with respect to network ground terminal.. Differential input voltage is measured at the noninverting input with respect to the corresponding inverting input. PCKGE recommended operating conditions DISSIPION RING LE C POWER RING DERING FCOR OVE = C = C POWER RING D mw. mw/ C 6 mw P mw. mw/ C 6 mw MIN NOM MX UNI Supply voltage, VCC.. V High-level input voltage, VIH or V low-level input voltage, VIL or. V Common-mode input voltage, VIC V Differential input voltage, VID ± V High-level output current, IOH Low-level output current, IOL Driver 6 m Receiver µ Driver 6 Receiver Operating free-air temperature, C he algebraic convention, where the less-positive (more-negative) limit is designated minimum, is used in this data sheet for common-mode input voltage and threshold voltage. m POS OFFICE OX 6 DLLS, EXS 6
4 SN, SN SLLSC D66, JULY 9 REVISED FERURY 99 DRIVER SECION electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PRMEER ES CONDIIONS MIN YP MX UNI VIK clamp voltage II = m VO voltage IO = 6 V VOD Differential output voltage IO =. 6 V VOD Differential output voltage RL = Ω, See Figure / VOD or RL = Ω, See Figure.. VOD Differential output voltage See Note. V VOD VOC VOC Change in magnitude of diferential output voltage Common-mode mode output voltage RL = Ω or Ω, See Figure V ±. V Change in magnitude of ±. V common-mode output voltage IO current VCC =, VO = V to V ± µ IOZ High-impedance-state output current VO = V to V ± µ IIH High-level input current VI =. V µ IIL Low-level input current VI =. V µ VO = V IOS Short-circuit output current VO = VCC m ICC Supply current (total package) No load VO = V s enabled s disabled 6 ll typical values are at VCC = V and = C. VOD and VOC are the changes in magnitude of VOD and VOC, respectively, that occur when the input is changed from a high level to a low level. he minimum VOD with a -Ω load is either / VOD or, whichever is greater. NOE : See Figure. of EI Standard RS-. switching characteristics, V CC = V, = C PRMEER ES CONDIIONS MIN YP MX UNI tdd Differential-output delay time ns RL =Ω Ω, See Figure ttd Differential-output transition time ns tpzh enable time to high level RL = Ω, See Figure ns tpzl enable time to low level RL = Ω, See Figure 6 ns tphz disable time from high level RL = Ω, See Figure ns tplz disable time from low level RL = Ω, See Figure ns V m POS OFFICE OX 6 DLLS, EXS 6
5 SN, SN SYMOL EQUIVLS D SHEE PRMEER RS-- RS- VO Voa, Vob Voa, Vob VOD Vo Vo VOD Vt (RL = Ω) Vt (RL = Ω) SLLSC D66, JULY 9 REVISED FERURY 99 VOD Vt (est ermination) Measurement ) VOD Vt Vt Vt Vt VOC VOS VOS VOC VOS VOS VOS VOS IOS Isa, Isb IO Ixa, Ixb Iia,Iib RECEIVER SECION electrical characteristics over recommended ranges of common-mode input voltage, supply voltage, and operating free-air temperature (unless otherwise noted) PRMEER ES CONDIIONS MIN YP MX UNI V+ Positive-going input threshold voltage VO =. V, IO =. m. V V Negative-going input threshold voltage VO =. V, IO = m. V Vhys hysteresis (V+ V ) mv VIK clamp voltage at II = m VOH High-level output voltage VID = mv, IOH = µ,. V See Figure VOL Low-level output voltage VID = mv, IOL = m,. V See Figure IOZ High-impedance-state impedance output current VO =. V to. V II Line input current Other input at V, VI = V See Note VI = V. IIH High-level enable-input current VIH =. V µ IIL Low-level enable-input current VIL =. V µ ri resistance kω IOS Short-circuit output current m ICC Supply current (total package) No load s enabled s disabled 6 ll typical values are at VCC = V, = C. he algebraic convention, where the less-positive (more-negative) limit is designated minimum, is used in this data sheet for common-mode input voltage and threshold voltage levels only. NOE : Refer to EI Standard RS- for exact conditions. switching characteristics, V CC = V, = C PRMEER ES CONDIIONS MIN YP MX UNI tplh Propagation delay time, low-to-high level output VID = to, 9 tphl Propagation delay time, high-to-low level output CL = pf, See Figure 6 tpzh enable time to high level CL = pf, See Figure tpzl enable time to high level tphz disable time from high level CL = pf, See Figure tplz disable time from low level µ m m ns ns ns POS OFFICE OX 6 DLLS, EXS 6
6 SN, SN SLLSC D66, JULY 9 REVISED FERURY 99 PRMEER MESUREM INFORMION VOD RL RL VOC VID VOL +IOL VOH IOH Figure. Driver V OD and V OC Figure. Receiver V OH and V OL Generator (see Note ) Ω ES CIRCUI RL = Ω CL = pf (see Note ) V V tdd tdd. V 9% % % %. V ttd ttd VOLGE WVEFORMS Figure. Driver Differential- est Circuit and Voltage Waveforms V or V Generator (see Note ) Ω S CL = pf (see Note ) SN Enable is ctive Low ES CIRCUI RL = Ω (SN) (SN) Figure. Driver Enable and Disable imes tpzh. V tphz V V. V VOLGE WVEFORMS VOH Voff V V or V S V RL = Ω (SN) (SN) tpzl V V Generator (see Note ) Ω SN Enable is ctive Low CL = pf (see Note ). V tplz V. V VOL ES CIRCUI VOLGE WVEFORMS Figure. Driver Enable and Disable imes NOES:. he input pulse is supplied by a generator having the following characteristics: PRR MHz, % duty cycle, tr 6 ns, tf 6 ns, ZO = Ω.. CL includes probe and jig capacitance. 6 POS OFFICE OX 6 DLLS, EXS 6
7 SN, SN Generator (see Note ) Ω PRMEER MESUREM INFORMION ES CIRCUI CL = pf (see Note ) SLLSC D66, JULY 9 REVISED FERURY 99 tplh Figure 6. Receiver Propagation Delay imes. V VOLGE WVEFORMS. V V V tphl VOH VOL S kω S V CL = pf (see Note ) kω (see Note C) Generator (see Note ) Ω S ES CIRCUI (SN) (SN) tpzh V S to S Open S Closed V Á (SN) Á (SN) tpzl V S to S Closed S Open V (SN) (SN) VOH V V S to S Closed S Closed V Á (SN) (SN). V VOL V S to S Closed S Closed V tphz tplz. V VOH. V. V. V VOL VOLGE WVEFORMS Figure. Receiver Enable and Disable imes NOES:. he input pulse is supplied by a generator having the following characteristics: PRR MHz, % duty cycle, tr 6 ns, tf 6 ns, ZO = Ω.. CL includes probe and jig capacitance. C. ll diodes are N96 or equivalent. POS OFFICE OX 6 DLLS, EXS 6
8 SN, SN SLLSC D66, JULY 9 REVISED FERURY 99 YPICL CHRCERISICS. DRIVER HIGH-LEVEL OUPU VOLGE HIGH-LEVEL OUPU CURR VCC = V = C. DRIVER LOW-LEVEL OUPU VOLGE LOW-LEVEL OUPU CURR VCC = V = C High-Level Voltage V V OH.... High-Level Voltage V... Á Á V OH. 6 6 IOH High-Level Current m IOH Low-Level Current m Figure Figure 9 Differential Voltage V VOD.... DRIVER DIFFERIL OUPU VOLGE DRIVER OUPU CURR VCC = V = C V VO O Voltage V RECEIVER OUPU VOLGE DIFFERIL INPU VOLGE VCC = V VIC = V V V+ IO = VIC = V V V+ = C VIC = V V V+ 6 IO Current m 9 VID Differential Voltage mv Figure Figure POS OFFICE OX 6 DLLS, EXS 6
9 SN, SN YPICL CHRCERISICS SLLSC D66, JULY 9 REVISED FERURY 99 High-Level Voltage V V OH RECEIVER HIGH-LEVEL OUPU VOLGE HIGH-LEVEL OUPU CURR VCC =. V VCC =. V VCC = V VID =. V = C High-Level Voltage V V OH RECEIVER HIGH-LEVEL OUPU VOLGE FREE-IR EMPERURE VCC = V VID = mv IOH = µ IOH High-Level Current m 6 Free-ir emperature C Figure Figure Low-Level Voltage V V OL RECEIVER LOW-LEVEL OUPU VOLGE LOW-LEVEL OUPU CURR VCC = V = C V OL Low-Level Voltage V RECEIVER LOW-LEVEL OUPU VOLGE FREE-IR EMPERURE VCC = V VID = mv IOL = m 6 IOL Low-Level Current m Free-ir emperature C Figure Figure POS OFFICE OX 6 DLLS, EXS 6 9
10 SN, SN SLLSC D66, JULY 9 REVISED FERURY 99 PPLICION INFORMION Direction / SN9 R Control R / SN9 SN SN6 SN6 R R R R SN SN6 NOE: he line should be terminated at both ends in its characteristic impedance. Stub lengths off the main line should be kept as short as possible. Figure 6. ypical pplication Circuit POS OFFICE OX 6 DLLS, EXS 6
11 IMPORN NOICE exas Instruments (I) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. I warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with I s standard warranty. esting and other quality control techniques are utilized to the extent I deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage ( Critical pplications ). I SEMICONDUCOR PRODUCS RE NO DESIGNED, INDED, UHORIZED, OR WRRNED O E SUILE FOR USE IN LIFE-SUPPOR PPLICIONS, DEVICES OR SYSEMS OR OHER CRIICL PPLICIONS. Inclusion of I products in such applications is understood to be fully at the risk of the customer. Use of I products in such applications requires the written approval of an appropriate I officer. Questions concerning potential risk applications should be directed to I through a local SC sales office. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards. I assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does I warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of I covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. Copyright 996, exas Instruments Incorporated
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Independent Asychronous Inputs and Outputs 16 Words by 5 Bits DC to 10-MHz Rate 3-State Outputs Packaged in Standard Plastic 300-mil DIPs description This 80-bit active-element memory is a monolithic Schottky-clamped
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PERIPHERAL DRIVERS FOR HIGH-CURRENT SWITCHING AT VERY HIGH SPEEDS Characterized for Use to 00 ma High-Voltage Outputs No Output Latch-Up at 0 V (After Conducting 00 ma) High-Speed Switching Circuit Flexibility
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Member of the Texas Instruments Widebus Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 200 Per MIL-STD-883, Method 3015; Exceeds 20 Using Machine Model (C =
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SCLS07B DECEMBER 92 REVISED MAY 997 Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK),
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4AC64, 74AC64 6-BIT BUS TRANSCEIVERS SCAS3A MARCH 990 REVISED APRIL 996 Members of the Texas Itruments Widebus Family 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers Flow-Through Architecture
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Inputs Are TTL Compatible EPIC (Enhanced-Performance Implanted CMOS) -µm Process Package Optio Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and DIP (N)
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Package Optio Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs TYPE TYPICAL MAXIMUM CLOCK FREUEY (CL = 0 pf) (MHz) TYPICAL POWER
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Inputs Are TTL-Voltage Compatible Eight High-Current Latches in a Single Package High-Current -State True s Can Drive up to LSTTL Loads Full Parallel Access for Loading Package Optio Include Plastic Small-Outline
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Meets or Exceeds the Requirements of TIA/EIA-232-F and ITU Recommendation V.28 Single Chip With Easy Interface Between UART and Serial-Port Connector Less Than 9-mW Power Consumption Wide Driver Supply
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Package Optio Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description These devices contain four independent 2-input exclusive-or
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Members of the Texas Itruments Widebus Family Inputs Are TTL-Voltage Compatible 3-State Bus Driving True s Full Parallel Access for Loading Flow-Through Architecture Optimizes PCB Layout Distributed and
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SN54LS373, SN54LS374, SN54S373, SN54S374, Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving s Full Parallel Access for Loading Buffered Control s Clock-Enable Has
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Contain Four Flip-Flops With Double-Rail Outputs Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators Package Options Include Plastic Small-Outline (D), Thin Shrink Small-Outline
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00-m Current Capability Per Driver Pulsed Current.- Per Driver Clamp Diodes for Inductive Transient Suppression Wide Supply Voltage Range 4.5 V to V Separate -ogic Supply Thermal Shutdown Internal ESD
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Meets or Exceeds the Requirements of ANSI EIA/TIA-232-E and ITU Recommendation V.28 Single Chip With Easy Interface Between UART and Serial Port Connector Less Than 9-mW Power Consumption Wide Driver Supply
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Member of Texas Instruments Widebus Family Latch-Up Performance Exceeds 250 ma Per JESD 17 description This 16-bit (dual-octal) noninverting bus transceiver contains two separate supply rails; B port has
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Member of Texas Instruments Widebus Family Latch-Up Performance Exceeds 250 ma Per JESD 17 ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) Bus Hold on Data
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ULNA THRU ULNA SLRS D, DECEMBER REVISED APRIL HIGH-VOLTAGE HIGH-CURRENT -ma Rated Collector Current (Single ) High-Voltage s... V Clamp Diodes Inputs Compatible With Various Types of Logic Relay Driver
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SN7577, SN7578 Meet or Exceed the Requirements of ANSI Standards TIA/EIA-4-B and TIA/EIA-485-A and ITU Recommendations V.0 and V. Designed for Multipoint Bus Transmission on Long Bus Lines in Noise Environments
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Eight Flip-Flops With Single-Rail Outputs Clock Enable Latched to Avoid False Clocking Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators Package Options Include Plastic
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WITH CLEA SDAS2A APIL 2 EVISED DECEMBE 4 Contain Eight Flip-Flops With Single-ail Outputs Buffered Clock and Direct-Clear Inputs Individual Data Input to Each Flip-Flop Applications Include: Buffer/Storage
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HIH-SPEED DIFFERENTIAL LINE DRIVER Designed for Signaling Rates Up to 5 Mbps Low-Voltage Differential Signaling With Typical Output Voltage of 7 mv and a -Ω Load Propagation Delay Time of. ns, Typical
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Operation From Very Slow Input Transitions Temperature-Compensated Threshold Levels High Noise Immunity Same Pinouts as HC00 Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB),
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Package Options Include Plastic Small-Outline (D), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description
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Operates With Single -V Power Supply LinBiCMOS Process Technology Two Drivers and Two Receivers ± 0-V Input Levels Low Supply Current...8 ma Typical Meets or Exceeds TIA/EIA-22-F and ITU Recommendation
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Member of the Texas Instruments Widebus Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process UBT (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in
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Member of Texas Instruments Widebus Family State-of-the-Art Advanced Low-Voltage BiCMOS (ALB) Technology Design for.-v Operation Schottky Diodes on All s to Eliminate Overshoot and Undershoot Industry
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Typical V OLP ( Ground Bounce) 2 V at V CC = 3.3 V, T A = 25 C s Accept Voltages to 5.5 V Latch-Up Performance Exceeds 100 ma Per JESD
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SLRSB DECEMBER REVISED SEPTEMBER HIGH-VOLTAGE HIGH-CURRENT -ma Rated Collector Current (Single ) High-Voltage s... V Clamp Diodes Inputs Compatible With Various Types of Logic Relay Driver Applications
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Dual Versions of Highly Stable SN542 and SN742 One Shots SN5422 and SN7422 Demonstrate Electrical and Switching Characteristics That Are Virtually Identical to the SN542 and SN742 One Shots Pinout Is Identical
More informationEN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at ore.hu.
EN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at www.hest ore.hu. Convert TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping
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SCAS AUGUST 99 REVISED MAY 99 Inputs Are TTL-Voltage Compatible EPIC (Enhanced-Performance Implanted CMOS) -µm Process Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin
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Inputs Are TTL-Voltage Compatible EPIC (Enhanced-Performance Implanted CMOS) Process Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), Thin Shrink
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HIGH-VOLTAGE, HIGH-CURRENT 500-mA-Rated Collector Current (Single ) High-Voltage s...50 V Clamp Diodes Inputs Compatible With Various Types of Logic Relay Driver Applications Compatible With ULN2800A-Series
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4.5-V to 5.5-V V CC Operation Fanout (Over Temperature Range) Standard s... 0 LSTTL Loads Bus-Driver s... 5 LSTTL Loads Wide Operating Temperature Range of 55 C to 25 C Balanced Propagation Delays and
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Compatible with TTL Inputs High-Speed Switching... Mbit/s Typ Bandwidth...2 MHz Typ High Common-Mode Transient Immunity... 000 V/µs Typ High-Voltage Electrical Insulation... 3000 Vdc Min Open-Collector
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SNALS2C, SNAS2A, SNALS2C, SNAS2A SDAS2C JUL 9 REISED AUGUST 99 -State Outputs Drive Bus Lines or Buffer Memory Address Registers pnp Inputs Reduce dc Loading Package Optio Include Plastic Small-Outline
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Operation From Very Slow Edges Improved Line-Receiving Characteristics High Noise Immunity SN5414, SN54LS14, SN5414, SN54LS14...J OR W PACKAGE SN7414... D, N, OR NS PACKAGE SN74LS14... D, DB, OR N PACKAGE
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ULNA, ULNA, ULNA, ULNA SLRS DECEMBER REVISED APRIL HIGH-VOLTAGE HIGH-CURRENT -ma Rated Collector Current (Single ) High-Voltage s... V Clamp Diodes Inputs Compatible With Various Types of Logic Relay Driver
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Single Down/Up Count-Control Line Look-Ahead Circuitry Enhances Speed of Cascaded Counters Fully Synchronous in Count Modes Asynchronously Presettable With Load Control Package Options Include Plastic
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Support the ME64 ETL Specification Reduced, TTL-Compatible, Input Threshold Range High-Drive Outputs (I OH = 60 m, I OL = 90 m) Support 25-Ω Incident-Wave Switching CC IS Pin Minimizes Signal Distortion
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Inputs Are TTL-Voltage Compatible EPIC (Enhanced-Performance Implanted CMOS) Process Contain Six Flip-Flops With Single-Rail s Applicatio Include: Buffer/Storage Registers Shift Registers Pattern Generators
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Complete PWM Power Control Circuitry Uncommitted Outputs for 00-mA Sink or Source Current Output Control Selects Single-Ended or Push-Pull Operation Internal Circuitry Prohibits Double Pulse at Either
More informationDistributed by: www.jameco.com -8-8-44 The content and copyrights of the attached material are the property of its owner. Bidirectional Transceivers Meet or Exceed the Requirements of ANSI Standards TIA/EIA-4-B
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Bidirectional Transceivers Meet or Exceed the Requirements of ANSI Standards TIA/EIA-4-B and TIA/EIA-485-A and ITU Recommendations V.11 and X.7 Designed for Multipoint Transmission on Long Bus Lines in
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Microprocessor Peripheral or Stand-Alone Operation 8-Bit Resolution A/D Converter Differential Reference Input Voltages Conversion Time...7 µs Max Total Access and Conversion Cycles Per Second TLC548...up
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Featuring Unitrode L and LD Products Now From Texas Instruments Wide Supply-Voltage Range:.5 V to V Separate Input-Logic Supply Internal ESD Protection Thermal Shutdown High-Noise-Immunity Inputs Functional
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Member of the Texas Itruments idebus Family Load Clock and Unload Clock Can Be Asynchronous or Coincident 256 ords by 18 Bits Low-Power Advanced CMOS Technology Full, Empty, and Half-Full Flags Programmable
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