SN75154 QUADRUPLE LINE RECEIVER
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1 Meets or Exceeds the Requirements of NSI Standard EI/I-22-E and IU Recommendation V.28 Input Resistance... kω to 7 kω Over Full EI/I-22-E Voltage Range Input hreshold djustable to Meet Fail-Safe Requirements Without Using External Components Built-In Hysteresis for Increased Noise Immunity Inverting Output Compatible With L Output With ctive Pullup for Symmetrical Switching Speeds Standard Supply Voltages... V or 2 V D OR N PCKGE (OP VIEW) V CC2 V CC R For function of R, see schematic description he SN74 is a monolithic low-power Schottky line receiver designed to satisfy the requirements of the standard interface between data terminal equipment and data communication equipment as defined by NSI Standard EI/I-22-E. Other applications are for relatively short, single-line, point-to-point data transmission and for level translators. Operation is normally from a single -V supply; however, a built-in option allows operation from a 2-V supply without the use of additional components. he output is compatible with most L circuits when either supply voltage is used. In normal operation, the threshold-control terminals are connected to the V CC terminal, even if power is being supplied via the alternate V CC2 terminal. his provides a wide hysteresis loop, which is the difference between the positive-going and negative-going threshold voltages. See typical characteristics. In this mode of operation, if the input voltage goes to zero, the output voltage will remain at the low or high level as determined by the previous input. For fail-safe operation, the threshold-control terminals are open. his reduces the hysteresis loop by causing the negative-going threshold voltage to be above zero. he positive-going threshold voltage remains above zero as it is unaffected by the disposition of the threshold terminals. In the fail-safe mode, if the input voltage goes to zero or an open-circuit condition, the output will go to the high level regardless of the previous input condition. he SN74 is characterized for operation from 0 C to 70 C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of exas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCION D information is current as of publication date. Products conform to specifications per the terms of exas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 99, exas Instruments Incorporated POS OFFICE BOX 60 DLLS, EXS 726
2 logic symbol logic diagram (positive logic) HRS DJ his symbol is in accordance with NSI/IEEE Std and IEC Publication schematic VCC2 Common to Four Receivers.2 kω VCC R kω of 4 Receivers hreshold Control. kω kω 9.9 kω.6 kω.6 kω 200 Ω Output Input 4.2 kω kω 240 Ω 2.7 kω Component values shown are nominal.... Substrate When VCC is used, VCC2 may be left open or shorted to VCC. When VCC2 is used, VCC must be left open or connected to the threshold control pins. 2 POS OFFICE BOX 60 DLLS, EXS 726
3 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Normal supply voltage, V CC (see Note ) V lternate supply voltage, V CC V Input voltage, V I ±2 V Continuous total power dissipation See Dissipation Rating able Operating free-air temperature range, C to 70 C Storage temperature range, stg C to 0 C Lead temperature,6 mm (/6 inch) from case for 0 seconds C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. hese are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOE : Voltage values are with respect to network terminal. PCKGE recommended operating conditions DISSIPION RING BLE 2 C DERING FCOR = 70 C POWER RING BOVE = 2 C POWER RING D 90 mw 7.6 mw/ C 608 mw N 0 mw 9.2 mw/ C 76 mw NS 62 mw.0 mw/ C 400 mw MIN NOM MX UNI Normal supply voltage, VCC 4.. V lternate supply voltage, VCC V High-level input voltage, VIH (see Note 2) V Low-level input voltage, VIL (see Note 2) V High-level output current, IOH 400 µ Low-level output current, IOL 6 m Operating free-air temperature, 0 70 C NOE 2: he algebraic convention, where the less positive (more negative) limit is designated as minimum, is used in this data sheet for logic and threshold levels only, e.g., when 0 V is the maximum, the minimum limit is a more negative voltage. POS OFFICE BOX 60 DLLS, EXS 726
4 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) VI+ VI Vhys PRMEER Positive-going g input threshold voltage Negative-going g g input threshold voltage Hysteresis voltage (VI+ VI ) Normal operation Fail-safe operation Normal operation Fail-safe operation Normal operation Fail-safe operation ES FIGURE ES CONDIIONS MIN P MX UNI VOH High-level output voltage IOH = 400 µ 2.4. V VOL Low-level output voltage IOL = 6 m V VI = 2 V to 4 V 7 VI = 4 V to V 7 ri Input resistance 2 VI = V to V 6 8 VI = V to 4 V 7 VI = 4 V to 2 V 7 VI(open) -circuit input voltage II = V IOS Short-circuit output current 4 VCC =. V, VI = V m ICC Supply current from VCC ICC2 Supply current from VCC2 ll typical values are at VCC = V, = 2 C. Not more than one output should be shorted at a time. switching characteristics, V CC = V, = 2 C, N = 0 PRMEER ES FIGURE VCC =. V, = 2 C 20 VCC2 =.2 V, = 2 C 2 40 V V V kω m ES CONDIIONS MIN P MX UNI tplh Propagation delay time, low- to high-level output ns tphl Propagation delay time, high- to low-level output 8 ns 6 CL =0pF pf, RL = 90 Ω tlh ransition time, low- to high-level output 7 ns thl ransition time, high- to low-level output 2.2 ns 4 POS OFFICE BOX 60 DLLS, EXS 726
5 PICL CHRCERISICS ÁÁVO Output Voltage V 4 2 Normal Operation OUPU VOLGE vs INPU VOLGE Fail-Safe Operation See Note V I VI VI + VCC = V = 2 C VI Input Voltage V NOE : For normal operation, the threshold controls are connected to VCC. For fail-safe operation, the threshold controls are open. Figure POS OFFICE BOX 60 DLLS, EXS 726
6 dc test circuits PRMEER MESUREMEN INFORMION ES BLE ES MESURE VCC VCC2 VOH IOH 4. V -circuit input (fail safe) VOH IOH 0.8 V VI + min, VI min (fail safe) VI + min (normal) VIL max, VI + min (normal) VIH min, VI+ max, VI max (fail safe) VIH min, VI + max (normal) VI max (normal) NOES:. Momentarily apply V, then 0.8 V. B. Momentarily apply V, then. VOH 0.8 V IOH. V VOH 0.8 V IOH.2 V VOH Note VCC IOH. V and VOH Note VCC IOH.2 V VOH V VCC IOH. V and VOH V VCC IOH.2 V VOL V IOL 4. V VOL V IOL 0.8 V VOL V VCC IOL 4. V and VOL V VCC IOL 0.8 V VOL Note B VCC IOL. V and VOL Note B VCC IOL.2 V. V 4. V.2 V 0.8 V VCC VCC2 R IOH VI,VI IOL VOL VOH Figure 2. V IH, V IL, V I+, V I, V OH, V OL rrows indicate actual direction of current flow. Current into a terminal is a positive value. 6 POS OFFICE BOX 60 DLLS, EXS 726
7 PRMEER MESUREMEN INFORMION dc test circuits (continued) ES BLE V 2 V VCC VCC2 V VCC and V II VCC VCC2 R VI ri = VI II 2 V VCC 2 V VCC VCC Figure. Input Resistance. V.2 V ES BLE VCC VCC2 R VCC VCC2. V VCC. V.2 V VCC.2 V VI(open) Figure 4. Input Voltage (). V.2 V. V ICC ICC2 VCC VCC2 R VCC VCC2 R V V IOS Each output is tested separately. Figure. Output Short-Circuit Current ll four line receivers are tested simultaneously. Figure 6. Supply Current rrows indicate actual direction of current flow. Current into a terminal is a positive value. POS OFFICE BOX 60 DLLS, EXS 726 7
8 PRMEER MESUREMEN INFORMION Input V Output RL = 90 Ω Pulse Generator (see Note ) VCC VCC2 R See Note C CL = 0 pf (see Note B) ES CIRCUI 0 ± 2 ns 0 ± 2 ns Input 0% V 90% 90% V 0% V 0 V V tphl tplh 2 V 2 V VOH Output. V. V 0.8 V 0.8 V VOL thl VOLGE WVEFORMS tlh NOES:. B. he pulse generator has the following characteristics: ZO = 0 Ω, tw 200 ns, duty cycle 20%. CL includes probe and jig capacitance. C. ll diodes are N064. Figure 6. est Circuit and Voltage Waveforms 8 POS OFFICE BOX 60 DLLS, EXS 726
9 IMPORN NOICE exas Instruments and its subsidiaries (I) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. ll products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. I warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with I s standard warranty. esting and other quality control techniques are utilized to the extent I deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERIN PPLICIONS USING SEMICONDUCOR PRODUCS M INVOLVE POENIL RISKS OF DEH, PERSONL INJUR, OR SEVERE PROPER OR ENVIRONMENL DMGE ( CRIICL PPLICIONS ). I SEMICONDUCOR PRODUCS RE NO DESIGNED, UHORIZED, OR WRRNED O BE SUIBLE FOR USE IN LIFE-SUPPOR DEVICES OR SSEMS OR OHER CRIICL PPLICIONS. INCLUSION OF I PRODUCS IN SUCH PPLICIONS IS UNDERSOOD O BE FULL HE CUSOMER S RISK. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. I assumes no liability for applications assistance or customer product design. I does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of I covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. I s publication of information regarding any third party s products or services does not constitute I s approval, warranty or endorsement thereof. Copyright 998, exas Instruments Incorporated
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Functionally Equivalent to AMD s AM2982 Improved I OH Specificatio Multiple Output Enables Allow Multiuser Control of the Interface Outputs Have Undershoot-Protection Circuitry Power-Up High-Impedance
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Inputs Are TTL Compatible EPIC (Enhanced-Performance Implanted CMOS) -µm Process Package Optio Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and DIP (N)
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Eight High-Current Latches in a Single Package High-Current -State True s Can Drive up to LSTTL Loads Full Parallel Access for Loading Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline
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Featuring Unitrode L and LD Products Now From Texas Instruments Wide Supply-Voltage Range:.5 V to V Separate Input-Logic Supply Internal ESD Protection Thermal Shutdown High-Noise-Immunity Inputs Functional
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4AC64, 74AC64 6-BIT BUS TRANSCEIVERS SCAS3A MARCH 990 REVISED APRIL 996 Members of the Texas Itruments Widebus Family 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers Flow-Through Architecture
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Member of Texas Instruments Widebus Family State-of-the-Art Advanced Low-Voltage BiCMOS (ALB) Technology Design for.-v Operation Schottky Diodes on All s to Eliminate Overshoot and Undershoot Industry
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Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and GND Configuratio Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-µm
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Member of the Texas Itruments idebus Family Load Clock and Unload Clock Can Be Asynchronous or Coincident 256 ords by 18 Bits Low-Power Advanced CMOS Technology Full, Empty, and Half-Full Flags Programmable
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4.5-V to 5.5-V V CC Operation Fanout (Over Temperature Range) Standard s... 0 LSTTL Loads Bus-Driver s... 5 LSTTL Loads Wide Operating Temperature Range of 55 C to 25 C Balanced Propagation Delays and
More informationEN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at ore.hu.
EN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at www.hest ore.hu. Convert TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping
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74ACT62 Independent Registers and Enables for A and B Buses Multiplexed Real-Time and Stored Data Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and Configuratio Minimize High-Speed Switching
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Inputs Are TTL-Voltage Compatible EPIC (Enhanced-Performance Implanted CMOS) Process Contain Six Flip-Flops With Single-Rail s Applicatio Include: Buffer/Storage Registers Shift Registers Pattern Generators
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3-State s Drive Bus Lines Directly PNP s Reduce dc Loading on Bus Lines Hysteresis at Bus s Improves Noise Margins Typical Propagation Delay Times Port to Port, 8 ns TYPE IOL (SINK CURRENT) IOH (SOURCE
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Member of Texas Instruments Widebus Family Latch-Up Performance Exceeds 250 ma Per JESD 17 description This 16-bit (dual-octal) noninverting bus transceiver contains two separate supply rails; B port has
More informationdescription V CC 2CLR 2D 2CLK 2PRE 2Q 2Q 1CLR 1D 1CLK 1PRE 1Q 1Q GND 2CLR 1CLR 1CLK NC 1PRE NC 1Q 2CLK 2PRE GND
Package Optio Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs TYPE TYPICAL MAXIMUM CLOCK FREUEY (CL = 0 pf) (MHz) TYPICAL POWER
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Dual Versions of Highly Stable SN542 and SN742 One Shots SN5422 and SN7422 Demonstrate Electrical and Switching Characteristics That Are Virtually Identical to the SN542 and SN742 One Shots Pinout Is Identical
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-State Buffer-Type s Drive Bus Lines Directly Bus-Structured Pinout Package Optio Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), Standard Plastic (N) and Ceramic (J) 00-mil DIPs,
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Member of the Texas Instruments Widebus Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process UBT (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in
More informationdescription 1G 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND V CC 2G/2G 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 1Y1 2A4 1Y2 2A3 1Y3 1A2 2Y3 1A3 2Y2 1A4 2A2 2G/2G 2Y1
SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244 3-State s Drive Bus Lines or Buffer Memory Address Registers PNP s Reduce DC Loading Hysteresis at s Improves Noise Margins description These
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Compatible with TTL Inputs High-Speed Switching... Mbit/s Typ Bandwidth...2 MHz Typ High Common-Mode Transient Immunity... 000 V/µs Typ High-Voltage Electrical Insulation... 3000 Vdc Min Open-Collector
More informationIMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the
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Power-On Reset Generator Automatic Reset Generation After Voltage Drop Output Defined From V CC 1 V Precision Voltage Seor Temperature-Compeated Voltage Reference True and Complement Reset Outputs Externally
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Equivalent Input Noise Voltage 5 nv/ Hz Typ at 1 khz Unity-Gain Bandwidth... 10 MHz Typ Common-Mode Rejection Ratio... 100 db Typ High dc Voltage Gain... 100 V/mV Typ Peak-to-Peak Output Voltage Swing
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