TL7702B, TL7705B, TL7702BY, TL7705BY SUPPLY VOLTAGE SUPERVISORS

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1 Power-On Reset Generator Automatic Reset Generation After Voltage Drop Output Defined From V CC 1 V Precision Voltage Seor Temperature-Compeated Voltage Reference True and Complement Reset Outputs Externally Adjustable Pulse Duration description The TL7702B and TL7705B are monolithic integrated circuit voltage supervisors designed for use as reset conollers in microcomputer and microprocessor systems. The supply voltage supervisor monitors the supply for undervoltage conditio at the input. During power up, the output becomes active (low) when V CC attai a value approaching 1 V. As V CC approaches 3 V (assuming that is above V T+ ), the delay timer function activates a time delay after which outputs and go CT TL77xxBC... P OR D PACKAGE TL77xxBM... JG PACKAGE (TOP VIEW) REF CT inactive (high and low respectively). When an undervoltage condition occurs during normal operation, outputs and go active. To eure that a complete reset occurs, the reset outputs remain active for a time delay after the voltage at the input exceeds the positive-going threshold value. The time delay is determined by the value of the external capacitor C T : t d C T, where C T is in farads (F) and t d is in seconds (s). An external capacitor (typically 0.1 µf) must be connected to REF to reduce the influence of fast aients in the supply voltage. The TL7702BC and TL7705BC are characterized from 0 C to 70 C. The TL7702BI and TL7705BI are characterized for operation from 40 C to 85 C. The TL7702BQ and TL7705BQ are characterized for operation from 40 C to 125 C. The TL7702BM and TL7705BM are characterized for operation from 55 C to 125 C TL77xxBM... FK PACKAGE (TOP VIEW) REF V CC No internal connection V CC TA SMALL OUTLINE (D) AVAILABLE OPTIONS CHIP CARRIER (FK) PACKAGE CERAMIC DIP (JG) PLASTIC DIP (P) 0 C to 70 C TL7702BCD, TL7705BCD TL7702BCP, TL7705BCP 40 C to 85 C TL7702BID, TL7705BID TL7702BIP, TL7705BIP 40 C to 125 C TL7702BQD, TL7705BQD TL7702BQP, TL7705BQP 55 C to 125 C TL7702BMFK TL7705BMFK TL7702BMJG TL7705BMJG CHIP FORM (Y) TL7702BY TL7705BY PRODUCTION DATA information is current as of publication date. Products conform to specificatio per the terms of Texas Iuments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 1995, Texas Iuments Incorporated POST OFFICE BOX DALLAS, TEXAS

TL7702BY and TL7705BY chip information These chips, when properly assembled, display characteristics similar to the TL7702BC and the TL7705BC.

2 TL7702BY and TL7705BY chip information These chips, when properly assembled, display characteristics similar to the TL7702BC and the TL7705BC. Thermal compression or ulasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with conductive epoxy or a gold-silicon preform. BONDING PAD ASSIGNMENTS (1) (8) (7) REF CT (1) (2) (3) (4) TL77xxBY (8) (7) () (5) VCC 81 (2) (3) () CHIP THICKNESS: 15 MILS TYPICAL BONDING PADS: 4 4 MILS MINIMUM TJmax = 150 C TOLERAES ARE ±10% ALL DIMENSIONS ARE IN MILS (4) (5) POST OFFICE BOX DALLAS, TEXAS 7525

3 functional block diagram The functional block diagram is shown for illusative purposes only; the actual circuit includes a imming network to adjust the reference voltage and see comparator ip point. VCC 8 Reference Voltage 100 µa CT 3 7 R1 (see Note A) 5 R2 (see Note A) REF NOTE A: TL7702B: R1 = 0 Ω, R2 = open TL7705B: R1 = 23 kω, R2 = 10 kω, nominal typical timing diagram VCC and VIT+ VIT VIT+ VIT Vres Vres 0 td td ÎÎÎÎ Output Undefined 0 ÎÎÎÎÎ Output ÎÎÎÎÎ Undefined POST OFFICE BOX DALLAS, TEXAS

4 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, V CC (see Note 1) V Input voltage range, V I () V to 20 V Input voltage range, V I () V to 20 V High-level output current, I OH () ma Low-level output current, I OL () ma Continuous total power dissipation See Dissipation Rating Table Operating free-air temperature range, T A : TL770xBC C to 70 C TL770xBl C to 85 C TL770xBQ C to 125 C TL770xBM C to 125 C Storage temperature range, T stg C to 150 C Case temperature for 0 seconds, T C : FK package C Lead temperature 1, mm (1/1 inch) from case for 0 seconds: JG package C Lead temperature 1, mm (1/1 inch) from case for 10 seconds: D or P packages C Sesses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are sess ratings only, and functional operation of the device at these or any other conditio beyond those indicated under recommended operating conditio is not implied. Exposure to absolute-maximum-rated conditio for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to the network ground terminal. PACKAGE TA 25 C POWER RATING DISSIPATION RATING TABLE DERATING FACTOR ABOVE TA = 25 C TA = 70 C POWER RATING TA = 85 C POWER RATING TA = 125 C POWER RATING D 725 mw 5.8 mw/ C 44 mw 377 mw 145 mw FK 1375 mw 11.0 mw/ C 880 mw 715 mw 275 mw JG 1050 mw 8.4 mw/ C 72 mw 54 mw 210 mw P 1000 mw 8.0 mw/ C 40 mw 520 mw 200 mw recommended operating conditio MIN MAX Supply voltage, VCC V High-level input voltage, VIH 2 18 V Low-level input voltage, VIL V Input voltage, VI 0 18 V High-level output current, IOH 1 ma Low-level output current, IOL 1 ma Timing capacitor, CT 10 µf Operating free-air temperature range, TA TL770xBC 0 70 TL770xBI TL770xBQ TL770xBM C 5 4 POST OFFICE BOX DALLAS, TEXAS 7525

5 elecical characteristics over recommended operating conditio (unless otherwise noted) TEST CONDITIONS TL77xxBC, TL77xxBI TL77xxBQ VOH High-level output voltage, IOH = 1 ma VCC 1.5 V VOL Low-level output voltage, IOL = 1 ma 0.4 V Vref Reference voltage Iref = 500 µa, TA = 25 C VIT TL7702B =25 C Negative-going input threshold TL7705B T A g g voltage, TL7702B TL7705B T A = Full range Vhys Hysteresis, (VIT+ VIT ) V TL7702B VCC = 3. V to 18 V, 10 TL7705B TA = 25 C 30 Vres Power-up reset voltage IOL at = 2 ma, TA = 25 C 1 V II Input current, VI = 0.4 V to VCC 10 µa II Input current, TL7702B VI = Vref to 18 V µa IOH High-level output current, VO = 18 V, See Figure 1 50 µa IOL Low-level output current, VO = 0 V, See Figure 1 50 µa ICC Supply current V = 15 V, 2 V VCC = 18 V TA = Full range 3.5 All elecical characteristics are measured with 0.1-µF capacitors connected at REF, CT, and VCC to. Full range for the C-suffix device is 0 C to 70 C, full range for the I-suffix is 40 C to 85 C, and full range for the Q-suffix device is 40 C to 125 C. This is the lowest voltage at which becomes active. switching characteristics, V CC = 5 V, CT open, T A = 25 C tplh tphl tw low-to-high-level output high-to-low-level output Effective pulse duration Rise time Fall time Rise time Fall time FROM (INPUT) TO (OUTPUT) TEST CONDITIONS See Figures 1, 2, and 3 TL77xxBC, TL77xxBI TL77xxBQ See Figure See Figure See Figures 1 and 3 mv ma POST OFFICE BOX DALLAS, TEXAS

6 elecical characteristics over recommended operating conditio (unless otherwise noted) TEST CONDITIONS TL7702BM, TL7705BM VOH High-level output voltage, IOH = 1 ma VCC 1.5 V VOL Low-level output voltage, IOL = 1 ma 0.4 V Vref Reference voltage Iref = 500 µa, TA = 25 C VIT TL7702B =25 C Negative-going input threshold TL7705B T A g g voltage at input TL7702B TL7705B T A = Full range Vhys Hysteresis, (VIT + VIT ) V TL7702B VCC = 3. V to 18 V, 10 TL7705B TA = 25 C 30 Vres Power-up reset voltage IOL at = 2 ma, TA = 25 C 1 V II Input current, VI = 0.4 V to VCC 10 µa II Input current, TL7702B VI = Vref to VCC 1.5 V µa IOH High-level output current, VO = 18 V 50 µa IOL Low-level output current, VO = 0 50 µa ICC Supply current V = 15 V, 2 V VCC = 18 V TA = Full range 4 All elecical characteristics are measured with 0.1-µF capacitors connected at REF, CT, and VCC to. Full range for the M-suffix device is 55 C to 125 C. This is the lowest value at which becomes active. switching characteristics, V CC = 5 V, CT open, T A = 25 C tplh tphl tw FROM TO (INPUT) (OUTPUT) low-to-high-level output high-to-low-level output Effective pulse duration TEST CONDITIONS See Figures 1, 2, and 3 TL7702BM, TL7705BM See Figure See Figure Rise time Fall time See Figures 1 and 3 Rise time Fall time *For products compliant to MIL-STD-883, Class B, these parameters are not production tested. mv ma * * 75* * * 50* 5 POST OFFICE BOX DALLAS, TEXAS 7525

7 elecical characteristics over recommended operating conditio, T A = 25 C (unless otherwise noted) TEST CONDITIONS TL7702Y, TL7705Y VOH High-level output voltage, IOH = 1 ma VCC 1.5 V VOL Low-level output voltage, IOL = 1 ma 0.4 V Vref Reference voltage Iref = 500 µa VIT Negative-going g ginput threshold TL7702Y V voltage, TL7705Y Vhys Hysteresis, (VIT+ VIT ) TL7702Y TL7705Y V CC =3Vto18V 3. V Vres Power-up reset voltage IOL at = 2 ma 1 V II Input current, VI = 0.4 V to VCC 10 µa II Input current, TL7702Y VI = Vref to 18 V µa IOH High-level output current, VO = 18 V, See Figure 1 50 µa IOL Low-level output current, VO = 0 V, See Figure 1 50 µa ICC Supply current V = 15 V, 2 V ma All elecical characteristics are measured with 0.1-µF capacitors connected at REF, CT, and VCC to. This is the lowest voltage at which becomes active. switching characteristics, V CC = 5 V, CT open, T A = 25 C tplh tphl tw low-to-high-level output high-to-low-level output Effective pulse duration Rise time Fall time Rise time Fall time FROM (INPUT) TO (OUTPUT) TEST CONDITIONS See Figures 1, 2, and TL7702Y, TL7705Y See Figure See Figure See Figures 1 and 3 mv POST OFFICE BOX DALLAS, TEXAS

8 MEASUREMENT INFORMATION 5 V RL (see Note A) DUT 5 V VCC DUT 15 pf (see Note B) RL (see Note A) 15 pf (see Note B) OUTPUT CONFIGURATION OUTPUT CONFIGURATION NOTES: A. For IOL and IOH, RL = 10 kω. For all switching characteristics, RL = 511 Ω. B. This figure includes jig and probe capacitance. Figure 1. and Output Configuratio tw 5 V 2.5 V 0 V WAVEFORMS tw VT + 2 V VT VT 2 V Figure 2. Input Pulse Definition Voltage Fault VIT+ VIT VIT+ 0 V Undefined 90% td 10% td 0.8 V 2 V VIH VIL tplh 90% 90% V OH 50% ÎÎÎ td 10% 90% 10% 10% 50% 10% VOL tphl Figure 3. Voltage Waveforms 5 8 POST OFFICE BOX DALLAS, TEXAS 7525

9 TYPICAL CHARACTERISTICS ASSERTION TIME vs LOAD RESISTAE DEASSERTION TIME vs LOAD RESISTAE VCC = 5 V CT = 0.1 µf CL = 10 pf TA = 25 C 00 VCC = 5 V CT = 0.1 µf CL = 10 pf TA = 25 C t Assertion Time t Deassertion Time RL Load Resistance kω RL Load Resistance kω Figure 4 Figure 5 ASSERTION TIME vs LOAD CAPACITAE DEASSERTION TIME vs LOAD CAPACITAE VCC = 5 V CT = 0.1 µf RL = 4.7 kω TA = 25 C µ s VCC = 5 V CT = 0.1 µf RL = 4.7 kω TA = 25 C t Assertion Time t Deassertion Time and CL Load Capacitance pf CL Load Capacitance pf Figure Figure 7 For proper operation, both and should be terminated with resistors of similar value. Failure to do so may cause unwanted plateauing in either output waveform during switching. POST OFFICE BOX DALLAS, TEXAS

10 APPLICATION INFORMATION VS System Supply 8 10 kω Reset Input (from system) 0.1 µf RT 3 (see Text) CT VCC REF CT kω To System Reset To System Reset Figure 8. System Reset Conoller With Undervoltage Seing When the TL770xB terminal is used to monitor V CC, a current-limiting resistor in series with C T is recommended. During normal operation, the timing capacitor is charged by the on-board current source to approximately V CC or an internal voltage clamp ( 7.1-V zener), whichever is less. When the circuit is then subjected to an undervoltage condition during which V CC is rapidly slewed down, the voltage on CT exceeds that on V CC. This forward biases a secondary path internally, which falsely activates the outputs. A fault is indicated when V CC drops below V (CT), not when V falls below V T. Texas Iuments performs a 100% elecical screen to verify that the outputs do not switch with 1 ma forced into the CT terminal. Adding the external resistor, R T, prevents false iggering. Its value is calculated as follows: V (CT) V T R T 1mA where: V (CT) = V CC or 7.1 V, whichever is less V T = 4.55 V (nom) R T = value of series resistor required for V CC = 5 V: R T 1mA Therefore, R T > 450 Ω Using a 20% tolerance resistor, R T should be greater than 50 Ω. Adding this series resistor changes the duration of the reset pulse by no more than 10%. R T extends the discharge of C T, but also skews the V (CT) threshold. These effects tend to cancel one another. The precise percentage change can be derived theoretically, but the equation is complicated by this interaction and is dependent upon the duration of the supply voltage fault condition. Both outputs of the TL770xB should be terminated with similar value resistors, even when only one is being used. This prevents unwanted plateauing in either output waveform during switching, which may be interpreted as an undefined state or delay system reset POST OFFICE BOX DALLAS, TEXAS 7525

11 IMPORTANT NOTICE Texas Iuments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. TI warrants performance of its semiconductor products and related software to the specificatio applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality conol techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applicatio using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage ( Critical Applicatio ). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. Inclusion of TI products in such applicatio is understood to be fully at the risk of the customer. Use of TI products in such applicatio requires the written approval of an appropriate TI officer. Questio concerning potential risk applicatio should be directed to TI through a local SC sales office. In order to minimize risks associated with the customer s applicatio, adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applicatio assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does TI warrant or represent that any licee, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. Copyright 199, Texas Iuments Incorporated

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