74ACT11374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
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1 Eight D-Type Flip-Flops in a Single Package -State Bus Driving True s Full Parallel Access for Loading Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) -m Process 500-mA Typical Latch-Up Immunity at 25 C Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages, and Standard Plastic 00-mil DIPs (NT) DB, DW, OR NT PACKAGE (TOP VIEW) Q 2Q Q 4Q 5Q 6Q 7Q 8Q D D 4D V CC V CC 5D 6D 7D 8D description This 8-bit flip-flop features -state outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight flip-flops of the 74ACT74 are edge-triggered D-type flip-flops. On the positive transition of the clock () input, the Q outputs are set to the logic levels set up at the data (D) inputs. An output-enable () input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance third state provides the capability to drive bus lines in a bus-organized system without need for interface or pullup components. does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The 74ACT74 is characterized for operation from 40 C to 85 C. FUNCTION TABLE (each flip-flop) INPUTS OUTPUT D Q L H H L L L L L X Q0 L H X Q0 L X Q0 H X X Z Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 996, Texas Instruments Incorporated POST OFFICE BOX 6550 DALLAS, TEXAS 75265
2 logic symbol 24 EN 2D D 4D 5D 6D 7D 8D Q 2Q Q 4Q 5Q 6Q 7Q 8Q This symbol is in accordance with ANSI/IEEE Std and IEC Publication logic diagram (positive logic) 24 2 Q 2D Q D 2 Q 4D Q 5D 7 9 5Q 6D 6 0 6Q 7D 5 7Q 8D 4 2 8Q 2 POST OFFICE BOX 6550 DALLAS, TEXAS 75265
3 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V CC V to 7 V Input voltage range, V I (see Note ) V to V CC V voltage range, V O (see Note ) V to V CC V Input clamp current, I IK (V I < 0 or V I > V CC ) ±20 ma clamp current, I OK (V O < 0 or V O > V CC ) ±50 ma Continuous output current, I O (V O = 0 to V CC ) ±50 ma Continuous current through V CC or ±200 ma Maximum power dissipation at T A = 55 C (in still air) (see Note 2): DB package W DW package W NT package W Storage temperature range, T stg C to 50 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES:. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 50 C and a board trace length of 750 mils, except for the NT package, which has a trace length of zero. recommended operating conditions VCC Supply voltage V VIH High-level input voltage 2 V VIL Low-level input voltage 0.8 V VI Input voltage CC V VO voltage CC V IOH High-level output current 24 ma IOL Low-level output current 24 ma t/v Input transition rise or fall rate 0 0 ns/v TA Operating free-air temperature C POST OFFICE BOX 6550 DALLAS, TEXAS 75265
4 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = 50 A IOH = 24 ma TA = 25 C MIN TYP MAX 4.5 V V V.94.8 V 5.5 V IOH = 75 ma 5.5 V.85 IOL =50A IOL =24mA 4.5 V V V V 5.5 V IOL = 75 ma 5.5 V.65 IOZ VO = VCC or 5.5 V ±0.5 ±5 A II VI = VCC or 5.5 V ±0. ± A ICC VI = VCC or, IO = V 8 80 A ICC One input at.4 V, Other inputs at or V CC 5.5 V 0.9 ma Ci VI = VCC or 5 V 4 pf Co VO = VCC or 5 V 0 pf Not more than one output should be tested at a time, and the duration of the test should not exceed 0 ms. This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than or VCC. timing requirements over recommended ranges of supply voltages and operating free-air temperature (unless otherwise noted) (see Figure ) TA = 25 C MIN MAX fclock Clock frequency MHz tw Pulse duration, low or high 9 9 ns tsu Setup time, data before ns th Hold time, data after ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure ) PARAMETER FROM TO TA = 25 C (INPUT) (OUTPUT) MIN TYP MAX fmax MHz tplh tphl tpzh tpzl tphz tplz Any Q Any Q Any Q ns ns ns 4 POST OFFICE BOX 6550 DALLAS, TEXAS 75265
5 operating characteristics, V CC = 5 V, T A = 25 C Cpdd PARAMETER TEST CONDITIONS TYP UNIT s enabled 07 Power dissipation capacitance per flip-flop flop CL =50pF pf, f=mhz pf s disabled 96 PARAMETER MEASUREMENT INFORMATION 2 VCC From Under Test CL = 50 pf (see Note A) 500 Ω 500 Ω S Open TEST tplh/tphl tplz/tpzl tphz/tpzh S Open 2 VCC LOAD CIRCUIT Timing Input Input tw Data Input tsu th Input In-Phase Out-of-Phase tplh tphl tphl tplh Control (low-level enabling) Waveform S at 2 VCC (see Note B) Waveform 2 S at (see Note B) tpzl tpzh tplz tphz 20% VCC 80% VCC VCC NOTES: A. CL includes probe and jig capacitance. B. Waveform is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR MHz, ZO = 50 Ω, tr = ns, tf = ns. D. The outputs are measured one at a time with one input transition per measurement. Figure. Load Circuit and Voltage Waveforms POST OFFICE BOX 6550 DALLAS, TEXAS
6 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ( CRITICAL APPLICATIONS ). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not constitute TI s approval, warranty or endorsement thereof. Copyright 998, Texas Instruments Incorporated
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SN54LS373, SN54LS374, SN54S373, SN54S374, Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving s Full Parallel Access for Loading Buffered Control s Clock-Enable Has
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Operates With Single -V Power Supply LinBiCMOS Process Technology Two Drivers and Two Receivers ± 0-V Input Levels Low Supply Current...8 ma Typical Meets or Exceeds TIA/EIA-22-F and ITU Recommendation
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Inputs Are TTL-Voltage ompatible EPI (Enhanced-Performance Implanted MOS) Process ontain Eight Flip-Flops With Single-ail s Direct lear Input Individual Data Input to Each Flip-Flop Applicatio Include:
More informationSN54ALS244C, SN54AS244A, SN74ALS244C, SN74AS244A OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
SNALS2C, SNAS2A, SNALS2C, SNAS2A SDAS2C JUL 9 REISED AUGUST 99 -State Outputs Drive Bus Lines or Buffer Memory Address Registers pnp Inputs Reduce dc Loading Package Optio Include Plastic Small-Outline
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3-State s Drive Bus Lines Directly PNP s Reduce dc Loading on Bus Lines Hysteresis at Bus s Improves Noise Margins Typical Propagation Delay Times Port to Port, 8 ns TYPE IOL (SINK CURRENT) IOH (SOURCE
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PERIPHERAL DRIVERS FOR HIGH-CURRENT SWITCHING AT VERY HIGH SPEEDS Characterized for Use to 00 ma High-Voltage Outputs No Output Latch-Up at 0 V (After Conducting 00 ma) High-Speed Switching Circuit Flexibility
More informationEN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at ore.hu.
EN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at www.hest ore.hu. Convert TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping
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s Are TTL-Voltage ompatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power onsumption Balanced Propagation Delays ±24-mA Drive urrent Fanout to 5 F Devices SR-Latchup-Resistant MOS Process
More information1OE 3B V GND ORDERING INFORMATION. TOP-SIDE MARKING QFN RGY Tape and reel SN74CBTLV3126RGYR CL126 PACKAGE
SN74CBTLV326 LOW-VOLTAGE QUADRUPLE FET BUS SWITCH SCDS03H DECEMBER 997 REVISED APRIL 2003 Standard 26-Type Pinout 5-Ω Switch Connection Between Two Ports Isolation Under Power-Off Conditions Latch-up Performance
More informationSN54AHC573, SN74AHC573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
Operating Range 2-V to 5.5-V V CC 3-State s Directly Drive Bus Lines Latch-Up Performance Exceeds 250 ma Per JESD 17 description The AHC573 devices are octal traparent D-type latches designed for 2-V to
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Compatible With IEEE Std 1194.1-1991 (TL) TTL A Port, ackplane Traceiver Logic (TL) Port Open-Collector -Port Outputs Sink 100 ma IAS V CC Pin Minimizes Signal Distortion During Live Iertion or Withdrawal
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Meet or Exceed the Requirements of TIA/EIA-232-F and ITU Recommendation V.28 Very Low Power Consumption... 5 mw Typ Wide Driver Supply Voltage Range... ±4.5 V to ±15 V Driver Output Slew Rate Limited to
More informationdescription 1G 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND V CC 2G/2G 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 1Y1 2A4 1Y2 2A3 1Y3 1A2 2Y3 1A3 2Y2 1A4 2A2 2G/2G 2Y1
SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244 3-State s Drive Bus Lines or Buffer Memory Address Registers PNP s Reduce DC Loading Hysteresis at s Improves Noise Margins description These
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8-Bit Counter With egister High-Current 3-State Parallel egister Outputs Can Drive up to 15 LSL Loads Counter Has Direct Clear Package Options Include Plastic Small-Outline (D, DW), and Ceramic Flat (W)
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Meets or Exceeds the Requirement of ANSI EIA/TIA-232-E and ITU Recommendation V.28 Withstands Sustained Output Short Circuit to Any Low-Impedance Voltage Between 25 V and 25 V 2-µs Max Transition Time
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SN676B, SN776B Bidirectional Transceivers Meet or Exceed the Requirements of ANSI Standards TIA/EIA--B and TIA/EIA-8-A and ITU Recommendations V. and X.7 Designed for Multipoint Transmission on Long Bus
More informationDistributed by: www.jameco.com 1-800-81-4242 The content and copyrights of the attached material are the property of its owner. Operating Range 2-V to.-v V CC Latch-Up Performance Exceeds 20 ma Per JESD
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WITH LEAR AND PRESET SDFS0A MARH 197 REVISED OTOBER 199 Package Optio Include Plastic Small-Outline Packages, eramic hip arriers, and Standard Plastic and eramic 00-mil DIPs description These devices contain
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Meets or Exceeds the Requirements of ANSI EIA/TIA-232-E and ITU Recommendation V.28 Single Chip With Easy Interface Between UART and Serial Port Connector Less Than 9-mW Power Consumption Wide Driver Supply
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Meets or Exceeds the Requirements of TIA/EIA-232-F and ITU Recommendation V.28 Single Chip With Easy Interface Between UART and Serial-Port Connector Less Than 9-mW Power Consumption Wide Driver Supply
More informationULN2804A DARLINGTON TRANSISTOR ARRAY
HIGH-VOLTAGE, HIGH-CURRENT 500-mA-Rated Collector Current (Single ) High-Voltage s...50 V Clamp Diodes Inputs Compatible With Various Types of Logic Relay Driver Applications Compatible With ULN2800A-Series
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EPIC (Enhanced-Performance Implanted CMOS) Process Operating Range 2-V to 5.5-V V CC Schmitt-Trigger Circuitry On A, B, and CLR Inputs for Slow Input Traition Rates Edge Triggered From Active-High or Active-Low
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SLRS28 SEPTEMBER 1988 Quadruple Circuits Capable of Driving High-Capacitance Loads at High Speeds Output Supply Voltage Range From 5 V to 24 V Low Standby Power Dissipation V CC3 Supply Maximizes Output
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SLRSB DECEMBER REVISED SEPTEMBER HIGH-VOLTAGE HIGH-CURRENT -ma Rated Collector Current (Single ) High-Voltage s... V Clamp Diodes Inputs Compatible With Various Types of Logic Relay Driver Applications
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8-Bit Resolution Linearity... ±1/2 LSB Maximum Differential Nonlinearity...±1/2 LSB Maximum Conversion Rate...60 MHz Min Nominal Output Signal Operating Range V CC to V CC 1 V TTL Digital Input Voltage
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Operating Range 2-V to 5.5-V V CC Latch-Up Performance Exceeds 250 m Per JESD 17 description The SN74HC1G04 contai one inverter gate. The device performs the Boolean function =. DBV OR DCK PCKGES (TOP
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Dual Versions of Highly Stable SN542 and SN742 One Shots SN5422 and SN7422 Demonstrate Electrical and Switching Characteristics That Are Virtually Identical to the SN542 and SN742 One Shots Pinout Is Identical
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Meet or Exceed the Requirements of ANSI EIA/TIA-232-E and ITU Recommendation V.28 Very Low Power Consumption 5 mw Typ Wide Driver Supply Voltage Range ±4.5 V to ±15 V Driver Output Slew Rate Limited to
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2-V to 5.5-V V CC Operation Typical V OLP (Output Ground Bounce) 2.3 V at V CC = 3.3 V, T A = 25 C Support Mixed-Mode Voltage
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Support the ME64 ETL Specification Reduced, TTL-Compatible, Input Threshold Range High-Drive Outputs (I OH = 60 m, I OL = 90 m) Support 25-Ω Incident-Wave Switching CC IS Pin Minimizes Signal Distortion
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Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max t pd of 5.5 ns at 3.3 V Output Ports Have Equivalent 26-Ω Series Resistors, So No External Resistors Are Required Typical V OLP (Output
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Dependable Texas Instruments Quality and Reliability description These devices contain six independent inverters. SN5404, SN54LS04, SN54S04, SN5404... J PACKAGE SN54LS04, SN54S04... J OR W PACKAGE SN7404...
More informationIMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the
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