SN65176B, SN75176B DIFFERENTIAL BUS TRANSCEIVERS
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1 SN676B, SN776B Bidirectional Transceivers Meet or Exceed the Requirements of ANSI Standards TIA/EIA--B and TIA/EIA-8-A and ITU Recommendations V. and X.7 Designed for Multipoint Transmission on Long Bus Lines in Noisy Environments -State Driver and Receiver s Individual Driver and Receiver Enables Wide Positive and Negative / Bus Voltage Ranges Driver Capability...±6 ma Max Thermal Shutdown Protection Driver Positive and Negative Current Limiting Receiver Impedance... kω Min Receiver Sensitivity...± mv Receiver Hysteresis... mv Typ Operate From Single -V Supply R RE DE D SLLSB JULY 98 REVISED JUNE 999 D OR P PACKAGE (TOP VIEW) V CC B A GND description The SN676B and SN776B differential bus transceivers are monolithic integrated circuits designed for bidirectional data communication on multipoint bus transmission lines. They are designed for balanced transmission lines and meet ANSI Standards TIA/EIA--B and TIA/EIA-8-A and ITU Recommendations V. and X.7. The SN676B and SN776B combine a -state differential line driver and a differential input line receiver, both of which operate from a single -V power supply. The driver and receiver have active-high and active-low enables, respectively, that can be connected together externally to function as a direction control. The driver differential outputs and the receiver differential inputs are connected internally to form differential input/output (I/O) bus ports that are designed to offer minimum loading to the bus when the driver is disabled or V CC =. These ports feature wide positive and negative common-mode voltage ranges, making the device suitable for party-line applications. The driver is designed for up to 6 ma of sink or source current. The driver features positive and negative current limiting and thermal shutdown for protection from line-fault conditions. Thermal shutdown is designed to occur at a junction temperature of approximately C. The receiver features a minimum input impedance of kω, an input sensitivity of ± mv, and a typical input hysteresis of mv. The SN676B and SN776B can be used in transmission-line applications employing the SN77 and SN77 quadruple differential line drivers and SN77 and SN77 quadruple differential line receivers. The SN676B is characterized for operation from C to C and the SN776B is characterized for operation from C to 7 C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 999, Texas Instruments Incorporated POST OFFICE BOX 6 DALLAS, TEXAS 76
2 SN676B, SN776B SLLSB JULY 98 REVISED JUNE 999 Function Tables DRIVER INPUT ENABLE OUTPUTS D DE A B H H H L L H L H X L Z Z RECEIVER DIFFERENTIAL INPUTS ENABLE OUTPUT A B RE R VID. V L H. V < VID <. V L? VID. V L L X H Z Open L? H = high level, L = low level,? = indeterminate, X = irrelevant, Z = high impedance (off) logic symbol logic diagram (positive logic) DE RE D EN EN 6 7 A B DE D RE R 6 7 A B Bus R This symbol is in accordance with ANSI/IEEE Std 9-98 and IEC Publication 67-. POST OFFICE BOX 6 DALLAS, TEXAS 76
3 SN676B, SN776B SLLSB JULY 98 REVISED JUNE 999 schematics of inputs and outputs EQUIVALENT OF EACH INPUT TYPICAL OF A AND B I/O PORTS TYPICAL OF RECEIVER OUTPUT VCC R(eq) VCC VCC 8 Ω NOM 6.8 kω NOM 96 Ω NOM 96 Ω NOM Driver input: R(eq) = kω NOM Enable inputs: R(eq )= 8 kω NOM R(eq) = equivalent resistor / Port GND absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, V CC (see Note ) V Voltage range at any bus terminal V to V Enable input voltage, V I V Package thermal impedance, θ JA (see Note ): D package C/W P package C/W Lead temperature,6 mm (/6 inch) from case for seconds C Storage temperature range, T stg C to C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES:. All voltage values, except differential input/output bus voltage, are with respect to network ground terminal.. The package thermal impedance is calculated in accordance with JESD, except for through-hole packages, which use a trace length of zero. recommended operating conditions MIN TYP MAX UNIT Supply voltage, VCC.7. V Voltage at any bus terminal (separately or common mode), VI or VIC High-level input voltage, VIH D, DE, and RE V Low-level input voltage, VIL D, DE, and RE.8 V Differential input voltage, VID (see Note ) ± V High-level output current, IOH Low-level output current, IOL Operating free-air temperature, TA 7 V Driver 6 ma Receiver µa Driver 6 Receiver 8 SN676B SN776B 7 NOTE : Differential-input/output bus voltage is measured at the noninverting terminal A with respect to the inverting terminal B. ma C POST OFFICE BOX 6 DALLAS, TEXAS 76
4 SN676B, SN776B SLLSB JULY 98 REVISED JUNE 999 DRIVER SECTION electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIK clamp voltage II = 8 ma. V VO voltage IO = 6 V VOD Differential output voltage IO =..6 6 V VOD Differential output voltage RL = Ω, See Figure / VOD or RL = Ω, See Figure.. V VOD Differential output voltage See Note. V VOD Change in magnitude of differential output ±. V voltage VOC Common-mode mode output voltage RL = Ωor Ω, See Figure VOC IO Change in magnitude of common-mode ±. V output voltage current + disabled, VO = V See Note VO = 7 V.8 IIH High-level input current VI =. V µa IIL Low-level input current VI =. V µa IOS Short-circuit output current ICC Supply current (total package) No load VO = 7 V VO = VO = VCC VO = V s enabled 7 s disabled 6 The power-off measurement in ANSI Standard TIA/EIA--B applies to disabled outputs only and is not applied to combined inputs and outputs. All typical values are at and TA = C. VOD and VOC are the changes in magnitude of VOD and VOC, respectively, that occur when the input is changed from a high level to a low level. The minimum VOD with a -Ω load is either / VOD or V, whichever is greater. NOTES:. See ANSI Standard TIA/EIA-8-A, Figure., Test Termination Measurement.. This applies for both power on and off; refer to ANSI Standard TIA/EIA-8-A for exact conditions. The TIA/EIA--B limit does not apply for a combined driver and receiver terminal. switching characteristics, V CC = V, R L = kω, T A = C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT td(od) Differential-output delay time ns RL =Ω Ω, See Figure tt(od) Differential-output transition time ns tpzh enable time to high level See Figure 8 ns tpzl enable time to low level See Figure 6 ns tphz disable time from high level See Figure ns tplz disable time from low level See Figure ns V V ma ma ma POST OFFICE BOX 6 DALLAS, TEXAS 76
5 SN676B, SN776B SYMBOL EQUIVALENTS DATA-SHEET PARAMETER TIA/EIA--B TIA/EIA-8-A VO Voa, Vob Voa, Vob VOD Vo Vo VOD Vt (RL = Ω) Vt (RL = Ω) Vt (Test Termination VOD Measurement ) VOD Vt Vt Vt Vt VOC Vos Vos VOC Vos Vos Vos Vos IOS Isa, Isb IO Ixa, Ixb Iia, Iib SLLSB JULY 98 REVISED JUNE 999 RECEIVER SECTION electrical characteristics over recommended ranges of common-mode input voltage, supply voltage, and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIT + Positive-going input threshold voltage VO =.7 V, IO =. ma. V VIT Negative-going input threshold voltage VO =. V, IO = 8 ma. V Vhys hysteresis voltage (VIT + VIT ) mv VIK Enable clamp voltage II = 8 ma. V VID = mv, VOH High-level output voltage See Figure VID = mv, VOL Low-level output voltage See Figure IOH = µa,, IOL = 8 ma, 7.7 V. V IOZ High-impedance-state output current VO =. V to. V ± µa II Line input current Other input = V, VI = V See Note 6 VI = 7 V.8 IIH High-level enable input current VIH =.7 V µa IIL Low-level enable input current VIL =. V µa ri resistance VI = V kω IOS Short-circuit output current 8 ma ICC Supply current (total package) No load s enabled s disabled 6 All typical values are at, TA = C. The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet for common-mode input voltage and threshold voltage levels only. NOTE 6: This applies for both power on and power off. Refer to EIA Standard TIA/EIA-8-A for exact conditions. ma ma POST OFFICE BOX 6 DALLAS, TEXAS 76
6 SN676B, SN776B SLLSB JULY 98 REVISED JUNE 999 switching characteristics, V CC = V, C L = pf, T A = C tplh tphl tpzh tpzl tphz tplz PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Propagation delay time, low- to high-level output ns VID = to V, See Figure 6 Propagation delay time, high- to low-level output ns enable time to high level ns See Figure 7 enable time to low level ns disable time from high level ns See Figure 7 disable time from low level 7 ns PARAMETER MEASUREMENT INFORMATION VOD RL RL VOC VID VOL +IOL VOH IOH Figure. Driver V OD and V OC Figure. Receiver V OH and V OL Generator (see Note B) Ω V RL = Ω CL = pf (see Note A). V td(od) % % tt(od) V. V V td(od) 9%. V % %. V tt(od) TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The input pulse is supplied by a generator having the following characteristics: PRR MHz, % duty cycle, tr 6 ns, tf 6 ns, ZO = Ω. Figure. Driver Test Circuit and Voltage Waveforms 6 POST OFFICE BOX 6 DALLAS, TEXAS 76
7 SN676B, SN776B SLLSB JULY 98 REVISED JUNE 999 V or V Generator (see Note B) Ω S CL = pf (see Note A) RL = Ω tpzh. V. V. V tphz V V. V VOH Voff V TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The input pulse is supplied by a generator having the following characteristics: PRR MHz, % duty cycle, tr 6 ns, tf 6 ns, ZO = Ω. Figure. Driver Test Circuit and Voltage Waveforms V or V Generator (see Note B) Ω S CL = pf (see Note A) V RL = Ω tpzl. V. V. V V V tplz V. V VOL TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The input pulse is supplied by a generator having the following characteristics: PRR MHz, % duty cycle, tr 6 ns, tf 6 ns, ZO = Ω. Figure. Driver Test Circuit and Voltage Waveforms V Generator (see Note B) Ω. V V CL = pf (see Note A) tplh. V. V. V tphl. V V VOH VOL TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The input pulse is supplied by a generator having the following characteristics: PRR MHz, % duty cycle, tr 6 ns, tf 6 ns, ZO = Ω. Figure 6. Receiver Test Circuit and Voltage Waveforms POST OFFICE BOX 6 DALLAS, TEXAS 76 7
8 SN676B, SN776B SLLSB JULY 98 REVISED JUNE 999 PARAMETER MEASUREMENT INFORMATION. V. V S kω S V CL = pf (see Note A) kω N96 or Equivalent Generator (see Note B) Ω S TEST CIRCUIT tpzh V. V V S to. V S Open S Closed tpzl V. V V S to. V S Closed S Open. V VOH V. V. V VOL. V V S to. V S Closed S Closed V. V V V S to. V S Closed S Closed tphz tplz. V VOH. V. V. V VOL VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The input pulse is supplied by a generator having the following characteristics: PRR MHz, % duty cycle, tr 6 ns, tf 6 ns, ZO = Ω. Figure 7. Receiver Test Circuit and Voltage Waveforms 8 POST OFFICE BOX 6 DALLAS, TEXAS 76
9 SN676B, SN776B TYPICAL CHARACTERISTICS SLLSB JULY 98 REVISED JUNE 999 VOH V High-Level Voltage V..... DRIVER HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT CURRENT TA = C V OL Low-Level Voltage V..... DRIVER LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT CURRENT TA = C 6 8 IOH High-Level Current ma 6 8 IOL Low-Level Current ma Figure 8 Figure 9 VOD V Differential Voltage V.... DRIVER DIFFERENTIAL OUTPUT VOLTAGE OUTPUT CURRENT TA = C IO Current ma 9 Figure POST OFFICE BOX 6 DALLAS, TEXAS 76 9
10 SN676B, SN776B SLLSB JULY 98 REVISED JUNE 999 TYPICAL CHARACTERISTICS VOH V High-Level Voltage V..... RECEIVER HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT CURRENT VID =. V TA = C VCC =.7 V Figure VCC =. V IOH High-Level Current ma VOH V High-Level Voltage V..... RECEIVER HIGH-LEVEL OUTPUT VOLTAGE FREE-AIR TEMPERATURE VID = mv IOH = µa Only the C to 7 C portion of the curve applies to the SN776B. Figure 6 8 TA Free-Air Temperature C RECEIVER LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT CURRENT RECEIVER LOW-LEVEL OUTPUT VOLTAGE FREE-AIR TEMPERATURE VOL V Low-Level Voltage V TA = C VOL V Low-Level Voltage V VID = mv IOL = 8 ma IOL Low-Level Current ma 6 8 TA Free-Air Temperature C Figure Figure POST OFFICE BOX 6 DALLAS, TEXAS 76
11 SN676B, SN776B TYPICAL CHARACTERISTICS SLLSB JULY 98 REVISED JUNE 999 VO V O Voltage V RECEIVER OUTPUT VOLTAGE ENABLE VOLTAGE VID =. V Load = 8 kω to GND TA = C VCC =. V VCC =.7 V VO O Voltage V 6 VCC =. V VCC =.7 V RECEIVER OUTPUT VOLTAGE ENABLE VOLTAGE VID =. V Load = kω to VCC TA = C... VI Enable Voltage V.. VI Enable Voltage V. Figure Figure 6 APPLICATION INFORMATION SN676B SN776B SN676B SN776B RT RT Up to Transceivers NOTE A: The line should be terminated at both ends in its characteristic impedance (RT = ZO). Stub lengths off the main line should be kept as short as possible. Figure 7. Typical Application Circuit POST OFFICE BOX 6 DALLAS, TEXAS 76
12 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ( CRITICAL APPLICATIONS ). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not constitute TI s approval, warranty or endorsement thereof. Copyright 999, Texas Instruments Incorporated
13 of >> Semiconductor Home > Products > Analog & Mixed-Signal > Interface Products > Transmitters and Receivers > SN776B, DIFFERENTIAL BUS TRANSCEIVER Device Status: Active > Description > Features > Datasheets > Pricing/Samples/Availability > Application Notes > Related Documents > Development Tools > Applications Parameter Name SN776B Drivers Per Package Receivers Per Package Driver tpd (ns) Receiver tpd (ns) Supply Voltage(s) (V) ICC (max) (ma) 7 Footprint SN776 Description The SN676B and SN776B differential bus transceivers are monolithic integrated circuits designed for bidirectional data communication on multipoint bus transmission lines. They are designed for balanced transmission lines and meet ANSI Standards TIA/EIA-- B and TIA/EIA-8-A and ITU Recommendations V. and X.7. The SN676B and SN776B combine a -state differential line driver and a differential input line receiver, both of which operate from a single -V power supply. The driver and receiver have active-high and active-low enables, respectively, that can be connected together externally to function as a direction control. The driver differential outputs and the receiver differential inputs are connected internally to form differential input/output (I/O) bus ports that are designed to offer minimum loading to the bus when the driver is disabled or V CC =. These ports feature wide positive and negative common-mode voltage ranges, making the device suitable for party-line applications. The driver is designed for up to 6 ma of sink or source current. The driver features positive and negative current limiting and thermal shutdown for protection from line-fault conditions. Thermal shutdown is designed to occur at a junction temperature of approximately C. The receiver features a minimum input impedance of k, an input sensitivity of ± mv, and a typical input hysteresis of mv. The SN676B and SN776B can be used in transmission-line applications employing the SN77 and SN77 quadruple differential line drivers and SN77 and SN77 quadruple differential line receivers.
14 of The SN676B is characterized for operation from - C to C and the SN776B is characterized for operation from C to 7 C. Features Bidirectional Transceivers Meet or Exceed the Requirements of ANSI Standards TIA/EIA--B and TIA/EIA- 8-A and ITU Recommendations V. and X.7 Designed for Multipoint Transmission on Long Bus Lines in Noisy Environments -State Driver and Receiver s Individual Driver and Receiver Enables Wide Positive and Negative / Bus Voltage Ranges Driver Capability...±6 ma Max Thermal Shutdown Protection Driver Positive and Negative Current Limiting Receiver Impedance... k Min Receiver Sensitivity...± mv Receiver Hysteresis... mv Typ Operate From Single -V Supply To view the following documents, Acrobat Reader.x is required. To download a document to your hard drive, right-click on the link and choose 'Save'. Datasheets Full datasheet in Acrobat PDF: sllsb.pdf (7 KB) Full datasheet in Zipped PostScript: sllsb.psz (66 KB) Pricing/Samples/Availability Orderable Device Package Pins Temp (ºC) Application Reports Status AND 8 OVERVIEW AND SYSTEM CONFIGURATIONS (SLLA7 - Updated: //) ANALOG APPLICATIONS JOURNAL, FEBRUARY (SLYTA - Updated: //) ANALOG APPLICATIONS JOURNAL, NOVEMBER 999 (SLYTA - Updated: //) COMPARING BUS SOLUTIONS (SLLA67 - Updated: /6/) ELECTROSTATIC DISCHARGE APPLICATION NOTE (SSYA8 - Updated: //999) INTERFACE CIRCUITS FOR TIA/EIA-8 (SLLA6 - Updated: /6/) JITTER ANALYSIS (SLLA7 - Updated: //) Price/unit USD (-999) Pack Qty Availability / Samples SN776BD D 8 TO 7 ACTIVE. 7 Check stock or order SN776BDR D 8 TO 7 ACTIVE.8 Check stock or order SN776BP P 8 TO 7 ACTIVE. Check stock or order SN776BPS PS 8 TO 7 ACTIVE Check stock or order
15 of SKEW DEFINITIONS (SLLA6 - Updated: 8//999) THERMAL CHARACTERISTICS OF LINEAR AND LOGIC PACKAGES USING JEDEC PCB DESIGNS (SZZA7A - Updated: 9//999) Related Documents A STATISTICAL SURVEY OF COMMON-MODE NOISE (SLLA7, KB - Updated: //999) Table Data Updated on: 6// (c) Copyright Texas Instruments Incorporated. All rights reserved. Trademarks, Important Notice!, Privacy Policy
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SN, SN SLLSC D66, JULY 9 REVISED FERURY 99 Meets EI Standards RS-- and RS- and CCI Recommendations V. and X. Designed for Multipoint ransmission on Long us Lines in Noisy Environments -State s us Voltage
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3-State Buffer-Type Outputs Drive Bus Lines Directly Bus-Structured Pinout Package Optio Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs
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Package Options Include Plastic Small-Outline (D), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description
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74A7 Eight Latches in a Single Package -State Bus-Driving True s Full Parallel Access for Loading Buffered Control Inputs Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and Configuratio
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Meets or Exceeds the Requirement of ANSI EIA/TIA-232-E and ITU Recommendation V.28 Withstands Sustained Output Short Circuit to Any Low-Impedance Voltage Between 25 V and 25 V 2-µs Max Transition Time
More informationPRODUCT PREVIEW SN54AHCT257, SN74AHCT257 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS. description
Inputs Are TTL-Voltage Compatible EPIC (Enhanced-Performance Implanted CMOS) Process Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), Thin Shrink
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Member of Texas Instruments Widebus Family Latch-Up Performance Exceeds 250 ma Per JESD 17 description This 16-bit (dual-octal) noninverting bus transceiver contains two separate supply rails; B port has
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Operation From Very Slow Input Transitions Temperature-Compensated Threshold Levels High Noise Immunity Same Pinouts as HC00 Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB),
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3-State s Drive Bus Lines Directly PNP s Reduce dc Loading on Bus Lines Hysteresis at Bus s Improves Noise Margins Typical Propagation Delay Times Port to Port, 8 ns TYPE IOL (SINK CURRENT) IOH (SOURCE
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Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description These devices contain four independent 2-input positive-nand
More informationSN54AS825A, SN74AS825A 8-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS020B JUNE 1984 REVISED AUGUST 1995
Functionally Equivalent to AMD s AM2982 Improved I OH Specificatio Multiple Output Enables Allow Multiuser Control of the Interface Outputs Have Undershoot-Protection Circuitry Power-Up High-Impedance
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Member of Texas Instruments Widebus Family State-of-the-Art Advanced Low-Voltage BiCMOS (ALB) Technology Design for.-v Operation Schottky Diodes on All s to Eliminate Overshoot and Undershoot Industry
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Typical V OLP ( Ground Bounce) 2 V at V CC = 3.3 V, T A = 25 C s Accept Voltages to 5.5 V Latch-Up Performance Exceeds 100 ma Per JESD
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SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244 3-State s Drive Bus Lines or Buffer Memory Address Registers PNP s Reduce DC Loading Hysteresis at s Improves Noise Margins description These
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Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-Pin V CC and GND Configurations to Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS)
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MC89, MC89A, SN89, SN89A, SN789, SN789A SLLS9B SEPTEMPER 97 REVISED MAY 99 Input Resistance... kω to 7 kω Input Signal Range...± V Operate From Single -V Supply Built-In Input Hysteresis (Double Thresholds)
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4AC64, 74AC64 6-BIT BUS TRANSCEIVERS SCAS3A MARCH 990 REVISED APRIL 996 Members of the Texas Itruments Widebus Family 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers Flow-Through Architecture
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Meets or Exceeds the Requirements of ANSI EIA/TIA-232-E and ITU Recommendation V.28 Single Chip With Easy Interface Between UART and Serial Port Connector Less Than 9-mW Power Consumption Wide Driver Supply
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Compare Two -Bit Words Totem-Pole Outputs () ALS Are Identical to ALS2 Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J)
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3-State Buffer-Type Outputs Drive Bus Lines Directly Bus-Structured Pinout Package Optio Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs
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Member of the Texas Instruments Widebus Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process UBT (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in
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SCAS AUGUST 99 REVISED MAY 99 Inputs Are TTL-Voltage Compatible EPIC (Enhanced-Performance Implanted CMOS) -µm Process Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin
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Members of the Texas Itruments Widebus Family Inputs Are TTL-Voltage Compatible 3-State Bus Driving True s Full Parallel Access for Loading Flow-Through Architecture Optimizes PCB Layout Distributed and
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Inputs Are TTL Compatible EPIC (Enhanced-Performance Implanted CMOS) -µm Process Package Optio Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and DIP (N)
More informationEN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at ore.hu.
EN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at www.hest ore.hu. Convert TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping
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SCLS07B DECEMBER 92 REVISED MAY 997 Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK),
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SN7577, SN7578 Meet or Exceed the Requirements of ANSI Standards TIA/EIA-4-B and TIA/EIA-485-A and ITU Recommendations V.0 and V. Designed for Multipoint Bus Transmission on Long Bus Lines in Noise Environments
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-State Buffer-Type s Drive Bus Lines Directly Bus-Structured Pinout Package Optio Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), Standard Plastic (N) and Ceramic (J) 00-mil DIPs,
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Meet or Exceed the Requirements of ANSI EIA/TIA-232-E and ITU Recommendation V.28 Very Low Power Consumption 5 mw Typ Wide Driver Supply Voltage Range ±4.5 V to ±15 V Driver Output Slew Rate Limited to
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Bidirectional Transceivers Meet or Exceed the Requirements of ANSI Standards TIA/EIA-4-B and TIA/EIA-485-A and ITU Recommendations V.11 and X.7 Designed for Multipoint Transmission on Long Bus Lines in
More informationDistributed by: www.jameco.com -8-8-44 The content and copyrights of the attached material are the property of its owner. Bidirectional Transceivers Meet or Exceed the Requirements of ANSI Standards TIA/EIA-4-B
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4.5-V to 5.5-V V CC Operation Fanout (Over Temperature Range) Standard s... 0 LSTTL Loads Bus-Driver s... 5 LSTTL Loads Wide Operating Temperature Range of 55 C to 25 C Balanced Propagation Delays and
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SN74CBTLV326 LOW-VOLTAGE QUADRUPLE FET BUS SWITCH SCDS03H DECEMBER 997 REVISED APRIL 2003 Standard 26-Type Pinout 5-Ω Switch Connection Between Two Ports Isolation Under Power-Off Conditions Latch-up Performance
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SLRS28 SEPTEMBER 1988 Quadruple Circuits Capable of Driving High-Capacitance Loads at High Speeds Output Supply Voltage Range From 5 V to 24 V Low Standby Power Dissipation V CC3 Supply Maximizes Output
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PERIPHERAL DRIVERS FOR HIGH-CURRENT SWITCHING AT VERY HIGH SPEEDS Characterized for Use to 00 ma High-Voltage Outputs No Output Latch-Up at 0 V (After Conducting 00 ma) High-Speed Switching Circuit Flexibility
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Package Optio Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description These devices contain four independent 2-input exclusive-or
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HIH-SPEED DIFFERENTIAL LINE DRIVER Designed for Signaling Rates Up to 5 Mbps Low-Voltage Differential Signaling With Typical Output Voltage of 7 mv and a -Ω Load Propagation Delay Time of. ns, Typical
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Operates With Single 5-V Power Supply LinBiCMOS Process Technology Two Drivers and Two Receivers ± 30-V Input Levels Low Supply Current...8 ma Typical Meets or Exceeds TIA/EIA-232-F and ITU Recommendation
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Inputs Are TTL-Voltage Compatible EPIC (Enhanced-Performance Implanted CMOS) Process Contain Six Flip-Flops With Single-Rail s Applicatio Include: Buffer/Storage Registers Shift Registers Pattern Generators
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SCAS032A JUL 187 REVISED APRIL 13 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and Configuratio Minimize High-Speed
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EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Useful for Jumperless Configuration of PC Motherboard Inputs Accept Voltages to 5.5 V Signals are 2.5-V Outputs Signal is a 3.3-V Output Minimum
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Package Optio Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs TYPE TYPICAL MAXIMUM CLOCK FREUEY (CL = 0 pf) (MHz) TYPICAL POWER
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Low Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation pplications Operates at 3.3-V LVTTL-Compatible Inputs and s Supports Mixed-Mode Signal Operation (-V Input and Voltages With 3.3-V )
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SN54LS373, SN54LS374, SN54S373, SN54S374, Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving s Full Parallel Access for Loading Buffered Control s Clock-Enable Has
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SN777B, SN778B SLLSC D66, JULY 98 REVISED FEBRUARY 99 Meets EIA Standards RS--A and RS-8 and CCITT Recommendations V. and X.7 Designed for Multipoint Transmission on Long Bus Lines in Noisy Environments
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74ACT62 Independent Registers and Enables for A and B Buses Multiplexed Real-Time and Stored Data Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and Configuratio Minimize High-Speed Switching
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Meets or Exceeds the Requirements of TIA/EIA-422-B, TIA/EIA-485-A, and ITU Recommendations V.11 and X.27 Recommended for PROFIBUS Applications Operates at Data Rates up to 35 MBaud Operating Temperature
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Member of the Texas Itruments idebus Family Load Clock and Unload Clock Can Be Asynchronous or Coincident 256 ords by 18 Bits Low-Power Advanced CMOS Technology Full, Empty, and Half-Full Flags Programmable
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Dual Versions of Highly Stable SN542 and SN742 One Shots SN5422 and SN7422 Demonstrate Electrical and Switching Characteristics That Are Virtually Identical to the SN542 and SN742 One Shots Pinout Is Identical
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Package Optio Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs TYPE TYPICAL MAXIMUM CLOCK FREUEY (CL = 0 pf) (MHz) TYPICAL POWER
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3-State Buffer-Type s Drive Bus Lines Directly Bus-Structured Pinout Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and Configuratio Minimize High-Speed Switching Noise EPIC (Enhanced-Performance
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WITH SELECTBLE POLRITY ND -STTE OUTPUTS SCS4 DECEMBER 99 REVISED NOVEMBER 99 Low Skew for Clock-Distribution and Clock-Generation pplicatio TTL-Compatible Inputs and s Distributes One Clock Input to Six
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Dependable Texas Instruments Quality and Reliability description These devices contain six independent inverters. SN5404, SN54LS04, SN54S04, SN5404... J PACKAGE SN54LS04, SN54S04... J OR W PACKAGE SN7404...
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HIGH-VOLTAGE, HIGH-CURRENT 500-mA-Rated Collector Current (Single ) High-Voltage s...50 V Clamp Diodes Inputs Compatible With Various Types of Logic Relay Driver Applications Compatible With ULN2800A-Series
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Operation From Very Slow Edges Improved Line-Receiving Characteristics High Noise Immunity SN5414, SN54LS14, SN5414, SN54LS14...J OR W PACKAGE SN7414... D, N, OR NS PACKAGE SN74LS14... D, DB, OR N PACKAGE
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5A1533, 7A1533 TAL D-TYPE TRANSPARENT LATHES SAS00 D257, JULY 187 REVISED APRIL 13 8-Latches in a Single Package 3-State Bus-Driving Inverting s Full Parallel Access for Loading Buffered ontrol Inputs
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Single Down/Up Count-Control Line Look-Ahead Circuitry Enhances Speed of Cascaded Counters Fully Synchronous in Count Modes Asynchronously Presettable With Load Control Package Options Include Plastic
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WITH CLEA SDAS2A APIL 92 EVISED DECEMBE 99 Contain Eight Flip-Flops With Single-ail Outputs Buffered Clock and Direct-Clear Inputs Individual Data Input to Each Flip-Flop Applications Include: Buffer/Storage
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Featuring Unitrode L and LD Products Now From Texas Instruments Wide Supply-Voltage Range:.5 V to V Separate Input-Logic Supply Internal ESD Protection Thermal Shutdown High-Noise-Immunity Inputs Functional
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SNALS2C, SNAS2A, SNALS2C, SNAS2A SDAS2C JUL 9 REISED AUGUST 99 -State Outputs Drive Bus Lines or Buffer Memory Address Registers pnp Inputs Reduce dc Loading Package Optio Include Plastic Small-Outline
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SLRSB DECEMBER REVISED SEPTEMBER HIGH-VOLTAGE HIGH-CURRENT -ma Rated Collector Current (Single ) High-Voltage s... V Clamp Diodes Inputs Compatible With Various Types of Logic Relay Driver Applications
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WITH CLEA SDAS2A APIL 2 EVISED DECEMBE 4 Contain Eight Flip-Flops With Single-ail Outputs Buffered Clock and Direct-Clear Inputs Individual Data Input to Each Flip-Flop Applications Include: Buffer/Storage
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Inputs Are TTL-oltage Compatible EPIC (Enhanced-Performance Implanted CMOS) Process Operation From ery Slow Input Traitio Temperature-Compeated Threshold Levels High Noise Immunity Same Pinouts as AHCT00
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Operates From.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max t pd of 4.8 ns at 3.3 V Typical V OLP (Output Ground Bounce) 2
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Convert TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays description These hex buffers/drivers feature
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Complete PWM Power Control Circuitry Uncommitted Outputs for 200-mA Sink or Source Current Output Control Selects Single-Ended or Push-Pull Operation Internal Circuitry Prohibits Double Pulse at Either
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ULNA, ULNA, ULNA, ULNA SLRS DECEMBER REVISED APRIL HIGH-VOLTAGE HIGH-CURRENT -ma Rated Collector Current (Single ) High-Voltage s... V Clamp Diodes Inputs Compatible With Various Types of Logic Relay Driver
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Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and GND Configuratio Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-µm
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