SN54ALS273, SN74ALS273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR
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1 WITH CLEA SDAS2A APIL 92 EVISED DECEMBE 99 Contain Eight Flip-Flops With Single-ail Outputs Buffered Clock and Direct-Clear Inputs Individual Data Input to Each Flip-Flop Applications Include: Buffer/Storage egisters Shift egisters Pattern Generators Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description These octal positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with a direct-clear (CL) input. Information at the data (D) inputs meeting the setup-time requirements is transferred to the Q outputs on the positive-going edge of the clock () pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When is at either the high or low level, the D input signal has no effect at the output. The SNALS2 is characterized for operation over the full military temperature range of C to 2 C. The SNALS2 is characterized for operation from 0 C to 0 C. SNALS2...J PACKAGE SNALS2... DW O N PACKAGE (TOP VIEW) CL Q Q D D Q GND V CC Q D D Q D Q SNALS2... FK PACKAGE (TOP VIEW) Q D D Q CL Q GND V CC Q D Q D D Q FUNCTION TABLE (each flip-flop) INPUTS OUTPUT CL D Q L X X L H H H H L L H H or L X Q0 PODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 99, Texas Instruments Incorporated POST OFFICE BOX 0 DALLAS, TEXAS 2
2 WITH CLEA SDAS2A APIL 92 EVISED DECEMBE 99 logic symbol CL D D D D D Q Q Q Q Q Q This symbol is in accordance with ANSI/IEEE Std 9-9 and IEC Publication -2. logic diagram (positive logic) D D D D D CL 2 Q Q 9 Q 2 Q Q 9 Q absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, V CC V Input voltage, V I V Operating free-air temperature range, T A : SNALS C to 2 C SNALS C to 0 C Storage temperature range C to 0 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 POST OFFICE BOX 0 DALLAS, TEXAS 2
3 WITH CLEA SDAS2A APIL 92 EVISED DECEMBE 99 recommended operating conditions SNALS2 SNALS2 MIN NOM MAX MIN NOM MAX UNIT VCC Supply voltage.... V VIH High-level input voltage 2 2 V VIL Low-level input voltage V IOH High-level output current 2. ma IOL Low-level output current 2 2 ma fclock Clock frequency MHz CL low 0 0 tw Pulse duration high. ns low. tsu Setup time before Data 0 0 CL inactive state ns th Hold time, data after 0 0 ns TA Operating free-air temperature C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PAAMETE TEST CONDITIONS SNALS2 SNALS2 MIN TYP MAX MIN TYP MAX VIK VCC =. V, II = ma.. V VCC =. V to. V, IOH = 0. ma VCC 2 VCC 2 VCC =V. VOL VCC =V. IOH = ma 2.. V IOH = 2. ma 2..2 IOL = 2 ma IOL = 2 ma II VCC =. V, VI = V ma IIH VCC =. V, VI = 2. V µa IIL VCC =. V, VI = 0. V ma IO VCC =. V, VO = 2.2 V ma ICCH VCC =. V ma ICCL VCC =. V ma All typical values are at VCC = V, TA = 2 C. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. UNIT V POST OFFICE BOX 0 DALLAS, TEXAS 2
4 WITH CLEA SDAS2A APIL 92 EVISED DECEMBE 99 switching characteristics (see Figure ) PAAMETE FOM (INPUT) TO (OUTPUT) VCC =. V to. V, CL = 0 pf, L = 00 Ω, TA = MIN to MAX SNALS2 SNALS2 MIN MAX MIN MAX fmax 0 MHz tphl CL Any Q 2 ns tplh Any Q tphl For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. UNIT ns POST OFFICE BOX 0 DALLAS, TEXAS 2
5 WITH CLEA SDAS2A APIL 92 EVISED DECEMBE 99 PAAMETE MEASUEMENT INFOMATION SEIES ALS/ALS AND AS/AS DEVICES VCC V L = = 2 S L From Output Under Test CL (see Note A) L Test Point From Output Under Test CL (see Note A) Test Point From Output Under Test CL (see Note A) 2 Test Point LOAD CICUIT FO BI-STATE TOTEM-POLE OUTPUTS LOAD CICUIT FO OPEN-COLLECTO OUTPUTS LOAD CICUIT FO -STATE OUTPUTS Timing Input High-Level Pulse Data Input tsu th Low-Level Pulse tw VOLTAGE WAVEFOMS SETUP AND HOLD TIMES VOLTAGE WAVEFOMS PULSE DUATIONS Output Control (low-level enabling) Waveform S Closed (see Note B) Waveform 2 S Open (see Note B) tpzl tpzh tphz tplz VOL VOLTAGE WAVEFOMS ENABLE AND DISABLE TIMES, -STATE OUTPUTS 0 V Input In-Phase Output Out-of-Phase Output (see Note C) tplh tphl tphl VOL tplh VOL VOLTAGE WAVEFOMS POPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of -state outputs, switch S is open. D. All input pulses have the following characteristics: P MHz, tr = tf = 2 ns, duty cycle = 0%. E. The outputs are measured one at a time with one transition per measurement. Figure. Load Circuits and Voltage Waveforms POST OFFICE BOX 0 DALLAS, TEXAS 2
6 IMPOTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CETAIN APPLICATIONS USING SEMICONDUCTO PODUCTS MAY INVOLVE POTENTIAL ISKS OF DEATH, PESONAL INJUY, O SEVEE POPETY O ENVIONMENTAL DAMAGE ( CITICAL APPLICATIONS ). TI SEMICONDUCTO PODUCTS AE NOT DESIGNED, AUTHOIZED, O WAANTED TO BE SUITABLE FO USE IN LIFE-SUPPOT DEVICES O SYSTEMS O OTHE CITICAL APPLICATIONS. INCLUSION OF TI PODUCTS IN SUCH APPLICATIONS IS UNDESTOOD TO BE FULLY AT THE CUSTOME S ISK. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not constitute TI s approval, warranty or endorsement thereof. Copyright 99, Texas Instruments Incorporated
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SLRS28 SEPTEMBER 1988 Quadruple Circuits Capable of Driving High-Capacitance Loads at High Speeds Output Supply Voltage Range From 5 V to 24 V Low Standby Power Dissipation V CC3 Supply Maximizes Output
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N5465, N465 8-BIT PAAE-OAD IFT EGITE 16C DECEMBE 1982 EVIED MAY 199 Complementary Outputs Direct Overriding oad (Data) Inputs Gated Clock Inputs Parallel-to-erial Data Conversion Package Options Include
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5A1533, 7A1533 TAL D-TYPE TRANSPARENT LATHES SAS00 D257, JULY 187 REVISED APRIL 13 8-Latches in a Single Package 3-State Bus-Driving Inverting s Full Parallel Access for Loading Buffered ontrol Inputs
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Meet or Exceed the Requirements of TIA/EIA-232-F and ITU Recommendation V.28 Very Low Power Consumption... 5 mw Typ Wide Driver Supply Voltage Range... ±4.5 V to ±15 V Driver Output Slew Rate Limited to
More informationTPS CHANNEL POWER SUPPLY SUPERVISOR
3-CHANNEL POWE SUPPLY SUPEVISO Over Voltage Protection and Lock Out for 5 V, 3.3 V, and 12 V Under Voltage Protection and Lock Out for 5 V and 3.3 V Fault Protection Output with Open Drain Output Stage
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Operates With Single -V Power Supply LinBiCMOS Process Technology Two Drivers and Two Receivers ± 0-V Input Levels Low Supply Current...8 ma Typical Meets or Exceeds TIA/EIA-22-F and ITU Recommendation
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Member of Texas Instruments Widebus Family State-of-the-Art Advanced Low-Voltage BiCMOS (ALB) Technology Design for.-v Operation Schottky Diodes on All s to Eliminate Overshoot and Undershoot Industry
More informationSN54ALS32, SN54AS32, SN74ALS32, SN74AS32 QUADRUPLE 2-INPUT POSITIVE-OR GATES
SN54ALS32, SN54AS32, SN74ALS32, SN74AS32 QUADRUPLE 2-INPUT POSITIVE-OR GATES SDAS113B APRIL 1982 REVISED DECEMBER 1994 Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers
More informationTL5632C 8-BIT 3-CHANNEL HIGH-SPEED DIGITAL-TO-ANALOG CONVERTER
8-Bit Resolution Linearity... ±1/2 LSB Maximum Differential Nonlinearity...±1/2 LSB Maximum Conversion Rate...60 MHz Min Nominal Output Signal Operating Range V CC to V CC 1 V TTL Digital Input Voltage
More informationSN5404, SN54LS04, SN54S04, SN7404, SN74LS04, SN74S04 HEX INVERTERS
Dependable Texas Instruments Quality and Reliability description These devices contain six independent inverters. SN5404, SN54LS04, SN54S04, SN5404... J PACKAGE SN54LS04, SN54S04... J OR W PACKAGE SN7404...
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Dual Versions of Highly Stable SN542 and SN742 One Shots SN5422 and SN7422 Demonstrate Electrical and Switching Characteristics That Are Virtually Identical to the SN542 and SN742 One Shots Pinout Is Identical
More informationCD74HCT4514, CD74HCT LINE TO 16-LINE DECODERS/DEMULTIPLEXERS WITH INPUT LATCHES
4.5-V to 5.5-V V CC Operation Fanout (Over Temperature Range) Standard s... 0 LSTTL Loads Bus-Driver s... 5 LSTTL Loads Wide Operating Temperature Range of 55 C to 25 C Balanced Propagation Delays and
More informationSN54ALS299, SN74ALS299 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH 3-STATE OUTPUTS
Multiplexed I/O Ports Provide Improved Bit Deity Four Modes of Operation: old (Store) Shift Right Shift eft oad Data Operate With Outputs Enabled or at igh Impedance -State Outputs Drive Bus ines Directly
More informationCDC LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS442B FEBRUARY 1994 REVISED NOVEMBER 1995
Low Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation pplications Operates at 3.3-V LVTTL-Compatible Inputs and s Supports Mixed-Mode Signal Operation (-V Input and Voltages With 3.3-V )
More informationSN54AHCT132, SN74AHCT132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS
Inputs Are TTL-oltage Compatible EPIC (Enhanced-Performance Implanted CMOS) Process Operation From ery Slow Input Traitio Temperature-Compeated Threshold Levels High Noise Immunity Same Pinouts as AHCT00
More informationSN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SN54LS373, SN54LS374, SN54S373, SN54S374, Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving s Full Parallel Access for Loading Buffered Control s Clock-Enable Has
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EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Useful for Jumperless Configuration of PC Motherboard Inputs Accept Voltages to 5.5 V Signals are 2.5-V Outputs Signal is a 3.3-V Output Minimum
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SN54ALS05A, SN74ALS05A HEX INVERTERS WITH OPEN-COLLECTOR OUTPUTS SDAS190A APRIL 1982 REVISED DECEMBER 1994 Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard
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Meet or Exceed the Requirements of ANSI EIA/TIA-232-E and ITU Recommendation V.28 Very Low Power Consumption 5 mw Typ Wide Driver Supply Voltage Range ±4.5 V to ±15 V Driver Output Slew Rate Limited to
More informationCD54ACT74, CD74ACT74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
s Are TTL-Voltage ompatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power onsumption Balanced Propagation Delays ±24-mA Drive urrent Fanout to 5 F Devices SR-Latchup-Resistant MOS Process
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Meets or Exceeds the Requirements of TIA/EIA-232-F and ITU Recommendation V.28 Single Chip With Easy Interface Between UART and Serial-Port Connector Less Than 9-mW Power Consumption Wide Driver Supply
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MC89, MC89A, SN89, SN89A, SN789, SN789A SLLS9B SEPTEMPER 97 REVISED MAY 99 Input Resistance... kω to 7 kω Input Signal Range...± V Operate From Single -V Supply Built-In Input Hysteresis (Double Thresholds)
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Inputs Are TTL-Voltage Compatible Contain Six Flip-Flops With Single-Rail s Applicatio Include: Buffer/Storage Registers Shift Registers Pattern Generators Latch-Up Performance Exceeds 250 ma Per JESD
More informationSN75C185 LOW-POWER MULTIPLE DRIVERS AND RECEIVERS
Meets or Exceeds the Requirements of ANSI EIA/TIA-232-E and ITU Recommendation V.28 Single Chip With Easy Interface Between UART and Serial Port Connector Less Than 9-mW Power Consumption Wide Driver Supply
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Compatible With IEEE Std 1194.1-1991 (TL) TTL A Port, ackplane Traceiver Logic (TL) Port Open-Collector -Port Outputs Sink 100 ma IAS V CC Pin Minimizes Signal Distortion During Live Iertion or Withdrawal
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Member of Texas Instruments Widebus Family Latch-Up Performance Exceeds 250 ma Per JESD 17 description This 16-bit (dual-octal) noninverting bus transceiver contains two separate supply rails; B port has
More informationCDC391 1-LINE TO 6-LINE CLOCK DRIVER WITH SELECTABLE POLARITY AND 3-STATE OUTPUTS
WITH SELECTBLE POLRITY ND -STTE OUTPUTS SCS4 DECEMBER 99 REVISED NOVEMBER 99 Low Skew for Clock-Distribution and Clock-Generation pplicatio TTL-Compatible Inputs and s Distributes One Clock Input to Six
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Operates From.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max t pd of 4.8 ns at 3.3 V Typical V OLP (Output Ground Bounce) 2
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SN676B, SN776B Bidirectional Transceivers Meet or Exceed the Requirements of ANSI Standards TIA/EIA--B and TIA/EIA-8-A and ITU Recommendations V. and X.7 Designed for Multipoint Transmission on Long Bus
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Operation From Very Slow Edges Improved Line-Receiving Characteristics High Noise Immunity SN5414, SN54LS14, SN5414, SN54LS14...J OR W PACKAGE SN7414... D, N, OR NS PACKAGE SN74LS14... D, DB, OR N PACKAGE
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Convert TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays description These hex buffers/drivers feature
More informationSN54ALS1035, SN74ALS1035 HEX NONINVERTING BUFFERS WITH OPEN-COLLECTOR OUTPUTS
Noninverting Buffers With Open-Collector Outputs description These devices contain six independent noninverting buffers. They perform the Boolean function Y = A. The open-collector outputs require pullup
More informationIMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the
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