ORDERING INFORMATION PACKAGE

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1 Operates From.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max t pd of 4.8 ns at 3.3 V Typical V OLP (Output Ground Bounce) <0.8 V at V CC = 3.3 V, T A = 25 C Typical V OHV (Output V OH Undershoot) >2 V at V CC = 3.3 V, T A = 25 C Latch-Up Performance Exceeds 250 ma Per JESD 7 ESD Protection Exceeds JESD V Human-Body Model (A4-A) 200-V Machine Model (A5-A) 000-V Charged-Device Model (C0) description/ordering information SN74LVC2A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET SCAS289J JANUARY 993 RESED AUGUST 2002 This dual negative-edge-triggered J-K flip-flop is designed for.65-v to 3.6-V V CC operation. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements is transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs can be changed without affecting the levels at the outputs. The SN74LVC2A can perform as a toggle flip-flop by tying J and K high. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. TA 40 C to85 C ORDERING INFORMATION PACKAGE D, DB, DGV, NS, OR PW PACKAGE (TOP EW) CLK K J PRE Q Q 2Q GND ORDERABLE PART NUMBER SN74LVC2AD SN74LVC2ADR TOP-SIDE MARKING SOIC D Tube Tape and reel LVC2A SOP NS Tape and reel SN74LVC2ANSR LVC2A SSOP DB Tape and reel SN74LVC2ADBR LC2A TSSOP PW Tape and reel SN74LVC2APWR LC2A TVSOP DGV Tape and reel SN74LVC2ADGVR LC2A Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at V CC CLR 2CLR 2CLK 2K 2J 2PRE 2Q Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2002, Texas Instruments Incorporated

2 SN74LVC2A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET SCAS289J JANUARY 993 RESED AUGUST 2002 logic diagram, each flip-flop (positive logic) FUNCTION TABLE INPUTS OUTPUTS PRE CLR CLK J K Q Q L H X X X H L H L X X X L H L L X X X H H H H L L Q0 Q0 H H H L H L H H L H L H H H H H Toggle H H H X X Q0 Q0 The output levels in this configuration may not meet the minimum levels for VOH. Furthermore, this configuration is unstable; that is, it does not persist when either PRE or CLR returns to its inactive (high) level. Q PRE Q CLR K J CLK 2

3 SN74LVC2A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET SCAS289J JANUARY 993 RESED AUGUST 2002 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V CC V to 6.5 V Input voltage range, V I (see Note ) V to 6.5 V Output voltage range, V O (see Notes and 2) V to V CC V Input clamp current, I IK (V I < 0) ma Output clamp current, I OK (V O < 0) ma Continuous output current, I O ±50 ma Continuous current through V CC or GND ±00 ma Package thermal impedance, θ JA (see Note 3): D package C/W DB package C/W DGV package C/W NS package C/W PW package C/W Storage temperature range, T stg C to 50 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES:. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 5-7. recommended operating conditions (see Note 4) MIN MAX UNIT VCC Supply voltage Operating Data retention only.5 V VCC =.65 V to.95 V 0.65 VCC H High-level input voltage VCC = 2.3 V to 2.7 V.7 V VCC = 2.7 V to 3.6 V 2 VCC =.65 V to.95 V 0.35 VCC L Low-level input voltage VCC = 2.3 V to 2.7 V 0.7 V VCC = 2.7 V to 3.6 V 0.8 Input voltage V VO Output voltage 0 VCC V IOH IOL High-level output current Low-level output current VCC =.65 V 4 VCC = 2.3 V 8 VCC = 2.7 V 2 VCC = 3 V 24 VCC =.65 V 4 VCC = 2.3 V 8 VCC = 2.7 V 2 VCC = 3 V 24 t/ v Input transition rise or fall rate 0 ns/v TA Operating free-air temperature C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. ma ma 3

4 SN74LVC2A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET SCAS289J JANUARY 993 RESED AUGUST 2002 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VOH IOH = 00 µa.65 V to 3.6 V VCC 0.2 IOH = 4 ma.65 V.2 IOH = 8 ma 2.3 V.7 IOH = 2 ma 2.7 V V 2.4 IOH = 24 ma 3 V 2.2 IOL = 00 µa.65 V to 3.6 V 0.2 IOL = 4 ma.65 V 0.45 VOL IOL = 8 ma 2.3 V 0.7 V IOL = 2 ma 2.7 V 0.4 IOL = 24 ma 3 V 0.55 II = 5.5 V or GND 3.6 V ±5 µa ICC = VCC or GND, IO = V 0 µa ICC One input at VCC 0.6 V, Other inputs at VCC or GND 2.7 V to 3.6 V 500 µa Ci = VCC or GND 3.3 V 4.5 pf All typical values are at VCC = 3.3 V, TA = 25 C. timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure ) VCC =.8 V ± 0.5 V VCC = 2.5 V ± 0.2 V VCC = 2.7 V V VCC = 3.3 V ± 0.3 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX fclock Clock frequency MHz tw Pulse duration, CLK high or low ns tsu Setup time Data before CLK PRE or CLR inactive 2.4. th Hold time, data after CLK ns This information was not available at the time of publication. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure ) PARAMETER fmax tpd FROM (INPUT) CLR or PRE CLK TO (OUTPUT) QorQ Q This information was not available at the time of publication. operating characteristics, T A = 25 C VCC =.8 V ± 0.5 V VCC = 2.5 V ± 0.2 V VCC = 2.7 V VCC = 3.3 V ± 0.3 V UNIT MIN MAX MIN MAX MIN MAX MIN TYP MAX MHz V CC =.8 V VCC = 2.5 V VCC = 3.3 V PARAMETER TEST CONDITIONS TYP TYP TYP Cpd Power dissipation capacitance f = 0 MHz 24 pf This information was not available at the time of publication. ns ns UNIT 4

5 SN74LVC2A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET SCAS289J JANUARY 993 RESED AUGUST 2002 PARAMETER MEASUREMENT INFORMATION From Output Under Test CL (see Note A) RL RL S VLOAD Open GND TEST tplh/tphl tplz/tpzl tphz/tpzh S Open VLOAD GND LOAD CIRCUIT VCC INPUTS tr/tf VLOAD CL RL V.8 V ± 0.5 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VCC VCC 2.7 V 2.7 V 2 ns 2 ns 2.5 ns 2.5 ns VCC/2 VCC/2.5 V.5 V 2 VCC 2 VCC 6 V 6 V 30 pf 30 pf 50 pf 50 pf kω 500 Ω 500 Ω 500 Ω 0.5 V 0.5 V 0.3 V 0.3 V tw Timing Input 0 V tsu th Input 0 V Data Input 0 V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Input 0 V Output Control 0 V Output tplh tphl VOH VOL Output Waveform S at VLOAD (see Note B) tpzl tplz VOL + V VLOAD/2 VOL Output tphl tplh VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOH VOL Output Waveform 2 S at GND (see Note B) tpzh tphz VOH V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING VOH 0 V NOTES: A. CL includes probe and jig capacitance. B. Waveform is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 0 MHz, ZO = 50 Ω. D. The outputs are measured one at a time with one transition per measurement. E. tplz and tphz are the same as tdis. F. tpzl and tpzh are the same as ten. G. tplh and tphl are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure. Load Circuit and Voltage Waveforms 5

6 MECHANICAL DATA MPDS006C FEBRUARY 996 RESED AUGUST 2000 DGV (R-PDSO-G**) 24 PINS SHOWN PLASTIC SMALL-OUTLINE 0,40 0,23 0,3 0,07 M ,6 NOM 4,50 4,30 6,60 6,20 Gage Plane 2 A 0 8 0,25 0,75 0,50,20 MAX 0,5 0,05 Seating Plane 0,08 DIM PINS ** A MAX 3,70 3,70 5,0 5,0 7,90 9,80,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60, /E 08/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,5 per side. D. Falls within JEDEC: 24/48 Pins MO-53 4/6/20/56 Pins MO-94

7 MECHANICAL DATA MSOI002B JANUARY 995 RESED SEPTEMBER 200 D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 8 PINS SHOWN (,27) (0,5) 0.04 (0,35) 0.00 (0,25) (6,20) (5,80) (0,20) NOM 0.57 (4,00) 0.50 (3,8) Gage Plane 4 A (0,25) (,2) 0.06 (0,40) Seating Plane (,75) MAX 0.00 (0,25) (0,0) (0,0) DIM PINS ** A MAX 0.97 (5,00) (8,75) (0,00) A MIN (4,80) (8,55) (9,80) /E 09/0 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed (0,5). D. Falls within JEDEC MS-02

9 MECHANICAL DATA MSSO002E JANUARY 995 RESED DECEMBER 200 DB (R-PDSO-G**) 28 PINS SHOWN PLASTIC SMALL-OUTLINE 0,65 0,38 0,22 0,5 M ,60 5,00 8,20 7,40 0,25 0,09 Gage Plane 4 0,25 A 0 8 0,95 0,55 2,00 MAX 0,05 MIN Seating Plane 0,0 DIM PINS ** A MAX 6,50 6,50 7,50 8,50 0,50 0,50 2,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 2, /E 2/0 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,5. D. Falls within JEDEC MO-50

10 MECHANICAL DATA MTSS00C JANUARY 995 RESED FEBRUARY 999 PW (R-PDSO-G**) 4 PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,65 0,0 M 0, ,50 4,30 6,60 6,20 0,5 NOM Gage Plane A ,25 0,75 0,50,20 MAX 0,5 0,05 Seating Plane 0,0 DIM PINS ** A MAX 3,0 5,0 5,0 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9, /F 0/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,5. D. Falls within JEDEC MO-53

11 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Mailing Address: Texas Instruments Post Office Box Dallas, Texas Copyright 2003, Texas Instruments Incorporated

1OE 3B V GND ORDERING INFORMATION. TOP-SIDE MARKING QFN RGY Tape and reel SN74CBTLV3126RGYR CL126 PACKAGE

1OE 3B V GND ORDERING INFORMATION. TOP-SIDE MARKING QFN RGY Tape and reel SN74CBTLV3126RGYR CL126 PACKAGE SN74CBTLV326 LOW-VOLTAGE QUADRUPLE FET BUS SWITCH SCDS03H DECEMBER 997 REVISED APRIL 2003 Standard 26-Type Pinout 5-Ω Switch Connection Between Two Ports Isolation Under Power-Off Conditions Latch-up Performance