L293, L293D QUADRUPLE HALF-H DRIVERS
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1 Featuring Unitrode L and LD Products Now From Texas Instruments Wide Supply-Voltage Range:.5 V to V Separate Input-Logic Supply Internal ESD Protection Thermal Shutdown High-Noise-Immunity Inputs Functional Replacements for SGS L and SGS LD Output Current A Per Channel ( ma for LD) Peak Output Current A Per Channel (. A for LD) Output Clamp Diodes for Inductive Transient Suppression (LD) description The L and LD are quadruple high-current half-h drivers. The L is designed to provide bidirectional drive currents of up to A at voltages from.5 V to V. The LD is designed to provide bidirectional drive currents of up to -ma at voltages from.5 V to V. Both devices are designed to drive inductive loads such as relays, solenoids, dc and bipolar stepping motors, as well as other high-current/high-voltage loads in positive-supply applications. SLRS8B SEPTEMBER 8 REVISED JUNE,EN A Y HEAT SINK AND GROUND Y A V CC HEAT SINK AND GROUND,EN A Y Y A V CC N, NE PACKAGE (TOP VIEW) V CC A Y HEAT SINK AND GROUND All inputs are TTL compatible. Each output is a complete totem-pole drive circuit, with a Darlington transistor sink and a pseudo-darlington source. Drivers are enabled in pairs, with drivers and enabled by,en and drivers and enabled by,en. When an enable input is high, the associated drivers are enabled and their outputs are active and in phase with their inputs. When the enable input is low, those drivers are disabled and their outputs are off and in the high-impedance state. With the proper data inputs, each pair of drivers forms a full-h (or bridge) reversible drive suitable for solenoid or motor applications. On the L, external high-speed output clamp diodes should be used for inductive transient suppression. A V CC terminal, separate from V CC, is provided for the logic inputs to minimize device power dissipation. The Land LD are characterized for operation from C to C DWP PACKAGE (TOP VIEW) Y A,EN V CC A Y Y A,EN HEAT SINK AND GROUND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright, Texas Instruments Incorporated POST OFFICE BOX 55 DALLAS, TEXAS 55
2 SLRS8B SEPTEMBER 8 REVISED JUNE block diagram VCC 5 M M 5 8 M VC NOTE: Output diodes are internal in LD. TEXAS INSTRUMENTS AVAILABLE OPTIONS PACKAGE TA C to C PLASTIC DIP (NE) LNE LDNE TA C to C AVAILABLE OPTIONS PACKAGED DEVICES SMALL OUTLINE (DWP) LDWP LDDWP PLASTIC DIP (N) LN LDN The DWP package is available taped and reeled. Add the suffix TR to device type (e.g., LDWPTR). POST OFFICE BOX 55 DALLAS, TEXAS 55
3 FUTION TABLE (each driver) INPUTS OUTPUT A EN Y H H H L H L X L Z H = high level, L = low level, X = irrelevant, Z = high impedance (off) In the thermal shutdown mode, the output is in the high-impedance state, regardless of the input levels. SLRS8B SEPTEMBER 8 REVISED JUNE logic diagram A,EN A A,EN A 5 ÁÁ Á Á Á Á ÁÁ Y Y Y Y schematics of inputs and outputs (L) EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS VCC VCC Current Source Input Output POST OFFICE BOX 55 DALLAS, TEXAS 55
4 SLRS8B SEPTEMBER 8 REVISED JUNE schematics of inputs and outputs (LD) EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS VCC VCC Current Source Input Output absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, V CC (see Note ) V Output supply voltage, V CC V Input voltage, V I V Output voltage range, V O V to V CC + V Peak output current, I O (nonrepetitive, t 5 ms): L ± A Peak output current, I O (nonrepetitive, t µs): LD ±. A Continuous output current, I O : L ± A Continuous output current, I O : LD ± ma Continuous total dissipation at (or below) 5 C free-air temperature (see Notes and ) mw Continuous total dissipation at 8 C case temperature (see Note ) mw Maximum junction temperature, T J C Lead temperature, mm (/ inch) from case for seconds C Storage temperature range, T stg C to 5 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES:. All voltage values are with respect to the network ground terminal.. For operation above 5 C free-air temperature, derate linearly at the rate of. mw/ C.. For operation above 5 C case temperature, derate linearly at the rate of. mw/ C. Due to variations in individual device electrical characteristics and thermal resistance, the built-in thermal overload protection may be activated at power levels slightly above or below the rated dissipation. POST OFFICE BOX 55 DALLAS, TEXAS 55
5 SLRS8B SEPTEMBER 8 REVISED JUNE recommended operating conditions VIH Supply voltage High-level input voltage MIN MAX UNIT VCC.5 VCC VCC V VCC V. VCC V VCC V. V VIL Low-level output voltage..5 V TA Operating free-air temperature C The algebraic convention, in which the least positive (most negative) designated minimum, is used in this data sheet for logic voltage levels. electrical characteristics, V CC = 5 V, V CC = V, T A = 5 C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH High-level output voltage L: IOH = A LD: IOH =. A VCC.8 VCC. V VOL Low-level output voltage L: IOL = A LD: IOL =. A..8 V VOKH High-level output clamp voltage LD: IOK =. A VCC +. V VOKL Low-level output clamp voltage LD: IOK =. A. V IIH High-level input current A EN VI =V.. µa IIL Low-level input current A VI = EN µa All outputs at high level ICC Logic supply current IO = All outputs at low level 5 ma All outputs at high impedance 8 All outputs at high level ICC Output supply current IO = All outputs at low level ma All outputs at high impedance switching characteristics, V CC = 5 V, V CC = V, T A = 5 C PARAMETER TEST CONDITIONS LNE, LDNE MIN TYP MAX UNIT tplh Propagation delay time, low-to-high-level output from A input 8 ns tphl Propagation delay time, high-to-low-level output from A input ns CL = pf, See Figure ttlh Transition time, low-to-high-level output ns tthl Transition time, high-to-low-level output ns switching characteristics, V CC = 5 V, V CC = V, T A = 5 C PARAMETER TEST CONDITIONS LDWP, LN LDDWP, LDN UNIT MIN TYP MAX tplh Propagation delay time, low-to-high-level output from A input 5 ns tphl Propagation delay time, high-to-low-level output from A input ns CL = pf, See Figure ttlh Transition time, low-to-high-level output ns tthl Transition time, high-to-low-level output 5 ns POST OFFICE BOX 55 DALLAS, TEXAS 55 5
6 SLRS8B SEPTEMBER 8 REVISED JUNE PARAMETER MEASUREMENT INFORMATION tf tr % % V Input 5 V V Input 5% 5% Pulse Generator (see Note B) V VCC VCC A Y EN Output CL = pf (see Note A) Output % % tw tphl tplh % % VOH 5% 5% % % VOL tthl ttlh TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The pulse generator has the following characteristics: tr ns, tf ns, tw = µs, PRR = 5 khz, ZO = 5 Ω. Figure. Test Circuit and Voltage Waveforms POST OFFICE BOX 55 DALLAS, TEXAS 55
7 APPLICATION INFORMATION SLRS8B SEPTEMBER 8 REVISED JUNE 5 V V kω VCC VCC,EN Control A A Y Motor A Y,EN Control B A Y A 5 Y Thermal Shutdown, 5,, Figure. Two-Phase Motor Driver (L) POST OFFICE BOX 55 DALLAS, TEXAS 55
8 SLRS8B SEPTEMBER 8 REVISED JUNE APPLICATION INFORMATION 5 V V kω VCC VCC,EN Control A A Y Motor A Y,EN Control B A Y A 5 Y Thermal Shutdown, 5,, Figure. Two-Phase Motor Driver (LD) 8 POST OFFICE BOX 55 DALLAS, TEXAS 55
9 SLRS8B SEPTEMBER 8 REVISED JUNE APPLICATION INFORMATION VCC SES5 M SES5 M 8 A A 5 / L, 5,, VCC EN EN A M A M H H Fast motor stop H Run H L Run L Fast motor stop L X Free-running motor stop L = low, H = high, X = don t care X Free-running motor stop Figure. DC Motor Controls (connections to ground and to supply voltage) VCC SES5 M SES5 A A 8 VCC / L, 5,, EN Figure 5. Bidirectional DC Motor Control EN A A FUTION H L H Turn right H H L Turn left H L L Fast motor stop H H H Fast motor stop L X X Fast motor stop L = low, H = high, X = don t care POST OFFICE BOX 55 DALLAS, TEXAS 55
10 SLRS8B SEPTEMBER 8 REVISED JUNE IL/IL = ma APPLICATION INFORMATION C. µf L 5 VCC D5 D + + D8 D VCC L IL 5 L IL D D D D D D8 = SES5 Figure. Bipolar Stepping-Motor Control mounting instructions The Rthj-amp of the L can be reduced by soldering the pins to a suitable copper area of the printed circuit board or to an external heatsink. Figure shows the maximum package power P TOT and the θ JA as a function of the side of two equal square copper areas having a thickness of 5 µm (see Figure ). In addition, an external heat sink can be used (see Figure 8). During soldering, the pin temperature must not exceed C, and the soldering time must not be longer than seconds. The external heatsink or printed circuit copper area must be connected to electrical ground. POST OFFICE BOX 55 DALLAS, TEXAS 55
11 APPLICATION INFORMATION SLRS8B SEPTEMBER 8 REVISED JUNE Copper Area 5-µm Thickness Printed Circuit Board Figure. Example of Printed Circuit Board Copper Area (used as heat sink). mm. mm 8. mm Figure 8. External Heat Sink Mounting Example (θ JA = 5 C/W) POST OFFICE BOX 55 DALLAS, TEXAS 55
12 SLRS8B SEPTEMBER 8 REVISED JUNE APPLICATION INFORMATION MAXIMUM POWER AND JUTION vs THERMAL RESISTAE 8 5 MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE TOT Power Dissipation W P θja PTOT (TA = C) 5 θja Thermal Resistance C/W P TOT Power Dissipation W With Infinite Heat Sink Heat Sink With θja = 5 C/W Free Air Side mm TA Ambient Temperature C Figure Figure POST OFFICE BOX 55 DALLAS, TEXAS 55
13 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Mailing Address: Texas Instruments Post Office Box 55 Dallas, Texas 55 Copyright, Texas Instruments Incorporated
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More informationDistributed by: www.jameco.com 1-800-81-4242 The content and copyrights of the attached material are the property of its owner. Operating Range 2-V to.-v V CC Latch-Up Performance Exceeds 20 ma Per JESD
More informationSN54AHC573, SN74AHC573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
Operating Range 2-V to 5.5-V V CC 3-State s Directly Drive Bus Lines Latch-Up Performance Exceeds 250 ma Per JESD 17 description The AHC573 devices are octal traparent D-type latches designed for 2-V to
More informationDistributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. Operating Range 2-V to 5.5-V V CC 3-State s Drive Bus Lines Directly Latch-Up
More informationMC1489, MC1489A, SN55189, SN55189A, SN75189, SN75189A QUADRUPLE LINE RECEIVERS
MC89, MC89A, SN89, SN89A, SN789, SN789A SLLS9B SEPTEMPER 97 REVISED MAY 99 Input Resistance... kω to 7 kω Input Signal Range...± V Operate From Single -V Supply Built-In Input Hysteresis (Double Thresholds)
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Member of the Texas Instruments Widebus Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 200 Per MIL-STD-883, Method 3015; Exceeds 20 Using Machine Model (C =
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Meet or Exceed the Requirements of ANSI EIA/TIA-232-E and ITU Recommendation V.28 Very Low Power Consumption 5 mw Typ Wide Driver Supply Voltage Range ±4.5 V to ±15 V Driver Output Slew Rate Limited to
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Independent Asychronous Inputs and Outputs 16 Words by 5 Bits DC to 10-MHz Rate 3-State Outputs Packaged in Standard Plastic 300-mil DIPs description This 80-bit active-element memory is a monolithic Schottky-clamped
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SCLS07B DECEMBER 92 REVISED MAY 997 Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK),
More informationCD54ACT74, CD74ACT74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
s Are TTL-Voltage ompatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power onsumption Balanced Propagation Delays ±24-mA Drive urrent Fanout to 5 F Devices SR-Latchup-Resistant MOS Process
More informationSN54HC573A, SN74HC573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS147B DECEMBER 1982 REVISED MAY 1997
High-Current -State s Drive Bus Lines Directly or up to LSTTL Loads Bus-Structured Pinout Package Options Include Plastic Small-Outline (DW) and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and
More informationTL594 PULSE-WIDTH-MODULATION CONTROL CIRCUIT
Complete PWM Power Control Circuitry Uncommitted Outputs for 200-mA Sink or Source Current Output Control Selects Single-Ended or Push-Pull Operation Internal Circuitry Prohibits Double Pulse at Either
More informationSN54LVC14A, SN74LVC14A HEX SCHMITT-TRIGGER INVERTERS
Typical V OLP ( Ground Bounce) 2 V at V CC = 3.3 V, T A = 25 C s Accept Voltages to 5.5 V Latch-Up Performance Exceeds 100 ma Per JESD
More informationSN54ALS00A, SN54AS00, SN74ALS00A, SN74AS00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES
Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description These devices contain four independent 2-input positive-nand
More informationSN54HC373, SN74HC373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS140B DECEMBER 1982 REVISED MAY 1997
Eight High-Current Latches in a Single Package High-Current -State True s Can Drive up to LSTTL Loads Full Parallel Access for Loading Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline
More informationSN54HCT373, SN74HCT373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
Inputs Are TTL-Voltage Compatible Eight High-Current Latches in a Single Package High-Current -State True s Can Drive up to LSTTL Loads Full Parallel Access for Loading Package Optio Include Plastic Small-Outline
More information74AC11373 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
74A7 Eight Latches in a Single Package -State Bus-Driving True s Full Parallel Access for Loading Buffered Control Inputs Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and Configuratio
More informationSN54AS825A, SN74AS825A 8-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS020B JUNE 1984 REVISED AUGUST 1995
Functionally Equivalent to AMD s AM2982 Improved I OH Specificatio Multiple Output Enables Allow Multiuser Control of the Interface Outputs Have Undershoot-Protection Circuitry Power-Up High-Impedance
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Low r S(on)... Ω Typ Output Short-Circuit Protection Avalanche Energy...75 mj Eight 35-mA MOS Outputs 5-V Switching Capability evices Are Cascadable Low Power Consumption description The TPIC6A595 is a
More informationSN54AHCT174, SN74AHCT174 HEX D-TYPE FLIP-FLOPS WITH CLEAR
Inputs Are TTL-Voltage Compatible EPIC (Enhanced-Performance Implanted CMOS) Process Contain Six Flip-Flops With Single-Rail s Applicatio Include: Buffer/Storage Registers Shift Registers Pattern Generators
More informationSN54ACT241, SN74ACT241 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
Inputs Are TTL Compatible EPIC (Enhanced-Performance Implanted CMOS) -µm Process Package Optio Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and DIP (N)
More informationSN54ALS873B, SN54AS873A, SN74ALS873B, SN74AS873A DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS036D APRIL 1982 REVISED AUGUST 1995
3-State Buffer-Type Outputs Drive Bus Lines Directly Bus-Structured Pinout Package Optio Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs
More informationSN74ALVCHR BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
Member of the Texas Instruments Widebus Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process UBT (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in
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±1% Output Tolerance at ±2% Output Tolerance Over Full Operating Range Thermal Shutdown description Internal Short-Circuit Current Limiting Pinout Identical to µa7800 Series Improved Version of µa7800
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Convert TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays description These hex buffers/drivers feature
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Compare Two -Bit Words Totem-Pole Outputs () ALS Are Identical to ALS2 Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J)
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EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Useful for Jumperless Configuration of PC Motherboard Inputs Accept Voltages to 5.5 V Signals are 2.5-V Outputs Signal is a 3.3-V Output Minimum
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Operating Range 2-V to 5.5-V V CC Latch-Up Performance Exceeds 250 m Per JESD 17 description The SN74HC1G04 contai one inverter gate. The device performs the Boolean function =. DBV OR DCK PCKGES (TOP
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SN676B, SN776B Bidirectional Transceivers Meet or Exceed the Requirements of ANSI Standards TIA/EIA--B and TIA/EIA-8-A and ITU Recommendations V. and X.7 Designed for Multipoint Transmission on Long Bus
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Package Optio Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs TYPE TYPICAL MAXIMUM CLOCK FREUEY (CL = 0 pf) (MHz) TYPICAL POWER
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Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and GND Configuratio Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-µm
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Members of the Texas Itruments Widebus Family Inputs Are TTL-Voltage Compatible 3-State Bus Driving True s Full Parallel Access for Loading Flow-Through Architecture Optimizes PCB Layout Distributed and
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Bidirectional Transceivers Meet or Exceed the Requirements of ANSI Standards TIA/EIA--B and TIA/EIA-8-A and ITU Recommendations V. and X.7 Designed for Multipoint Transmission on Long Bus Lines in Noisy
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Convert TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays s Fully Compatible With Most TTL Circuits
More informationdescription/ordering information
Meets or Exceeds TIA/EIA-232-F and ITU Recommendation V.28 Operates From a Single 5-V Power Supply With 1.0-F Charge-Pump Capacitors Operates Up To 120 kbit/s Two Drivers and Two Receivers ±30-V Input
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5-V Digital or ±7.5-V Peak-to-Peak Switching 5-Ω Typical On-State Resistance for 5-V Operation Switch On-State Resistance Matched to Within 5 Ω Over 5-V Signal-Input Range On-State Resistance Flat Over
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Complementary Switch FET Drivers application INFO available FEATURES Single Input (PWM and TTL Compatible) High Current Power FET Driver, 1.0A Source/2A Sink Auxiliary Output FET Driver, 0.5A Source/1A
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Complete PWM Power Control Circuitry Uncommitted Outputs for 200-mA Sink or Source Current Output Control Selects Single-Ended or Push-Pull Operation Internal Circuitry Prohibits Double Pulse at Either
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ULNA, ULNA, ULNA, ULNA SLRS DECEMBER REVISED APRIL HIGH-VOLTAGE HIGH-CURRENT -ma Rated Collector Current (Single ) High-Voltage s... V Clamp Diodes Inputs Compatible With Various Types of Logic Relay Driver
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Single Supply or Dual Supplies Wide Range of Supply Voltage...2 V to 36 V Low Supply-Current Drain Independent of Supply Voltage... 0.8 ma Typ Low Input Bias Current... 25 Typ Low Input Offset Current...3
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POWER LOGIC OCTAL -TYPE LATC Low r S(on)... Ω Typical Avalanche Energy...3 mj Eight Power MOS-Transistor Outputs of -ma Continuous Current -ma Typical Current-Limiting Capability Output Clamp Voltage...
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POWER OIC 8-BIT ARESSABE ATC ow r S(on).... Ω Typical Avalanche Energy...75 mj Eight Power MOS Transistor Outputs of 5-mA Continuous Current.5-A Pulsed Current Per Output Output Clamp Voltage at Four istinct
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ULNA THRU ULNA SLRS D, DECEMBER REVISED APRIL HIGH-VOLTAGE HIGH-CURRENT -ma Rated Collector Current (Single ) High-Voltage s... V Clamp Diodes Inputs Compatible With Various Types of Logic Relay Driver
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