SN74ACT STROBED FIRST-IN, FIRST-OUT MEMORY

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1 Member of the Texas Itruments idebus Family Load Clock and Unload Clock Can Be Asynchronous or Coincident 256 ords by 18 Bits Low-Power Advanced CMOS Technology Full, Empty, and Half-Full Flags Programmable Almost-Full/Almost-Empty Flag Fast Access Times of 15 ith a 5-pF Load and All Data Outputs Switching Simultaneously Data Rates up to 5 MHz 3-State Outputs Pin-to-Pin Compatible ith SN74ACT784 and SN74ACT7814 Packaged in Shrink Small-Outline 3-mil Package Using 25-mil Center-to-Center Spacing description A FIFO memory is a storage device that allows data to be written into and read from its array at independent data rates. The SN74ACT786 is a 256-word by 18-bit FIFO for high speed and fast access times. It processes data at rates up to 5 MHz and access times of 15 in a bit-parallel format. Data is written into memory on a low-to-high traition at the load clock () input and is read out on a low-to-high traition at the unload clock () input. The memory is full when the number of words clocked in exceeds the number of words clocked out by 256. hen the memory is full, signals have no effect on the data residing in memory. hen the memory is empty, signals have no effect. SN74ACT786 D17 D16 D15 D14 D13 D12 D11 D1 V CC D9 D8 GND D7 D6 D5 D4 D3 D2 D1 D HF PEN AF/AE NC NC DL PACKAGE (TOP VIE) Status of the FIFO memory is monitored by the full (), empty (), half-full (HF), and almost-full/almost-empty (AF/AE) flags. The output is low when the memory is full and high when the memory is not full. The output is low when the memory is empty and high when it is not empty. The HF output is high when the FIFO contai 128 or more words. The AF/AE status flag is a programmable flag. The first one or two low-to-high traitio of after reset are used to program the almost-empty offset value (X) and the almost-full offset value (Y) if program enable (PEN) is low. The AF/AE flag is high when the FIFO contai X or fewer words or (256 Y) or more words. The AF/AE flag is low when the FIFO contai between (X + 1) and (255 Y) words Q17 Q16 Q15 GND Q14 V CC Q13 Q12 Q11 Q1 Q9 GND Q8 Q7 Q6 Q5 V CC Q4 Q3 Q2 GND Q1 Q NC NC NC No internal connection Please be aware that an important notice concerning availability, standard warranty, and use in critical applicatio of Texas Itruments semiconductor products and disclaimers thereto appears at the end of this data sheet. idebus is a trademark of Texas Itruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specificatio per the terms of Texas Itruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 1998, Texas Itruments Incorporated POST OFFICE BOX DALLAS, TEXAS

2 description (continued) A low level on the reset () input resets the internal stack pointers and sets high, HF low, and low. The Q outputs are not reset to any specific logic level. The FIFO must be reset upon power up.the first word loaded into empty memory causes to go high and the data to appear on the Q outputs. It is important to note that the first word does not have to be unloaded. The data outputs are noninverting with respect to the data inputs and are in the high-impedance state when the output-enable () input is high. The SN74ACT786 is characterized for operation from C to 7 C. logic symbol PEN EN1 Φ FIFO SN74ACT786 PROGRAM ENABLE HALF- ALMOST / HF AF/AE D D1 D2 D3 D4 D5 D6 D7 D8 D9 D1 D11 D12 D13 D14 D15 D16 D Data Data Q Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q1 Q11 Q12 Q13 Q14 Q15 Q16 Q17 This symbol is in accordance with ANSI/IEEE Std and IEC Publication POST OFFICE BOX DALLAS, TEXAS 75265

3 functional block diagram D D17 Read Pointer Location 1 Location 2 SRAM rite Pointer Location 255 Location 256 Q Q17 PEN Reset Logic Status- Flag Logic HF AF/AE Terminal Functio TERMINAL NAME NO. I/O DESCRIPTION AF/AE 24 O Almost-full/almost-empty flag. Depth-offset values can be programmed for AF/AE, or the default value of 32 can be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AE is high when memory contai X or fewer words or (256 Y) or more words. AF/AE is high after reset. D D17 2 9, 11 12, I 18-bit data input port 29 O Empty flag. is high when the FIFO memory is not empty; is low when the FIFO memory is empty or upon assertion of. 28 O Full flag. is high when the FIFO memory is not full or upon assertion of ; is low when the FIFO memory is full. HF 22 O Half-full flag. HF is high when the FIFO memory contai 128 or more words. HF is low after reset. 25 I Load clock. Data is written to the FIFO on the rising edge of when is high. 56 I Output enable. hen is high, the data outputs are in the high-impedance state. PEN 23 I Program enable. After reset and before the first word is written to the FIFO, the binary value on D D6 is latched as an AF/AE offset value when PEN is low and RTCLK is high. Q Q , 36 38, 4 43, 45 49, O 18-bit data output port 51, I Reset. A low level on this input resets the FIFO and drives high and HF and low. 32 I Unload clock. Data is read from the FIFO on the rising edge of when is high. POST OFFICE BOX DALLAS, TEXAS

4 offset values for AF/AE The AF/AE flag has two programmable limits, the almost-empty offset value (X) and the almost-full offset value (Y). They can be programmed after the FIFO is reset and before the first word is written to memory. The AF/AE flag is high when the FIFO contai X or fewer words or (256 Y) or more words. To program the offset values, PEN can be brought low after reset only when is low. On the following low-to-high traition of, the binary value on D D6 is stored as the almost-empty offset value (X) and the almost-full offset value (Y). Holding PEN low for another low-to-high traition of reprograms Y to the binary value on D D6 at the time of the second low-to-high traition. rites to the FIFO memory are disabled while the offsets are programmed. A maximum value of 127 can be programmed for either X or Y (see Figure 1). To use the default values of X = Y = 32, PEN must be held high. PEN ÎÎÎÎÎÎÎÎÎÎ Don t Care D D6 Don t Care X and Y Y ÌÌÌÌÌ Figure 1. Programming X and Y Separately 4 POST OFFICE BOX DALLAS, TEXAS 75265

5 1 PEN Don t Care 256 (256 Y) (X+1) D D (257 X) (256 X) (Y+2) (Y+1) 1 Q Q17 Ï AF/AE HF Define the AF/AE Flag Using the Default Value of X and Y Figure 2. rite, Read, and Flag Timing Reference POST OFFICE BOX DALLAS, TEXAS

6 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V CC V to 7 V Input voltage range, V I V to 7 V Voltage range applied to a disabled 3-state output V to 5.5 V Package thermal impedance, θ JA (see Note 1) C/ Storage temperature range, T stg C to 15 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated under recommended operating conditio is not implied. Exposure to absolute-maximum-rated conditio for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditio ACT786-2 ACT ACT786-4 UNIT MIN MAX MIN MAX MIN MAX VCC Supply voltage V VIH High-level input voltage V VIL Low-level input voltage V IOH High-level output current Q outputs, flags ma IOL Low-level output current Q outputs Flags TA Operating free-air temperature C ma electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH VCC = 4.5 V, IOH = 8 ma 2.4 V VOL Flags VCC = 4.5 V, IOL = 8 ma.5 Q outputs VCC = 4.5 V, IOL = 16 ma.5 II VCC = 5.5 V, VI = VCC or ±5 µa IOZ VCC = 5.5 V, VO = VCC or ±5 µa ICC VCC = 5.5 V, VI = VCC.2 V or 4 µa ICC VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND 1 ma Ci VI =, f = 1 MHz 4 pf Co VO =, f = 1 MHz 8 pf All typical values are at VCC = 5 V, TA = 25 C. This is the supply current for each input that is at one of the specified TTL voltage levels rather than V or VCC. V 6 POST OFFICE BOX DALLAS, TEXAS 75265

7 timing requirements over recommended operating conditio (see Figures 1 through 3) ACT786-2 ACT ACT786-4 MIN MAX MIN MAX MIN MAX fclock Clock frequency MHz tw Pulse duration high or low high or low PEN low low D D17 before tsu Setup time PEN before th Hold time inactive before high D D17 after inactive after high PEN low after PEN high after UNIT switching characteristics over recommended ranges of supply voltage and operating free-air temperature, C L = 5 pf (unless otherwise noted) (see Figures 5 and 6) PARAMETER FROM TO ACT786-2 ACT ACT786-4 (INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX fmax or MHz tpd Any Q tpd Any Q 1.5 tplh tphl tplh tpd tplh tphl low UNIT low AF/AE low AF/AE HF low HF ten Any Q tdis Any Q All typical values are at VCC = 5 V, TA = 25 C. This parameter is measured at CL = 3 pf (see Figure 4). operating characteristics, V CC = 5 V, T A = 25 CFigure 2 PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance per FIFO channel Outputs enabled CL = 5 pf, f = 5 MHz 53 pf POST OFFICE BOX DALLAS, TEXAS

8 7 V PARAMETER MEASUREMENT INFORMATION From Output Under Test CL = 5 pf (see Note A) S1 5 Ω 5 Ω Test Point PARAMETER ten tdis tpd tpzh tpzl tphz tplz tplh tphl S1 Open Closed Open Closed Open Open tw LOAD CIRCUIT 3 V Timing Input 1.5 V 3 V V Input 1.5 V 1.5 V VOLTAGE AVEFORMS PULSE DURATION V tsu th Data Input 1.5 V 1.5 V VOLTAGE AVEFORMS SETUP AND HOLD TIMES 3 V V Output Control tpzl 1.5 V tplz 1.5 V 3 V V Input Output tplh 1.5 V 1.5 V tphl 1.5 V 1.5 V 3 V V VOH VOL Output aveform 1 S1 at 7 V Output aveform 2 S1 at Open tpzh 1.5 V tphz 1.5 V 3.5 V VOL +.3 V VOL VOH VOH.3 V V VOLTAGE AVEFORMS PROPAGATION DELAY TIMES VOLTAGE AVEFORMS ENABLE AND DISABLE TIMES NOTE A: CL includes probe and jig capacitance. Figure 3. Load Circuit and Voltage aveforms 8 POST OFFICE BOX DALLAS, TEXAS 75265

9 TYPICAL CHARACTERISTICS SN74ACT786 Propagation Delay Time pd t typ + 8 typ + 6 typ + 4 typ + 2 typ VCC = 5 V TA = 25 C RL = 5 Ω PROPAGATION DELAY TIME vs LOAD CAPACITANCE Supply Current ma CC(f) I TA = 75 C CL = pf SUPPLY CURRENT vs CLOCK FREQUENCY VCC = 5 V VCC = 5.5 V VCC = 4.5 V 2 typ CL Load Capacitance pf fclock Clock Frequency MHz Figure 4 Figure 5 APPLICATION INFORMATION SN74ACT786 D18 D35 D D17 Q Q17 Q18 Q35 SN74ACT786 D D17 D D17 Q Q17 Q Q17 Figure 6. ord-idth Expaion: Bits POST OFFICE BOX DALLAS, TEXAS

10 IMPORTANT NOTICE Texas Itruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditio of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specificatio applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ( CRITICAL APPLICATIONS ). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR ARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE Y AT THE CUSTOMER S RISK. In order to minimize risks associated with the customer s applicatio, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applicatio assistance or customer product design. TI does not warrant or represent that any licee, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not cotitute TI s approval, warranty or endorsement thereof. Copyright 1998, Texas Itruments Incorporated

SN54ACT16373, 74ACT BIT D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

SN54ACT16373, 74ACT BIT D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS Members of the Texas Itruments Widebus Family Inputs Are TTL-Voltage Compatible 3-State Bus Driving True s Full Parallel Access for Loading Flow-Through Architecture Optimizes PCB Layout Distributed and