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2 Operating Range 2-V to 5.5-V V CC 3-State s Drive Bus Lines Directly Latch-Up Performance Exceeds 250 ma Per JESD 17 ESD Protection Exceeds JESD V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101) description The AHC574 devices are octal edge-triggered D-type flip-flops that feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. On the positive traition of the clock (CLK) input, the Q outputs are set to the logic levels of the data (D) inputs. A buffered output-enable (OE) input places the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components. SN54AHC574...J OR W PACKAGE SN74AHC DB, DGV, DW, N, NS, OR PW PACKAGE (TOP VIEW) SN54AHC FK PACKAGE (TOP VIEW) OE does not affect internal operatio of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To eure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. 3D 4D 5D 6D 7D OE 1D 2D 3D 4D 5D 6D 7D 8D GND D 1D OE V CC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q CLK D GND CLK V CC 8Q 7Q 1Q 2Q 3Q 4Q 5Q 6Q Please be aware that an important notice concerning availability, standard warranty, and use in critical applicatio of Texas Itruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specificatio per the terms of Texas Itruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2002, Texas Itruments Incorporated On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX DALLAS, TEXAS

3 TA ORDERING INFORMATION PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP N Tube SN74AHC574N SN74AHC574N SOIC DW Tube Tape and reel SN74AHC574DW SN74AHC574DWR AHC C to 85 C SOP NS Tape and reel SN74AHC574NSR AHC574 SSOP DB Tape and reel SN74AHC574DBR HA574 TSSOP PW Tape and reel SN74AHC574PWR HA574 TVSOP DGV Tape and reel SN74AHC574DGVR HA574 CDIP J Tube SNJ54AHC574J SNJ54AHC574J 55 C to 125 C CFP W Tube SNJ54AHC574W SNJ54AHC574W LCCC FK Tube SNJ54AHC574FK SNJ54AHC574FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at FUNCTION TABLE (each flip-flop) INPUTS OUTPUT OE CLK D Q L H H L L L L H or L X Q0 H X X Z logic diagram (positive logic) OE 1 CLK 11 1D 2 1D C1 19 1Q To Seven Other Channels 2 POST OFFICE BOX DALLAS, TEXAS 75265

4 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V CC V to 7 V Input voltage range, V I (see Note 1) V to 7 V voltage range, V O (see Note 1) V to V CC V Input clamp current, I IK (V I < 0) ma clamp current, I OK (V O < 0 or V O > V CC ) ±20 ma Continuous output current, I O (V O = 0 to V CC ) ±25 ma Continuous current through V CC or GND ±75 ma Package thermal impedance, θ JA (see Note 2): DB package C/W DGV package C/W DW package C/W N package C/W NS package C/W PW package C/W Storage temperature range, T stg C to 150 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated under recommended operating conditio is not implied. Exposure to absolute-maximum-rated conditio for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD recommended operating conditio (see Note 3) SN54AHC574 SN74AHC574 MIN MAX MIN MAX Supply voltage V = 2 V VIH High-level input voltage = 3 V V = 5.5 V = 2 V VIL Low-level input voltage = 3 V V = 5.5 V VI Input voltage V VO voltage 0 0 V = 2 V A IOH High-level output current = 3.3 V ± 0.3 V 4 4 = 5 V ± 0.5 V 8 8 ma = 2 V A IOL Low-level output current = 3.3 V ± 0.3 V 4 4 t/ v Input traition rise or fall rate = 5 V ± 0.5 V 8 8 = 3.3 V ± 0.3 V = 5 V ± 0.5 V TA Operating free-air temperature C NOTE 3: All unused inputs of the device must be held at or GND to eure proper device operation. Refer to the TI application report, Implicatio of Slow or Floating CMOS Inputs, literature number SCBA004. ma /V POST OFFICE BOX DALLAS, TEXAS

5 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS TA = 25 C SN54AHC574 SN74AHC574 MIN TYP MAX MIN MAX MIN MAX 2 V IOH = 50 A 3 V VOH 4.5 V V OH IOH = 4 ma 3 V IOH = 8 ma 4.5 V V IOL = 50 A 3 V VOL 4.5 V V OL IOL = 4 ma 3 V IOL = 8 ma 4.5 V II VI = 5.5 V or GND to 5.5 V ±0.1 ±1* ±1 A IOZ VO = or GND 5.5 V ±0.25 ±2.5 ±2.5 A ICC VI = or GND, IO = V A Ci VI = or GND 5 V pf Co VO = or GND 5 V 3 pf * On products compliant to MIL-PRF-38535, this parameter is not production tested at =. timing requirements over recommended operating free-air temperature range, V CC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TA = 25 C SN54AHC574 SN74AHC574 MIN MAX MIN MAX MIN MAX tw Pulse duration, CLK high or low tsu Setup time, data before CLK th Hold time, data after CLK timing requirements over recommended operating free-air temperature range, V CC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25 C SN54AHC574 SN74AHC574 MIN MAX MIN MAX MIN MAX tw Pulse duration, CLK high or low tsu Setup time, data before CLK th Hold time, data after CLK POST OFFICE BOX DALLAS, TEXAS 75265

6 switching characteristics over recommended operating free-air temperature range, V CC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER fmax FROM TO LOAD TA = 25 C SN54AHC574 SN74AHC574 (INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX CLK Q CL = 15 pf OE Q CL = 15 pf OE Q CL = 15 pf CLK Q CL = 50 pf OE Q CL = 50 pf OE Q CL = 50 pf CL = 15 pf 80* 125* 65* 65 CL = 50 pf * 13.2* 1* 15.5* * 13.2* 1* 15.5* * 12.8* 1* 15* * 12.8* 1* 15* * 13* 1* 15* * 13* 1* 15* tsk(o) CL = 50 pf 1.5** 1.5 On products compliant to MIL-PRF-38535, this parameter is not production tested. On products compliant to MIL-PRF-38535, this parameter does not apply. switching characteristics over recommended operating free-air temperature range, V CC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER fmax FROM TO LOAD TA = 25 C SN54AHC574 SN74AHC574 (INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX CLK Q CL = 15 pf OE Q CL = 15 pf OE Q CL = 15 pf CLK Q CL = 50 pf OE Q CL = 50 pf OE Q CL = 50 pf CL = 15 pf 130* 180* 110* 110 CL = 50 pf * 8.6* 1* 10* * 8.6* 1* 10* * 9* 1* 10.5* * 9* 1* 10.5* * 9* 1* 10.5* * 9* 1* 10.5* tsk(o) CL = 50 pf 1** 1 On products compliant to MIL-PRF-38535, this parameter is not production tested. On products compliant to MIL-PRF-38535, this parameter does not apply. MHz MHz POST OFFICE BOX DALLAS, TEXAS

7 noise characteristics, V CC = 5 V, C L = 50 pf, T A = 25 C (see Note 4) PARAMETER SN74AHC574 VOL(P) Quiet output, maximum dynamic VOL 0.8 V VOL(V) Quiet output, minimum dynamic VOL 0.8 V VOH(V) Quiet output, minimum dynamic VOH 4.2 V VIH(D) High-level dynamic input voltage 3.5 V VIL(D) Low-level dynamic input voltage 1.5 V NOTE 4: Characteristics are for surface-mount packages only. operating characteristics, V CC = 5 V, T A = 25 C MIN MAX PARAMETER TEST CONDITIONS TYP Cpd Power dissipation capacitance No load, f = 1 MHz 28 pf 6 POST OFFICE BOX DALLAS, TEXAS 75265

8 PARAMETER MEASUREMENT INFORMATION From Under Test CL (see Note A) Test Point From Under Test CL (see Note A) RL = 1 kω S1 Open GND TEST / / / Open Drain S1 Open GND LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS Input 50% tw 50% Timing Input Data Input tsu 50% th 50% 50% VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Input In-Phase Out-of-Phase 50% 50% 50% 50% VOH 50% VOL VOH 50% VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Control Waveform 1 S1 at (see Note B) Waveform 2 S1 at GND (see Note B) 50% 50% 50% 50% VOL V VOL VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING VOH VOH 0.3 V NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditio such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditio such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 Ω, tr 3, tf 3. D. The outputs are measured one at a time with one input traition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX DALLAS, TEXAS

9 IMPORTANT NOTICE Texas Itruments Incorporated and its subsidiaries (TI) reserve the right to make correctio, modificatio, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI s terms and conditio of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specificatio applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applicatio assistance or customer product design. Customers are respoible for their products and applicatio using TI components. To minimize the risks associated with customer products and applicatio, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any licee, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third party products or services does not cotitute a licee from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a licee from a third party under the patents or other intellectual property of the third party, or a licee from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditio, limitatio, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not respoible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not respoible or liable for any such statements. Mailing Address: Texas Itruments Post Office Box Dallas, Texas Copyright 2002, Texas Itruments Incorporated

SN54AHC573, SN74AHC573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

SN54AHC573, SN74AHC573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS Operating Range 2-V to 5.5-V V CC 3-State s Directly Drive Bus Lines Latch-Up Performance Exceeds 250 ma Per JESD 17 description The AHC573 devices are octal traparent D-type latches designed for 2-V to