SN54HC126, SN74HC126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

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1 SN54HC26, SN74HC26 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCLS03E MARCH 94 REVISED JULY 2003 Wide Operating Voltage Range of 2 V to 6 V High-Current 3-State Outputs Interface Directly With System Bus or Can Drive Up To 5 LSTTL Loads Low Power Consumption, 0-µA Max I CC Typical t pd = ns ±6-mA Output Drive at 5 V Low Input Current of µa Max SN54HC26...J OR W PACKAGE SN74HC26... D, DB, N, NS, OR PW PACKAGE (TOP VIEW) OE A Y 2OE 2A 2Y GND V CC 4OE 4A 4Y 3OE 3A 3Y Y NC 2OE NC 2A SN54HC26...FK PACKAGE (TOP VIEW) A OE NC V CC 4OE A NC 4Y NC 3OE 2Y GND NC 3Y 3A description/ordering information NC No internal connection These quadruple bus buffer gates feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pullup resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. TA ORDERING INFORMATION PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP N Tube of 25 SN74HC26N SN74HC26N Tube of 50 SN74HC26D SOIC D Reel of 2500 SN74HC26DR HC26 Reel of 250 SN74HC26DT 40 C to 5 C SOP NS Reel of 2000 SN74HC26NSR HC26 SSOP DB Reel of 2000 SN74HC26DBR HC26 Tube of 90 SN74HC26PW TSSOP PW Reel of 2000 SN74HC26PWR HC26 Reel of 250 SN74HC26PWT CDIP J Tube of 25 SNJ54HC26J SNJ54HC26J 55 C to 25 C CFP W Tube of 50 SNJ54HC26W SNJ54HC26W LCCC FK Tube of 55 SNJ54HC26FK SNJ54HC26FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2003, Texas Instruments Incorporated On products compliant to MIL-PRF-3535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

2 SN54HC26, SN74HC26 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCLS03E MARCH 94 REVISED JULY 2003 FUNCTION TABLE (each buffer) INPUTS OUTPUT OE A Y H H H H L L L X Z logic diagram (positive logic) OE 3OE 0 A 2 3 Y 3A 9 3Y 2OE 4 4OE 3 2A 5 6 2Y 4A 2 4Y Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V CC V to 7 V Input clamp current, I IK (V I < 0 or V I > V CC ) (see Note ) ±20 ma Output clamp current, I OK (V O < 0 or V O > V CC ) (see Note ) ±20 ma Continuous output current, I O (V O = 0 to V CC ) ±35 ma Continuous current through V CC or GND ±70 ma Package thermal impedance, θ JA (see Note 2): D package C/W DB package C/W N package C/W NS package C/W PW package C/W Storage temperature range, T stg C to 50 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES:. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD

3 SN54HC26, SN74HC26 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCLS03E MARCH 94 REVISED JULY 2003 recommended operating conditions (see Note 3) SN54HC26 SN74HC26 MIN NOM MAX MIN NOM MAX VCC Supply voltage V VCC = 2 V.5.5 VIH High-level input voltage VCC = 4.5 V V VCC = 6 V VCC = 2 V VIL Low-level input voltage VCC = 4.5 V V VCC = 6 V.. VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V VCC = 2 V t/ v Input transition rise/fall time VCC = 4.5 V ns VCC = 6 V TA Operating free-air temperature C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC VOH VI I = VIH or VIL VOL VI I = VIH or VIL TA = 25 C SN54HC26 SN74HC26 MIN TYP MAX MIN MAX MIN MAX 2 V IOH = 20 µa 4.5 V V V IOH = 6 ma 4.5 V IOH = 7. ma 6 V V IOL = 20 µa 4.5 V V V IOL = 6 ma 4.5 V IOL = 7. ma 6 V II VI = VCC or 0 6 V ±0. ±00 ±000 ±000 na IOZ VO = VCC or 0 6 V ±0.0 ±0.5 ±0 ±5 µa ICC VI = VCC or 0, IO = 0 6 V 60 0 µa Ci 2 V to 6 V pf UNIT UNIT 3

4 SN54HC26, SN74HC26 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCLS03E MARCH 94 REVISED JULY 2003 switching characteristics over recommended operating free-air temperature range, C L = 50 pf (unless otherwise noted) (see Figure ) PARAMETER FROM (INPUT) TO (OUTPUT) VCC TA = 25 C SN54HC26 SN74HC26 MIN TYP MAX MIN MAX MIN MAX 2 V tpd A Y 4.5 V ns 6 V V ten OE Y 4.5 V ns 6 V V tdis OE Y 4.5 V ns 6 V V ttt Any 4.5 V 2 5 ns 6 V UNIT switching characteristics over recommended operating free-air temperature range, C L = 50 pf (unless otherwise noted) (see Figure ) PARAMETER FROM (INPUT) TO (OUTPUT) VCC TA = 25 C SN54HC26 SN74HC26 MIN TYP MAX MIN MAX MIN MAX 2 V tpd A Y 4.5 V ns 6 V V ten OE Y 4.5 V ns 6 V V ttt Any 4.5 V ns 6 V UNIT operating characteristics, T A = 25 C PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance per gate No load 45 pf 4

5 PARAMETER MEASUREMENT INFORMATION SN54HC26, SN74HC26 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCLS03E MARCH 94 REVISED JULY 2003 VCC PARAMETER RL CL S S2 From Output Under Test CL (see Note A) Test Point RL LOAD CIRCUIT S S2 ten tpzh tpzl tdis tphz tplz tpd or tt kω kω 50 pf or 50 pf 50 pf 50 pf or 50 pf Open Closed Open Closed Open Closed Open Closed Open Open Input VCC 0 V tplh tphl In-Phase Output Out-of-Phase Output 0% tphl 90% 90% 90% VOH 0% VOL tf VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES tr 0% 0% tf tplh VOH 90% VOL tr Output Control Output Waveform (See Note B) tpzl tplz 0% VCC 0 V VCC VOL tpzh tphz Input 0% 90% 90% tr VCC 0% 0 V tf Output Waveform 2 (See Note B) 90% VOH 0 V VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tplz and tphz are the same as tdis. F. tpzl and tpzh are the same as ten. G. tplh and tphl are the same as tpd. Figure. Load Circuit and Voltage Waveforms 5

7 MECHANICAL DATA MLCC006B OCTOBER 996 FK (S-CQCC-N**) 2 TERMINAL SHOWN LEADLESS CERAMIC CHIP CARRIER NO. OF TERMINALS ** MIN A MAX MIN B MAX (,69) 0.35 (9,09) (7,0) 0.35 (9,09) A SQ B SQ (,23) (6,26) (,7) 0.93 (23,3).4 (2,99) 0.45 (,63) (6,76) 0.76 (9,32) (24,43).65 (29,59) (0,3) (2,5) (2,5) 0.50 (2,6).047 (26,6) 0.45 (,63) (4,22) (4,22) 0.5 (2,).063 (27,0) (0,5) 0.00 (0,25) 0.00 (2,03) (,63) (0,5) 0.00 (0,25) (,40) (,4) (,4) (0,9) 0.02 (0,7) (0,54) (,27) (,4) (0,9) / D 0/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDEC MS-004

8 MPDI002C JANUARY 995 REVISED DECEMBER N (R-PDIP-T**) 6 PINS SHOWN PLASTIC DUAL-IN-LINE PACKAGE DIM PINS ** A A MAX (9,69) (9,69) (23,37).060 (26,92) 6 9 A MIN (,92) (,92) 0.50 (2,59) (23,) (6,60) (6,0) C MS-00 VARIATION AA BB AC AD (,7) (,4) D (,4) (0,76) D (0,5) MIN (,26) (7,62) 0.05 (0,3) (5,0) MAX Gauge Plane Seating Plane 0.25 (3,) MIN 0.00 (0,25) NOM 0.02 (0,53) 0.05 (0,3) 0.00 (0,25) 0.00 (2,54) M (0,92) MAX 4/ PIN ONLY 20 pin vendor option D /E 2/2002 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-00, except and 20 pin minimum body lrngth (Dim A). D. The 20 pin end lead shoulder width is a vendor option, either half or full width.

9 MECHANICAL DATA MSOI002B JANUARY 995 REVISED SEPTEMBER 200 D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE PINS SHOWN (,27) (0,5) 0.04 (0,35) 0.00 (0,25) (6,20) 0.22 (5,0) 0.00 (0,20) NOM 0.57 (4,00) 0.50 (3,) Gage Plane 4 A (0,25) (,2) 0.06 (0,40) Seating Plane (,75) MAX 0.00 (0,25) (0,0) (0,0) DIM PINS ** 4 6 A MAX 0.97 (5,00) (,75) (0,00) A MIN (4,0) (,55) 0.36 (9,0) /E 09/0 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed (0,5). D. Falls within JEDEC MS-02

11 MECHANICAL DATA MSSO002E JANUARY 995 REVISED DECEMBER 200 DB (R-PDSO-G**) 2 PINS SHOWN PLASTIC SMALL-OUTLINE 0,65 0,3 0,22 0,5 M 2 5 5,60 5,00,20 7,40 0,25 0,09 Gage Plane 4 0,25 A 0 0,95 0,55 2,00 MAX 0,05 MIN Seating Plane 0,0 DIM PINS ** A MAX 6,50 6,50 7,50,50 0,50 0,50 2,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 2, /E 2/0 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,5. D. Falls within JEDEC MO-50

12 MECHANICAL DATA MTSS00C JANUARY 995 REVISED FEBRUARY 999 PW (R-PDSO-G**) 4 PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,65 0,0 M 0,9 4 4,50 4,30 6,60 6,20 0,5 NOM Gage Plane A 7 0 0,25 0,75 0,50,20 MAX 0,5 0,05 Seating Plane 0,0 DIM PINS ** A MAX 3,0 5,0 5,0 6,60 7,90 9,0 A MIN 2,90 4,90 4,90 6,40 7,70 9, /F 0/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,5. D. Falls within JEDEC MO-53

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SN54HC00, SN74HC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES

SN54HC00, SN74HC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS181E DECEMBER 1982 REVISED AUGUST 2003 Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption,