SN54AHCT74, SN74AHCT74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

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1 Inputs Are TTL-Voltage ompatible Latch-Up Performance Exceeds 250 ma Per JESD 17 SN54AHT74, SN74AHT74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH LEAR AND PRESET SLS263N DEEMBER 1995 REVISED JULY 2003 ESD Protection Exceeds JESD V Human-Body Model (A1-A) 200-V Machine Model (A115-A) 1000-V harged-device Model (101) SN54AHT74...J OR W PAKAGE SN74AHT74... D, DB, DGV, N, NS, OR PW PAKAGE (TOP VIEW) 1LR 1D 1LK 1PRE 1Q 1Q GND V 2LR 2D 2LK 2PRE 2Q 2Q description/ordering information SN74AHT74... RGY PAKAGE (TOP VIEW) 1D 1LK 1PRE 1Q 1Q LR 2Q V GND LR 2D 2LK 2PRE 2Q 1LK N 1PRE N 1Q SN54AHT74... FK PAKAGE (TOP VIEW) 1D 1LR N V 2LR Q GND N 2Q 2Q N No internal connection 2D N 2LK N 2PRE The AHT74 dual positive-edge-triggered devices are D-type flip-flops. A low level at the preset (PRE) or clear (LR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and LR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. lock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. TA ORDERING INFORMATION PAKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING QFN RGY Tape and reel SN74AHT74RGYR HB74 PDIP N Tube SN74AHT74N SN74AHT74N Tube SN74AHT74D SOI D AHT74 Tape and reel SN74AHT74DR 40 to 85 SOP NS Tape and reel SN74AHT74NSR AHT74 SSOP DB Tape and reel SN74AHT74DBR HB74 TSSOP PW Tube Tape and reel SN74AHT74PW SN74AHT74PWR HB74 TVSOP DGV Tape and reel SN74AHT74DGVR HB74 DIP J Tube SNJ54AHT74J SNJ54AHT74J 55 to 125 FP W Tube SNJ54AHT74W SNJ54AHT74W L FK Tube SNJ54AHT74FK SNJ54AHT74FK Package drawings, standard packing quantities, thermal data, symbolization, and PB design guidelines are available at Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. opyright 2003, Texas Instruments Incorporated On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFIE BOX DALLAS, TEXAS

2 SN54AHT74, SN74AHT74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH LEAR AND PRESET SLS263N DEEMBER 1995 REVISED JULY 2003 logic diagram, each flip-flop (positive logic) PRE FUNTION TABLE (each flip-flop) INPUTS OUTPUTS PRE LR LK D Q Q L H X X H L H L X X L H L L X X H H H H H H L H H L L H H H L X Q0 Q0 This configuration is nonstable; that is, it does not persist when PRE or LR returns to its inactive (high) level. LK TG Q D TG TG TG Q LR 2 POST OFFIE BOX DALLAS, TEXAS 75265

3 SN54AHT74, SN74AHT74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH LEAR AND PRESET SLS263N DEEMBER 1995 REVISED JULY 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V V to 7 V Input voltage range, V I (see Note 1) V to 7 V Output voltage range, V O (see Note 1) V to V V Input clamp current, I IK (V I < 0) ma Output clamp current, I OK (V O < 0 or V O > V ) ±20 ma ontinuous output current, I O (V O = 0 to V ) ±25 ma ontinuous current through V or GND ±50 ma Package thermal impedance, θ JA (see Note 2): D package /W (see Note 2): DB package /W (see Note 2): DGV package /W (see Note 2): N package /W (see Note 2): NS package /W (see Note 2): PW package /W (see Note 3): RGY package /W Storage temperature range, T stg to 150 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD The package thermal impedance is calculated in accordance with JESD recommended operating conditions (see Note 4) SN54AHT74 SN74AHT74 UNIT MIN MAX MIN MAX V Supply voltage V VIH High-level input voltage 2 2 V VIL Low-level input voltage V VI Input voltage V VO Output voltage 0 V 0 V V IOH High-level output current 8 8 ma IOL Low-level output current 8 8 ma t/ v Input transition rise or fall rate ns/v TA Operating free-air temperature NOTE 4: All unused inputs of the device must be held at V or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating MOS Inputs, literature number SBA004. POST OFFIE BOX DALLAS, TEXAS

4 SN54AHT74, SN74AHT74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH LEAR AND PRESET SLS263N DEEMBER 1995 REVISED JULY 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST ONDITIONS V VOH VOL IOH = 50 A IOH = 8 ma IOL = 50 A IOL = 8 ma 45V V 4.5 TA = 25 SN54AHT74 SN74AHT74 MIN TYP MAX MIN MAX MIN MAX II VI = 5.5 V or GND 0 V to 5.5 V ±0.1 ±1* ±1 A I VI = V or GND, IO = V A I One input at 3.4 V, Other inputs at V or GND UNIT 5.5 V ma i VI = V or GND 5 V pf * On products compliant to MIL-PRF-38535, this parameter is not production tested at V = 0 V. This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or V. timing requirements over recommended operating free-air temperature range, V = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) tw tsu Pulse duration Setup time before LK PARAMETER TA = 25 SN54AHT74 SN74AHT74 MIN MAX MIN MAX MIN MAX PRE or LR low LK Data PRE or LR inactive th Hold time, data after LK ns V V UNIT ns ns switching characteristics over recommended operating free-air temperature range, V = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) FROM TO LOAD TA = 25 SN54AHT74 SN74AHT74 PARAMETER (INPUT) (OUTPUT) APAITANE MIN TYP MAX MIN MAX MIN MAX L = 15 pf 100** 160** 80** 80 fmax L = 50 pf tplh 7.6** 10.4** 1** 12** 1 12 PRE or LR QorQ Q L =15pF tphl 7.6** 10.4** 1** 12** 1 12 tplh 5.8** 7.8** 1** 9** 1 9 LK Q or Q L = 15 pf tphl 5.8** 7.8** 1** 9** 1 9 tplh PRE or LR Q or Q L = 50 pf tphl tplh LK Q or Q L = 50 pf tphl ** On products compliant to MIL-PRF-38535, this parameter is not production tested. UNIT MHz ns ns ns ns 4 POST OFFIE BOX DALLAS, TEXAS 75265

5 SN54AHT74, SN74AHT74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH LEAR AND PRESET SLS263N DEEMBER 1995 REVISED JULY 2003 noise characteristics, V = 5 V, L = 50 pf, T A = 25 (see Note 5) PARAMETER SN74AHT74 VOL(P) Quiet output, maximum dynamic VOL 0.8 V VOL(V) Quiet output, minimum dynamic VOL 0.8 V VOH(V) Quiet output, minimum dynamic VOH 4 V VIH(D) High-level dynamic input voltage 2 V VIL(D) Low-level dynamic input voltage 0.8 V NOTE 5: haracteristics are for surface-mount packages only. operating characteristics, V = 5 V, T A = 25 MIN MAX UNIT PARAMETER TEST ONDITIONS TYP UNIT pd Power dissipation capacitance No load, f = 1 MHz 32 pf POST OFFIE BOX DALLAS, TEXAS

6 SN54AHT74, SN74AHT74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH LEAR AND PRESET SLS263N DEEMBER 1995 REVISED JULY 2003 PARAMETER MEASUREMENT INFORMATION From Output Under Test L (see Note A) Test Point From Output Under Test L (see Note A) RL = 1 kω S1 V Open GND TEST tplh/tphl tplz/tpzl tphz/tpzh Open Drain S1 Open V GND V LOAD IRUIT FOR TOTEM-POLE OUTPUTS LOAD IRUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS Input tw 1.5 V 1.5 V 3 V 0 V Timing Input Data Input tsu 1.5 V th 1.5 V 1.5 V 3 V 0 V 3 V 0 V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Input 1.5 V 1.5 V 3 V 0 V Output ontrol 1.5 V 1.5 V 3 V 0 V In-Phase Output Out-of-Phase Output tplh tphl 50% V 50% V tphl VOH 50% V VOL tplh VOH 50% V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 1 S1 at V (see Note B) Output Waveform 2 S1 at GND (see Note B) tpzl tpzh 50% V 50% V tplz VOL V VOL tphz VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING V VOH VOH 0.3 V 0 V NOTES: A. L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 Ω, tr 3 ns, tf 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 1. Load ircuit and Voltage Waveforms 6 POST OFFIE BOX DALLAS, TEXAS 75265

8 MEHANIAL DATA MFP002A JANUARY 1995 REVISED FEBRUARY 2002 W (R-GDFP-F) ERAMI DUAL FLATPAK (1,) (0,66) (6,60) (5,97) Base and Seating Plane (2,03) (1,) (0,20) (0,10) (7,11) MAX (0,48) (0,38) (1,27) (9,91) (8,51) (0,13) MIN 4 Places (9,) (6,35) (9,) (6,35) / 02/02 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice.. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification only. E. Falls within MIL STD 1835 GDFP1-F and JEDE MO-092AB POST OFFIE BOX DALLAS, TEXAS 75265

9 MEHANIAL DATA ML006B OTOBER 1996 FK (S-Q-N**) 28 TERMINAL SHOWN LEADLESS ERAMI HIP ARRIER NO. OF TERMINALS ** MIN A MAX MIN B MAX (8,69) (9,09) (7,80) (9,09) A SQ B SQ (11,23) (16,26) (18,78) (23,83) 1.1 (28,99) (11,63) (16,76) (19,32) (24,43) (29,59) (10,31) (12,58) (12,58) (21,6) (26,6) (11,63) (,22) (,22) (21,8) (27,0) (0,51) (0,25) (2,03) (1,63) (0,51) (0,25) (1,40) (1,) (1,) (0,89) (0,71) (0,54) (1,27) (1,) (0,89) 40400/ D 10/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice.. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDE MS-004 POST OFFIE BOX DALLAS, TEXAS 75265

11 MEHANIAL DATA MPDS006 FEBRUARY 1996 REVISED AUGUST 2000 DGV (R-PDSO-G**) 24 PINS SHOWN PLASTI SMALL-OUTLINE 0,40 0,23 0,13 0,07 M ,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 1 12 A 0 8 0,25 0,75 0,50 1,20 MAX 0,15 0,05 Seating Plane 0,08 DIM PINS ** A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11, /E 08/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice.. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDE: 24/48 Pins MO-153 /16/20/56 Pins MO-194 POST OFFIE BOX DALLAS, TEXAS 75265

15 MEHANIAL DATA MSSO002E JANUARY 1995 REVISED DEEMBER 2001 DB (R-PDSO-G**) 28 PINS SHOWN PLASTI SMALL-OUTLINE 0,65 0,38 0,22 0,15 M ,60 5,00 8,20 7,40 0,25 0,09 Gage Plane 1 0,25 A 0 8 0,95 0,55 2,00 MAX 0,05 MIN Seating Plane 0,10 DIM PINS ** A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12, /E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice.. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDE MO-150 POST OFFIE BOX DALLAS, TEXAS 75265

16 MEHANIAL DATA MTSS001 JANUARY 1995 REVISED FEBRUARY 1999 PW (R-PDSO-G**) PINS SHOWN PLASTI SMALL-OUTLINE PAKAGE 0,30 0,65 0,10 M 0,19 8 4,50 4,30 6,60 6,20 0,15 NOM Gage Plane 1 A ,25 0,75 0,50 1,20 MAX 0,15 0,05 Seating Plane 0,10 DIM PINS ** A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9, /F 01/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice.. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDE MO-153 POST OFFIE BOX DALLAS, TEXAS 75265

17 IMPORTANT NOTIE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. ustomers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. ustomers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio Data onverters dataconverter.ti.com Automotive DSP dsp.ti.com Broadband Interface interface.ti.com Digital ontrol Logic logic.ti.com Military Power Mgmt power.ti.com Optical Networking Microcontrollers microcontroller.ti.com Security Telephony Video & Imaging Wireless Mailing Address: Texas Instruments Post Office Box Dallas, Texas opyright 2004, Texas Instruments Incorporated

CD54ACT74, CD74ACT74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

CD54ACT74, CD74ACT74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET s Are TTL-Voltage ompatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power onsumption Balanced Propagation Delays ±24-mA Drive urrent Fanout to 5 F Devices SR-Latchup-Resistant MOS Process