SN54ACT573, SN74ACT573 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

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1 4.5-V to 5.5-V V CC Operation Inputs Accept Voltages to 5.5 V Max t pd of 9.5 ns at 5 V Inputs Are TTL-Voltage Compatible description/ordering information These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches are D-type transparent latches. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines in a bus-organized system without need for interface or pullup components. SN54ACT573, SN74ACT573 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SCAS538D OCTOBER 1995 REVISED OCTOBER 2002 OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. TA ORDERING INFORMATION PACKAGE SN54ACT573...J OR W PACKAGE SN74ACT DB, DW, N, NS, OR PW PACKAGE (TOP VIEW) OE 1D 2D 3D 4D 5D 6D 7D 8D GND ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP N Tube SN74ACT573N SN74ACT573N Tube SN74ACT573DW SOIC DW ACT573 Tape and reel SN74ACT573DWR 40 C to85 C SOP NS Tape and reel SN74ACT573NSR ACT573 SSOP DB Tape and reel SN74ACT573DBR AD573 TSSOP PW Tape and reel SN74ACT573PWR AD573 CDIP J Tube SNJ54ACT573J SNJ54ACT573J 55 C to 125 C CFP W Tube SNJ54ACT573W SNJ54ACT573W LCCC FK Tube SNJ54ACT573FK SNJ54ACT573FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at V CC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q LE SN54ACT FK PACKAGE (TOP VIEW) 3D 4D 5D 6D 7D 2D 1D OE V CC 8D GND LE 8Q 7Q 1Q 2Q 3Q 4Q 5Q 6Q Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2002, Texas Instruments Incorporated On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX DALLAS, TEXAS

2 SN54ACT573, SN74ACT573 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SCAS538D OCTOBER 1995 REVISED OCTOBER 2002 FUNCTION TABLE (each latch) INPUTS OUTPUT OE LE D Q L H H H L H L L L L X Q0 H X X Z logic diagram (positive logic) OE 1 LE 11 1D 2 C1 1D 19 1Q To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V CC V to 7 V Input voltage range, V I (see Note 1) V to V CC V Output voltage range, V O (see Note 1) V to V CC V Input clamp current, I IK (V I < 0 or V I > V CC ) ±20 ma Output clamp current, I OK (V O < 0 or V O > V CC ) ±20 ma Continuous output current, I O (V O = 0 to V CC ) ±50 ma Continuous current through, V CC or GND ±200 ma Package thermal impedance, θ JA (see Note 2): DB package C/W DW package C/W N package C/W NS package C/W PW package C/W Storage temperature range, T stg C to 150 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD POST OFFICE BOX DALLAS, TEXAS 75265

3 SN54ACT573, SN74ACT573 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SCAS538D OCTOBER 1995 REVISED OCTOBER 2002 recommended operating conditions (see Note 3) SN54ACT573 SN74ACT573 MIN MAX MIN MAX VCC Supply voltage V VIH High-level input voltage 2 2 V VIL Low-level input voltage V VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V IOH High-level output current ma IOL Low-level output current ma t/ v Input transition rise or fall rate 8 8 ns/v TA Operating free-air temperature C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = 50 µa VOH IOH = 24 ma VOL TA = 25 C SN54ACT573 SN74ACT573 MIN TYP MAX MIN MAX MIN MAX 4.5 V V V V IOH = 50 ma 5.5 V 3.85 IOH = 75 ma 5.5 V 3.85 IOL =50µA IOL =24mA 4.5 V V V V IOL = 50 ma 5.5 V 1.65 IOL = 75 ma 5.5 V 1.65 IOZ VO = VCC or GND 5.5 V ±0.25 ±5 ±2.5 µa II VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µa ICC VI = VCC or GND, IO = V µa One input at 3.4 V, ICC Other inputs at GND or VCC UNIT UNIT 55V ma Ci VI = VCC or GND 5 V 5 pf Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms. This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC. timing requirements over recommended operating free-air temperature range, V CC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25 C SN54ACT573 SN74ACT573 MIN MAX MIN MAX MIN MAX tw Pulse duration, LE high ns tsu Setup time, data before LE ns th Hold time, data after LE ns V V UNIT POST OFFICE BOX DALLAS, TEXAS

4 SN54ACT573, SN74ACT573 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SCAS538D OCTOBER 1995 REVISED OCTOBER 2002 switching characteristics over recommended operating free-air temperature range, V CC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER tplh tphl tplh tphl tpzh tpzl tphz tplz FROM TO TA = 25 C SN54ACT573 SN74ACT573 (INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX D Q LE Q OE Q OE Q UNIT ns ns ns ns operating characteristics, V CC = 5 V, T A = 25 C PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance CL = 50 pf, f = 1 MHz 25 pf 4 POST OFFICE BOX DALLAS, TEXAS 75265

5 PARAMETER MEASUREMENT INFORMATION SN54ACT573, SN74ACT573 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SCAS538D OCTOBER 1995 REVISED OCTOBER 2002 From Output Under Test CL = 50 pf (see Note A) 500 Ω 500 Ω S1 2 VCC Open TEST tplh/tphl tplz/tpzl tphz/tpzh S1 Open 2 VCC Open Input Input Output LOAD CIRCUIT tw 3 V 1.5 V 1.5 V 0 V VOLTAGE WAVEFORMS 3 V 1.5 V 1.5 V 0 V tplh tphl VOH 50% VCC 50% VCC VOL VOLTAGE WAVEFORMS Timing Input Data Input Output Control (low-level enabling) Output Waveform 1 S1 at 2 VCC (see Note B) Output Waveform 2 S1 at Open (see Note B) tsu tpzl tpzh 1.5 V th 1.5 V 1.5 V VOLTAGE WAVEFORMS 1.5 V 1.5 V tplz 3 V 0 V 3 V 0 V 50% VCC VOL V VOL 50% VCC VOLTAGE WAVEFORMS tphz 3 V 0 V VCC VOH VOH 0.3 V 0 V NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 Ω, tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX DALLAS, TEXAS

6 PACKAGE OPTION ADDENDUM 8-Jun-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) A ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NC RA ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NC SA ACTIVE CFP W 20 TBD Call TI Level-NC-NC-NC SN74ACT573DBLE OBSOLETE SSOP DB 20 TBD Call TI Call TI SN74ACT573DBR ACTIVE SSOP DB Pb-Free SN74ACT573DBRE4 ACTIVE SSOP DB Pb-Free SN74ACT573DW ACTIVE SOIC DW Pb-Free SN74ACT573DWG4 ACTIVE SOIC DW Green (RoHS & no Sb/Br) SN74ACT573DWR ACTIVE SOIC DW Pb-Free SN74ACT573DWRG4 ACTIVE SOIC DW Green (RoHS & no Sb/Br) SN74ACT573N ACTIVE PDIP N Pb-Free SN74ACT573NE4 ACTIVE PDIP N Pb-Free SN74ACT573NSR ACTIVE SO NS Pb-Free SN74ACT573NSRE4 ACTIVE SO NS Pb-Free SN74ACT573PW ACTIVE TSSOP PW Pb-Free SN74ACT573PWE4 ACTIVE TSSOP PW Pb-Free SN74ACT573PWLE OBSOLETE TSSOP PW 20 TBD Call TI Call TI SN74ACT573PWR ACTIVE TSSOP PW Pb-Free SN74ACT573PWRE4 ACTIVE TSSOP PW Pb-Free Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-2-250C-1 YEAR/ Level-1-235C-UNLIM Level-1-260C-UNLIM Level-2-250C-1 YEAR/ Level-1-235C-UNLIM Level-1-260C-UNLIM Level-NC-NC-NC Level-NC-NC-NC Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-1-250C-UNLIM Level-1-250C-UNLIM Level-1-250C-UNLIM Level-1-250C-UNLIM SNJ54ACT573FK ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NC SNJ54ACT573J ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NC (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free or Green (RoHS & no Sb/Br) - please check for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free : TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame Addendum-Page 1

7 PACKAGE OPTION ADDENDUM 8-Jun-2005 retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

10 MECHANICAL DATA MLCC006B OCTOBER 1996 FK (S-CQCC-N**) 28 TERMINAL SHOWN LEADLESS CERAMIC CHIP CARRIER NO. OF TERMINALS ** MIN A MAX MIN B MAX (8,69) (9,09) (7,80) (9,09) A SQ B SQ (11,23) (16,26) (18,78) (23,83) (28,99) (11,63) (16,76) (19,32) (24,43) (29,59) (10,31) (12,58) (12,58) (21,6) (26,6) (11,63) (14,22) (14,22) (21,8) (27,0) (0,51) (0,25) (2,03) (1,63) (0,51) (0,25) (1,40) (1,14) (1,14) (0,89) (0,71) (0,54) (1,27) (1,14) (0,89) / D 10/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDEC MS-004 POST OFFICE BOX DALLAS, TEXAS 75265

14 MECHANICAL DATA MSSO002E JANUARY 1995 REVISED DECEMBER 2001 DB (R-PDSO-G**) 28 PINS SHOWN PLASTIC SMALL-OUTLINE 0,65 0,38 0,22 0,15 M ,60 5,00 8,20 7,40 0,25 0,09 Gage Plane ,25 A 0 8 0,95 0,55 2,00 MAX 0,05 MIN Seating Plane 0,10 DIM PINS ** A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12, /E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 POST OFFICE BOX DALLAS, TEXAS 75265

15 MECHANICAL DATA MTSS001C JANUARY 1995 REVISED FEBRUARY 1999 PW (R-PDSO-G**) 14 PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,65 0,10 M 0, ,50 4,30 6,60 6,20 0,15 NOM Gage Plane 1 A ,25 0,75 0,50 1,20 MAX 0,15 0,05 Seating Plane 0,10 DIM PINS ** A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9, /F 01/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153 POST OFFICE BOX DALLAS, TEXAS 75265

16 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio Data Converters dataconverter.ti.com Automotive DSP dsp.ti.com Broadband Interface interface.ti.com Digital Control Logic logic.ti.com Military Power Mgmt power.ti.com Optical Networking Microcontrollers microcontroller.ti.com Security Telephony Video & Imaging Wireless Mailing Address: Texas Instruments Post Office Box Dallas, Texas Copyright 2005, Texas Instruments Incorporated

SN54ALS1035, SN74ALS1035 HEX NONINVERTING BUFFERS WITH OPEN-COLLECTOR OUTPUTS

SN54ALS1035, SN74ALS1035 HEX NONINVERTING BUFFERS WITH OPEN-COLLECTOR OUTPUTS Noninverting Buffers With Open-Collector Outputs description These devices contain six independent noninverting buffers. They perform the Boolean function Y = A. The open-collector outputs require pullup